intersil X9241A DATA SHEET

®

www.BDTIC.com/Intersil

X9241A

Quad Digital Controlled Potentionmeters (XDCP™)

Data Sheet FN8164.6August 31, 2007

Non-Volatile/Low Power/2-Wire/64 Taps

The X9241A integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
microcircuit.

The digitally controlled potentiometer is implemented using
63 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. Each
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and 4 nonvolatile Data Registers
(DR0:DR3) that can be directly written to and read by the
user. The contents of the WCR controls the position of the
wiper on the resistor array through the switches. Power up
recalls the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.

Features

• Four potentiometers in one package

• 2-wire serial interface

• Register oriented format

- Direct read/write/transfer of wiper positions

- Store as many as four positions per potentiometer

• Terminal Voltages: +5V, -3.0V

• Cascade resistor arrays

• Low power CMOS

• High Reliability

- Endurance–100,000 data changes per bit per register

- Register data retention–100 years

• 16-bytes of nonvolatile memory

• 3 resistor array values

-2kΩ, 10kΩ, 50kΩ or combination

- Cascadable for values of 4kΩ to 200kΩ

• Resolution: 64 taps each pot

• 20 Ld plastic DIP, 20 Ld TSSOP and 20 Ld SOIC
packages

• Pb-free available (RoHS compliant)

Block Diagram

V

CC

V

SS

SCL

SDA

A0

A1

A2

A3

INTERFACE

AND

CONTROL

CIRCUITRY

DATA

/

V

R0

R1

WIPER
COUNTER
REGISTER

R3

R1

R3

(WCR)

WIPER
COUNTER
REGISTER

(WCR)

REGISTER

ARRAY

POT 1

R2

8

R0

R2

V

H0/RH0

VL0/R

VW0/R

V

H1/RH1

VL1/R
VW1/R

R0

R1

WIPER
COUNTER
REGISTER

L0

W0

L1

W1

R2

R0

R2

R3

R1

R3

(WCR)

WIPER
COUNTER
REGISTER

(WCR)

REGISTER

ARRAY

POT 2

REGISTER

ARRAY

POT 3

H2

R

H2

V

L2/RL2

VW2/R

VH3/R

VL3/R
VW3/R

W2

H3

L3

W3

1

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9241A

www.BDTIC.com/Intersil

Ordering Information

POTENTIOMETER

LIMITS

V

CC

PART NUMBER PART MARKING

X9241AMP X9241AMP 5 ±10% 2/10/50
X9241AMPZ (Note) X9241AMPZ 0 to +70 20 Ld PDIP*** (Pb-free)
X9241AMPI X9241AMPI -40 to +85 20 Ld PDIP
X9241AMPIZ (Note) X9241AMPIZ -40 to +85 20 Ld PDIP*** (Pb-free)
X9241AMS* X9241AMS 0 to +70 20 Ld SOIC
X9241AMSZ* (Note) X9241AMS Z 0 to +70 20 Ld SOIC (Pb-free)
X9241AMSI*
X9241AMSIZ* (Note) X9241AMSI Z -40 to +85 20 Ld SOIC (Pb-free)
X9241AMV X9241AM V 0 to +70 20 Ld TSSOP
X9241AMVZ (Note) X9241AM VZ 0 to +70 20 Ld TSSOP (Pb-free)
X9241AMVI*
X9241AMVIZ* (Note) X9241AM VIZ -40 to +85 20 Ld TSSOP (Pb-free)
X9241AWP X9241AWP 10
X9241AWPI X9241AWPI -40 to +85 20 Ld PDIP
X9241AWPIZ (Note) X9241AWPIZ -40 to +85 20 Ld PDIP*** (Pb-free)
X9241AWS*
X9241AWSZ* (Note) X9241AWS Z 0 to +70 20 Ld SOIC (Pb-free)
X9241AWSI*
X9241AWSIZ* (Note) X9241AWSI Z -40 to +85 20 Ld SOIC (Pb-free)
X9241AWV*
X9241AWVZ* (Note) X9241AW VZ 0 to +70 20 Ld TSSOP (Pb-free)
X9241AWVI*
X9241AWVIZ*
X9241AYP X9241AYP 2
X9241AYPZ (Note) X9241AYPZ 0 to +70 20 Ld PDIP*** (Pb-free)
X9241AYS* X9241AYS 0 to +70 20 Ld SOIC
X9241AYSZ* (Note) X9241AYS Z 0 to +70 20 Ld SOIC (Pb-free)
X9241AYSI* X9241AYSI -40 to +85 20 Ld SOIC
X9241AYSIZ* (Note) X9241AYSI Z -40 to +85 20 Ld SOIC (Pb-free)
X9241AYV X9241AY V 0 to +70 20 Ld TSSOP
X9241AYVZ (Note) X9241AY VZ 0 to +70 20 Ld TSSOP (Pb-free)
X9241AYVI*
X9241AYVIZ* (Note) X9241AY VIZ -40 to +85 20 Ld TSSOP (Pb-free)

,

** X9241AMSI -40 to +85 20 Ld SOIC

,

** X9241AM VI -40 to +85 20 Ld TSSOP

,

** X9241AWS 0 to +70 20 Ld SOIC

,

** X9241AWSI -40 to +85 20 Ld SOIC

,

** X9241AW V 0 to +70 20 Ld TSSOP

,

** X9241AW VI -40 to +85 20 Ld TSSOP

(Note) X9241AW VIZ -40 to +85 20 Ld TSSOP (Pb-free)

,

** X9241AY VI -40 to +85 20 Ld TSSOP

(V)

ORGANIZATION

Pot 0 = 2k
Pot 1 = 10k

Pot 2 = 10k
Pot 3 = 50k

Pot 0 = 10k
Pot 1 = 10k

Pot 2 = 10k
Pot 3 = 10k

Pot 0 = 2k
Pot 1 = 2k
Pot 2 = 2k

Pot 3 = 2k

(k)

TEMP RANGE

(°C) PACKAGE

0 to +70 20 Ld PDIP

0 to +70 20 Ld PDIP

0 to +70 20 Ld PDIP

2

FN8164.6

August 31, 2007

X9241A

www.BDTIC.com/Intersil

Ordering Information (Continued)

V

LIMITS

PART NUMBER PART MARKING

X9241AUP X9241AUP 5 ±10% 50
X9241AUPZ (Note) X9241AUPZ 0 to +70 20 Ld PDIP*** (Pb-free)
X9241AUPI X9241AUPI -40 to +85 20 Ld PDIP
X9241AUPIZ (Note) X9241AUPIZ -40 to +85 20 Ld PDIP*** (Pb-free)
X9241AUS X9241AUS 0 to +70 20 Ld SOIC
X9241AUSZ* (Note) X9241AUS Z 0 to +70 20 Ld SOIC (Pb-free)
X9241AUSI*
X9241AUSIZ* (Note) X9241AUSI Z -40 to +85 20 Ld SOIC (Pb-free)
X9241AUV* X9241AU V 0 to +70 20 Ld TSSOP
X9241AUVZ* (Note) X9241AU VZ 0 to +70 20 Ld TSSOP (Pb-free)
X9241AUVI*
X9241AUVIZ* (Note) X9241AU VIZ -40 to +85 20 Ld TSSOP (Pb-free)
*Add "T1" suffix for tape and reel.

**Add “T2” suffix for tape and reel.
***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%

matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.

,

** X9241AUSI -40 to +85 20 Ld SOIC

,

** X9241AU VI -40 to +85 20 Ld TSSOP

CC

(V)

POTENTIOMETER

ORGANIZATION

(k)

Pot 0 = 50k
Pot 1 = 50k
Pot 2 = 50k

Pot 3 = 50k

TEMP RANGE

(°C) PACKAGE

0 to +70 20 Ld PDIP

Pin Descriptions

Host Interface Pins
Serial Clock (SCL)

The SCL input is used to clock data into and out of the
X9241A.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wire­ORed with any number of open drain or open collector
outputs. An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the guidelines
for calculating typical values on the bus pull-up resistors
graph.

Address

The Address inputs are used to set the least significant
4-bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the Address
input in order to initiate communication with the X9241A.

Potentiometer Pins

VH/RH(VH0/RH0 TO VH3/RH3), VL/RL (VL0/RL0 TO VL3/RL3)

The R
connections on either end of a mechanical potentiometer.

V

The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.

and RL inputs are equivalent to the terminal

H

(VW0/RW0 TO VW3/RW3)

W/RW

Pinout

X9241A

TOP VIEW

1
2
3
4
5

X9241A

6
7
8
9
10

(20 LD DIP, SOIC, TSSOP)

VW0/RW0

VL0/RL0

V

H0/RH0

A0
A2

VW1/RW1

V

L1/RL1

V

H1/RH1

SDA
V

SS

Pin Names

SYMBOL DESCRIPTION

SCL Serial Clock
SDA Serial Data

A0 to A3 Address

V

V

to VH3/RH3,

H0/RH0

V

to VL3/R

L0/RL0

to VW3/RW3Potentiometer Pins (wiper equivalent)

W0/RW0

Potentiometer Pins (terminal equivalent)

L3

20
19
18
17
16
15
14
13
12

11

V

CC

V

W3/RW3

V

L3/RL3

V

H3/RH3

A1
A3

SCL
VW2/RW2
V

L2/RL2

V

H2/RH2

3

FN8164.6

August 31, 2007

X9241A

www.BDTIC.com/Intersil

Principles of Operation

The X9241A is a highly integrated microcircuit incorporating
four resistor arrays, their associated registers and counters
and the serial interface logic providing direct communication
between the host and the XDCP potentiometers.

Serial Interface

The X9241A supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9241A will be
considered a slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL
LOW periods (t
are reserved for indicating start and stop conditions.

Start Condition

All commands to the X9241A are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (t
SDA and SCL lines for the start condition and will not
respond to any command until this condition is met.

). SDA state changes during SCL HIGH

LOW

). The X9241A continuously monitors the

HIGH

At both ends of each array and between each resistor
segment is a FET switch connected to the wiper (V
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The 6 least significant bits of
the WCR are decoded to select, and enable, 1 of 64
switches.

The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR
can be read and written by the host system.

W/RW

)

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most significant
4-bits of the slave address are the device type identifier
(refer to Figure 1). For the X9241A, this is fixed as 0101[B].

DEVICE TYPE

IDENTIFIER

10 0 A3 A2 A1 A0

FIGURE 1. SLAVE ADDRESS

1

DEVICE ADDRESS

Stop Condition

All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH.

Acknowledge

Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting 8-bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the 8-bits of data. See Figure 7.

The X9241A will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9241A will
respond with a final acknowledge.

Array Description

The X9241A is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (V
and V

L/RL

inputs).

H/RH

The next 4-bits of the slave address are the device address.
The physical device address is defined by the state of the A0
to A3 inputs. The X9241A compares the serial data stream
with the address input state; a successful compare of all 4
address bits is required for the X9241A to respond with an
acknowledge.

Acknowledge Polling

The disabling of the inputs, during the internal nonvolatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the nonvolatile write command,
the X9241A initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9241A is still busy with the write operation, no ACK will be
returned. If the X9241A has completed the write operation,
an ACK will be returned and the master can then proceed
with the next operation.

4

FN8164.6

August 31, 2007

X9241A

www.BDTIC.com/Intersil

Flow 1. ACK Polling Sequence

NONVOLATILE WRITE

COMMAND COMPLETED

ENTER ACK POLLING

ISSUE

START

ISSUE SLAVE

ADDRESS

ACK

RETURNED?

YES

FURTHER

OPERATION?

YES

ISSUE

INSTRUCTION

PROCEED

NO

NO

ISSUE STOP

ISSUE STOP

PROCEED

The 4 high order bits define the instruction. The next 2-bits
(P1 and P0) select which one of the four potentiometers is to
be affected by the instruction. The last 2-bits (R1 and R0)
select one of the four registers that are to be acted upon
when a register oriented instruction is issued.

Four of the nine instructions end with the transmission of the
instruction byte. The basic sequence is illustrated in Figure 3.
These two-byte instructions exchange data between the WCR
and one of the data registers. A transfer from a Data R egister
to a WCR is essentially a write to a static RAM. The response
of the wiper to this action will be delayed t

STPWV

. A transfer
from WCR current wiper position to a Data Register is a write
to nonvolatile memory and takes a minimum of t

WR

to
complete. The transfer can occur between one of the four
potentiometers and one of its associated registers; or it may
occur globally , wherein the transfer occurs be tween all four of
the potentiometers and one of their associated registers.

Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9241A; either between the host and one of the Data
Registers or directly between the host and the WCR. These
instructions are: Read WCR, read the current wiper position
of the selected pot; Write WCR, change current wiper
position of the selected pot; Read Data Register, read the
contents of the selected nonvolatile register; Write Data
Register, write a new value to the selected Data Register.
The sequence of operations is shown in Figure 4.

Instruction Structure

The next byte sent to the X9241A contains the instruction
and register pointer information. The 4 most significant bits
are the instruction. The next 4-bits point to one of four pots
and when applicable they point to one of four associated
registers. The format is in Figure 2.

POTENTIOMETER

SELECT

I1I2I3 I0 P1 P0 R1 R0

INSTRUCTIONS

FIGURE 2. INSTRUCTION BYTE FORMAT

SCL

SDA

S

0101A3A2A1A0
T
A
R
T

REGISTER

SELECT

The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9241A has responded with an acknowledge, the master
can clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (t

) while SDA is HIGH, the

HIGH

selected wiper will move one resistor segment towards the
V

terminal. Similarly, for each SCL clock pulse while

H/RH

SDA is LOW, the selected wiper will move one resistor
segment towards the V

terminal. A detailed illustration

L/RL

of the sequence and timing for this operation is shown in
Figures 5 and 6 respectively.

I3 I2 I1 I0 P1 P0 R1 R0

A
C
K

S

A

T

C

O

K

P

FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE

5

FN8164.6

August 31, 2007