intersil X9221A DATA SHEET

®

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X9221A

64 Taps, 2-Wire Serial Bus

Data Sheet FN8163.2August 30, 2006

Dual Digitally Controlled Potentiometer
(XDCP™)

FEATURES

• Two XDCPs in one package

• 2-wire serial interface

• Register oriented format, 8 registers total
—Directly write wiper position
—Read wiper position
—Store as many as four positions per pot

• Instruction format
—Quick transfer of register contents to resistor

array

• Direct write cell
—Endurance–100,000 writes per bit per register

• Resistor array values
—2kΩ, 10kΩ, 50kΩ

• Resolution: 64 taps each pot

• 20 Ld plastic DIP and 20 Ld SOIC packages

• Pb-free plus anneal available (RoHS compliant)

BLOCK DIAGRAM

DESCRIPTION

The X9221A integrates two digitally controlled potenti­ometers (XDCP) on a monolithic CMOS integrated
microcircuit.

The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 2 non­volatile Data Registers (DR0:DR1) that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array through the switches. Power up recalls the con­tents of DR0 to the WCR.

The XDCP can be used as a three-terminal potentiom­eter or as a two-terminal variable resistor in a wide
variety of applications including control, parameter
adjustments, and signal processing.

V

CC

V

SS

SCL
SDA

A0
A1
A2

A3

Interface

and

Control

Circuitry

Data

Pot 0

R0

R1

Wiper
Counter
Register

R3

R1

R3

(WCR)

Wiper
Counter
Register

(WCR)

Register

Array
Pot 1

R2

8

R0

R2

V

H0/RH0

VL0/R
VW0/R

V

H1/RH1

VL1/R
VW1/R

L0

W0

L1

W1

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Inte

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

rsil Americas Inc. 2005-2006. All Rights Reserved

Ordering Information

www.BDTIC.com/Intersil

X9221A

V

LIMITS

PART NUMBER PART MARKING

X9221AYS X9221AYS 5 ±10% 2 0 to +70 20 Ld SOIC (300MIL) MDP0027
X9221AYSZ (Note) X9221AYS Z 0 to +70 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
X9221AYSI* X9221AYSI -40 to +85 20 Ld SOIC (300MIL) MDP0027
X9221AYSIZ* (Note) X9221AYSI Z -40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
X9221AWS* X9221AWS 10 0 to +70 20 Ld SOIC (300MIL) MDP0027
X9221AWSZ* (Note) X9221AWS Z 0 to +70 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
X9221AWSI* X9221AWSI -40 to +85 20 Ld SOIC (300MIL) MDP0027
X9221AWSIZ* (Note) X9221AWSI Z -40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
X9221AUP X9221AUP 50 0 to +70 20 Ld PDIP MDP0031
X9221AUPZ (Note) X9221AUPZ 0 to +70 20 Ld PDIP (Pb-Free) MDP0031
X9221AUPI X9221AUPI -40 to +85 20 Ld PDIP MDP0031
X9221AUPIZ (Note) X9221AUPIZ -40 to +85 20 Ld PDIP (Pb-Free) MDP0031
X9221AUSI* X9221AUSI -40 to +85 20 Ld SOIC (300MIL) MDP0027
X9221AUSIZ* (Note) X9221AUSI Z -40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-

100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

CC

(V) R

(k)

TOTAL

free material sets; molding compounds/die attach materials and

TEMP

R

ANGE (°C) PACKAGE

PKG.

DWG. #

PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)

The SCL input is used to clock data into and out of the
X9221A.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical val­ues, refer to the guidelines for calculating typical val­ues on the bus pull-up resistors graph.

Address

The Address inputs are used to set the least signifi­cant 4 bits of the 8-bit slave address. A match in the
slave address serial data stream must be made with
the Address input in order to initiate communication
with the X9221A

Potentiometer Pins

V

H/RH(VH0/RH0-VH1/RH1

The V

and VL/RL inputs are equivalent to the ter-

H/RH

), VL/RL (VL0/RL0-VL1/RL1)

minal connections on either end of a mechanical
potentiometer.

V

(VW0/RW0-VW1/RW1)

W/RW

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

PIN CONFIGURATION

DIP/SOIC

VW0/RW0

V

L0/RL0

V

H0/RL0

V

W1/RW1

V

L1/RL1

V

H1/RH1

SDA

V

A0

A2

SS

1

2

3

4

5

6

7

8

9

10

X9221A

20

19

18

17

16

15

14

13

12

11

V

CC

RES

RES

RES

A1

A3

SCL

RES

RES

RES

2

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August 30, 2006

X9221A

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PIN NAMES

Symbol Description

SCL Serial Clock

SDA Serial Data

A0–A3 Address

V

H0/RH0-VH1/RH1

V

L0/RH0-VL1/RL0

V

W0/RW0-VW1/RW1

RES Reserved (Do not connect)

,

Potentiometers
(terminal equivalent)

Potentiometers
(wiper equivalent)

PRINCIPLES OF OPERATION

The X9221A is a highly integrated microcircuit incor­porating two resistor arrays, their associated registers
and counters and the serial interface logic providing
direct communication between the host and the XDCP
potentiometers.

Serial Interface

The X9221A supports a bidirectional bus oriented pro­tocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and pro­vide the clock for both transmit and receive operations.
Therefore, the X9221A will be considered a slave
device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods (t

). SDA state changes during

LOW

SCL HIGH are reserved for indicating start and stop
conditions.

Start Condition

All commands to the X9221A are preceded by the
start condition, which is a HIGH to LOW transition of
SDA while SCL is HIGH (t

). The X9221A continu-

HIGH

ously monitors the SDA and SCL lines for the start
condition, and will not respond to any command until
this condition is met.

Stop Condition

All communications must be terminated by a stop con­dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data. See Figure 7.

The X9221A will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the com­mand byte. If the command is followed by a data byte
the X9221A will respond with a final acknowledge.

Array Description

The X9221A is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

and VL/RL inputs).

H/RH

At both ends of each array and between each resistor
segment is a FET switch connected to the wiper
(V

) output. Within each individual array only one

W/RW

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six least significant bits of the WCR are decoded to
select, and enable, one of sixty-four switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most signifi­cant four bits of the slave address are the device type
identifier (refer to Figure 1 below). For the X9221A this
is fixed as 0101[B].

Figure 1. Slave Address

Device Type

Identifier

10 0 A3 A2 A1 A0

1

Device Address

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August 30, 2006

X9221A

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The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0-A3 inputs. The X9221A compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9221A to respond with an acknowledge.

Acknowledge Polling

The disabling of the inputs, during the internal nonvol­atile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the
stop condition is issued to indicate the end of the non­volatile write command the X9221A initiates the inter­nal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9221A is
still busy with the write operation no ACK will be
returned. If the X9221A has completed the write oper­ation an ACK will be returned and the master can then
proceed with the next operation.

Flow 1. ACK Polling Sequence

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

YES

NO

Issue STOP

Instruction Structure

The next byte sent to the X9221A contains the instruc­tion and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of two pots and when applicable they
point to one of four associated registers. The format is
shown below in Figure 2.

Figure 2. Instruction Byte Format

t

Potentiometer

Select

I1I2I3 I0 0 P0 R1 R0

Instructions

Register

Select

The four high order bits define the instruction. The
sixth bit (P0) selects which one of the two potentiome­ters is to be affected by the instruction. The last two
bits (R1 and R0) select one of the four registers that is
to be acted upon when a register oriented instruction
is issued.

Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illus­trated in Figure 3. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a data register to a WCR is
essentially a write to a static RAM. The response of
the wiper to this action will be delayed t

STPWV

. A
transfer from WCR’s current wiper position to a data
register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

WR

between either potentiometer and their associated
registers or it may occur between both of the potenti­ometers and one of their associated registers.

Further

Operation?

NO

complete. These instructions transfer data between
the host and the X9221A; either between the host and
one of the data registers or directly between the host

Four instructions require a three-byte sequence to

YES

Issue

Instruction

Issue STOP

and the WCR. These instructions are: Read WCR,
read the current wiper position of the selected pot;
Write WCR, change current wiper position of the
selected pot; Read Data Register, read the contents of
the selected nonvolatile register; Write Data Register,

Proceed

Proceed

write a new value to the selected data register. The
sequence of operations is shown in Figure 4.

The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9221A has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine

4

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August 30, 2006

X9221A

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tuning capability to the host. For each SCL clock pulse

) while SDA is HIGH, the selected wiper will

(t

HIGH

move one resistor segment towards the V

H/RH

termi-

nal. Similarly, for each SCL clock pulse while SDA is

Figure 3. Two-Byte Command Sequence

SCL

SDA

0101A3A2A1A0

S

T
A
R

T

Figure 4. Three-Byte Command Sequence

SCL

SDA

LOW, the selected wiper will move one resistor seg­ment towards the V

terminal. A detailed illustra-

L/RL

tion of the sequence and timing for this operation are
shown in Figures 5 and 6 respectively.

I3 I2 I1 I0 0 P0 R1 R0

A
C
K

S

A

T

C

O

K

P

S

0 1 0 1 A3 A2 A1 A0
T
A
R
T

Figure 5. Increment/Decrement Command Sequined

e

SCL

SDA

S

0 1 0 1 A3 A2 A1 A0 I3 I2 I1 I0 0 P0 R1 R0
T
A
R

T

I3 I2 I1 I0 0 P0 R1 R0

A
C
K

A
C
K

0 0 D5 D4 D3 D2 D1 D0

A
C
K

XX

I

A
C
K

I

N

N

C

C

1

2

I

N
C

n

S

A

T

C

O

K

P

D
E

C

1

S

D

E

T

C

O

n

P

5

FN8163.2

August 30, 2006

Figure 6. Increment/Decrement Timing Limits

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INC/DEC

CMD

Issued

SCL

SDA

X9221A

t

CLWV

VW/R

W

Voltage Out

Table 1. Instruction Set

Instruction Format

Instruction

0P0R

0

Read WCR 1 0 0 1 0 1/0 N/A

R

1

0

(7)

N/A Read the contents of the Wiper Counter Register

pointed to by P

OperationI3I2I1I

0

Write WCR 1 0 1 0 0 1/0 N/A N/A Write new value to the Wiper Counter Register

pointed to by P

0

Read Data Register 1 0 1 1 0 1/0 1/0 1/0 Read the contents of the Register pointed to by

and R1–R

P

0

0

Write Data Register 1 1 0 0 0 1/0 1/0 1/0 Write new value to the Register pointed to by P0

and R

1–R0

XFR Data Register to
WCR

XFR WCR to Data
Register

Global XFR Data
Register to WCR

1 1 0 1 0 1/0 1/0 1/0 Transfer the contents of the Register pointed to

and R1–R0 to its associated WCR

by P

0

1 1 1 0 0 1/0 1/0 1/0 Transfer the contents of the WCR pointed to by

to the Register pointed to by R1–R

P

0

0

0 0 0 1 N/A N/A 1/0 1/0 Transfer the contents of the Data Registers

pointed to by R

of both pots to their

1–R0

respective WCR

Global XFR WCR
to Data Register

1 0 0 0 N/A N/A 1/0 1/0 Transfer the contents of all WCRs to their

respective data Registers pointed to by R

1–R0

of both pots

Increment/Decrement
Wiper

0 0 1 0 0 1/0 N/A N/A Enable Increment/decrement of the WCR point-

ed to by P

0

Note: (7) N/A = Not applicable or don’t care; that is, a data register is not involved in the operation and need not be addressed (typical)

6

FN8163.2

August 30, 2006

Figure 7. Acknowledge Response from Receiver

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SCL from

Master

Data Output

from Transmitter

Data Output

from Receiver

1

X9221A

89

START

DETAILED OPERATION

Both XDCP potentiometers share the serial interface
and share a common architecture. Each potentiometer
is comprised of a resistor array, a wiper counter regis­ter and four data registers. A detailed discussion of the
register organization and array operation follows.

Wiper Counter Register

The X9221A contains two wiper counter registers
(WCR), one for each XDCP potentiometer. The WCR
can be envisioned as a 6-bit parallel and serial load
counter with its outputs decoded to select one of sixty­four switches along its resistor array. The contents of
the WCR can be altered in four ways: it may be written
directly by the host via the Write WCR instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated data registers
via the XFR Data Register instruction (parallel load); it
can be modified one step at a time by the Increment/
Decrement instruction; finally, it is loaded with the con­tents of its data register zero (R0) upon power-up.

Acknowledge

The WCR is a volatile register; that is, its contents are
lost when the X9221A is powered-down. Although the
register is automatically loaded with the value in R0
upon power-up, it should be noted this may be differ­ent from the value present at power-down.

Data Registers

Each potentiometer has four nonvolatile data regis­ters. These can be read or written directly by the host
and data can be transferred between any of the four
data registers and the WCR. It should be noted all
operations changing data in one of these registers is a
nonvolatile operation and will take a maximum of
10ms.

If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.

7

FN8163.2

August 30, 2006

Figure 8. Detailed Potentiometer Block Diagram

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X9221A

Serial Data Path

From Interface

Circuitry

Register 0 Register 1

Register 2 Register 3

If WCR = 00[H] then VW/RW = VL/RL

If WCR = 3F[H] then V

W/RW

= VH/R

Serial
Bus

Input

8 6

UP/DN

H

Modified SCL

Parallel
Bus

Input

Wiper

Counter

Register

INC/DEC

UP/DN

CLK

Logic

C
o
u
n

t

e

r

D
e
c
o
d
e

VH/R

VL/R

VW/R

H

L

W

8

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August 30, 2006

X9221A

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ABSOLUTE MAXIMUM RATINGS

Temperature Under Bias ................... -65°C to +135°C

Storage Temperature ........................ -65°C to +150°C

Voltage on SCK, SCL or Any Address

Input With Respect to V

Voltage on Any V

Referenced to V

ΔV = |V

H/RH–VL/RL

H/RH

SS

................................. +6V / -4.3V

|........................................... 10.3V

...................... -1V to +7V

SS

, VW/RW or VL/RL

Lead Temperature (soldering, 10s) ................. +300°C

(10s) ..............................................................±6mA

I

W

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
indicated in the operational sections of this specifica­tion) is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C+70°C

Industrial -40°C+85°C

Supply Voltage Limits

X9221A 5V ± 10%

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Limits

Symbol Parameter

R

TOTAL

I

W

R

W

V

TERM

C

H/CL/CW

End to End Resistance -20 +20 %

Power Rating 50 mW +25°C, each pot

Wiper Current -3 +3 mA

Wiper Resistance 40 130 Ω Wiper Current = ±1mA

Voltage on any VH/RH, VW/RW or

Pin

V

L/RL

Noise ≤120 dBV Ref: 1V

Resolution 1.6 % See Note 5

Absolute Linearity

Relative Linearity

Temperature Coefficient ±300 ppm/°C See Note 5

Radiometric Temperature Coefficient ±20 ppm/°C See Note 5

Potentiometer Capacitances 10/10/25 pF See circuit #3

(1)

(2)

-3.0 +5 V

-1 +1 MI

-0.2 +0.2 MI

(3)

(3)

Test ConditionsMin. Typ. Max. Unit

V

w(n)(actual - Vw(n)(expected)

V

w(n + 1)

- [V

w(n) + MI

]

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August 30, 2006

X9221A

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D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Limits

Symbol Parameter

l

CC

I

SB

I

LI

I

LO

V

IH

V

IL

V

OL

Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as

Supply Current (Active) 3 mA f

= 100kHz, SDA = Open, Other Inputs = V

SCL

VCC Current (Standby) 200 500 µA SCL = SDA = VCC, Addr. = V

Input Leakage Current 10 µA VIN = VSS to V

Output Leakage Current 10 µA V

= VSS to V

OUT

Input HIGH Voltage 2 VCC + 1 V

Input LOW Voltage -1 0.8 V

Output LOW Voltage 0.4 V IOL = 3mA

a potentiometer.

(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-

ometer. It is a measure of the error in step size.

(3) MI = RTOT/63 or (V

H/RH–VL/RL

)/63, single pot

ENDURANCE AND DATA RETENTION

Parameter Min. Unit

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 years

Test ConditionsMin. Typ. Max. Unit

SS

SS

CC

CC

CAPACITANCE

Symbol Parameter Max. Unit Test Conditions

(5)

C

I/O

(5)

C

IN

Input/output capacitance (SDA) 8 pF V

I/O

= 0V

Input capacitance (A0, A1, A2, A3 and SCL) 6 pF VIN = 0V

POWER-UP TIMING

Symbol Parameter Min. Max. Unit

(6)

t

PUR

(6)

t

PUW

t

RVCC

Notes: (5) This parameter is periodically sampled and not 100% tested.

(6) t

PUR

periodically sampled and not 100% tested.

Power-up to initiation of read operation 1 ms

Power-up to initiation of write operation 5 ms

VCC Power-up ramp rate 0.2 50 V/ms

and t

are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are

PUW

Power Up Requirements (Power up sequencing can affect correct recall of the wiper registers)

The preferred power-on sequence is as follows: First V

, then the potentiometer pins. It is suggested that V

CC

CC

reach 90% of its final value before power is applied to the potentiometer pins. The VCC ramp rate specification should
be met, and any glitches or slope changes in the V

line should be held to <100mV if possible. Also, VCC should not

CC

reverse polarity by more than 0.5V.

10

FN8163.2

August 30, 2006

A.C. CONDITIONS OF TEST

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Input pulse levels VCC x 0.1 to VCC x 0.9

Input rise and fall times 10ns

Input and output timing levels V

CC

x 0.5

SYMBOL TABLE

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from LOW
to HIGH

May change
from HIGH
to LOW

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from LOW
to HIGH

Will change
from HIGH
to LOW

Changing:
State Not
Known

is High
Impedance

X9221A

Circuit #3 SPICE Macro Model

Macro Model

R

10pF

C

TOTAL

H

R

C

25pF

W

R

L

C

L

10pF

W

R

H

Guidelines for Calculating Typical Values of Bus
Pull-Up R

esistors

Equivalent A.C. Test Circuit

SDA Output

5V

1533Ω

100pF

120

100

80

60

40

Resistance (kΩ)

20

Min.
Resistance

0

20 40 60 80

0

Bus Capacitance (pF)

V

R

=

MIN

I

R

=

MAX

C

Max.
Resistance

CC MAX

OL MIN

t

R

BUS

=1.8kΩ

100

120

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FN8163.2

August 30, 2006

X9221A

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A.C. CHARACTERISTICS

(Over recommended operating conditions unless otherwise stated)

Symbol Parameter

f

SCL

t

LOW

t

HIGH

t

R

t

F

T

i

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

AA

t

DH

t

SU:STO

t

BUF

t

WR

t

STPWV

t

CLWV

SCL clock frequency 0 100 kHz 10

Clock LOW period 4700 ns 10

Clock HIGH period 4000 ns 10

SCL and SDA rise time 1000 ns 10

SCL and SDA fall time 300 ns 10

Noise suppression time constant (glitch filter) 100 ns 10

Start condition setup time (for a repeated start condition) 4700 ns 10 & 12

Start condition hold time 4000 ns 10 & 12

Data in setup time 250 ns 10

Data in hold time 0 ns 10

SCL LOW to SDA data out valid 300 3500 ns 11

Data out hold time 300 ns 11

Stop condition setup time 4700 ns 10 & 12

Bus free time prior to new transmission 4700 ns 10

Write cycle time (nonvolatile write operation) 10 ms 13

Wiper response time from stop generation 1000 µs 13

Wiper response from SCL LOW 500 µs 6

Limits

Unit

Reference

FigureMin. Max.

TIMING DIAGRAMS

Figure 10. Input Bus Timing

t

HIGH

SCL

t

SU:STA

SDA

(Data in)

Figure 11. Output Bus Timing

SCL

SDA

t

HD:STAtHD:DAT

SDA

OUT

t

LOW

t

AA

(ACK) SDA

t

DH

OUT

t

SU:DAT

t

F

SDA

OUT

t

R

t

SU:STO

t

BUF

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FN8163.2

August 30, 2006

Figure 12. Start Stop Timing

www.BDTIC.com/Intersil

SCL

X9221A

STOP Condition START Condition

t

HD:STA

SDA

(Data in)

t

SU:STA

Figure 13. Write Cycle and Wiper Response Timing

SCL

SDA

Wiper

Output

SDA

Clock 8

IN

Clock 9

ACK

STOP

t

SU:STO

t

STPWV

t

START

WR

13

FN8163.2

August 30, 2006

Small Outline Package Family (SO)

www.BDTIC.com/Intersil

A

D

NN

(N/2)+1

X9221A

h X 45°

PIN #1

E

C

SEATING
PLANE

0.004 C

E1

B

0.010 BM CA

I.D. MARK

1

e

0.010 BM CA

(N/2)

c

SEE DETAIL “X”

L1

H

A2

GAUGE
PLANE

A1

b

DETAIL X

L

4° ±4°

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL SO-8 SO-14

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28) TOLERANCE NOTES

A

0.010

Rev. L 2/01

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August 30, 2006

Plastic Dual-In-Line Packages (PDIP)

www.BDTIC.com/Intersil

X9221A

SEATING
PLANE

D

A2

A

L

L

e

b

A1

NOTE 5

c

E

eA

eB

N

PIN #1

E1

INDEX

12 N/2

b2

MDP0031

PLASTIC DUAL-IN-LINE PACKAGE

SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE NOTES

A 0.210 0.210 0.210 0.210 0.210 MAX

A1 0.015 0.015 0.015 0.015 0.015 MIN

A2 0.130 0.130 0.130 0.130 0.130 ±0.005

b 0.018 0.018 0.018 0.018 0.018 ±0.002

b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015

c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002

D 0.375 0.750 0.750 0.890 1.020 ±0.010 1

E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010

E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2

e 0.100 0.100 0.100 0.100 0.100 Basic

eA 0.300 0.300 0.300 0.300 0.300 Basic

eB 0.345 0.345 0.345 0.345 0.345 ±0.025

L 0.125 0.125 0.125 0.125 0.125 ±0.010

N 8 14 16 18 20 Reference

NOTES:

1. Plastic or metal protrusions of 0.010” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.

4. Dimension eB is measured with the lead tips unconstrained.

5. 8 and 16 lead packages have half end-leads as shown.

Rev. B 2/99

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

15

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August 30, 2006