intersil X9221A DATA SHEET

®

www.BDTIC.com/Intersil

X9221A

64 Taps, 2-Wire Serial Bus

Data Sheet FN8163.2August 30, 2006

Dual Digitally Controlled Potentiometer
(XDCP™)

FEATURES

• Two XDCPs in one package

• 2-wire serial interface

• Register oriented format, 8 registers total
—Directly write wiper position
—Read wiper position
—Store as many as four positions per pot

• Instruction format
—Quick transfer of register contents to resistor

array

• Direct write cell
—Endurance–100,000 writes per bit per register

• Resistor array values
—2kΩ, 10kΩ, 50kΩ

• Resolution: 64 taps each pot

• 20 Ld plastic DIP and 20 Ld SOIC packages

• Pb-free plus anneal available (RoHS compliant)

BLOCK DIAGRAM

DESCRIPTION

The X9221A integrates two digitally controlled potenti­ometers (XDCP) on a monolithic CMOS integrated
microcircuit.

The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 2 non­volatile Data Registers (DR0:DR1) that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array through the switches. Power up recalls the con­tents of DR0 to the WCR.

The XDCP can be used as a three-terminal potentiom­eter or as a two-terminal variable resistor in a wide
variety of applications including control, parameter
adjustments, and signal processing.

V

CC

V

SS

SCL
SDA

A0
A1
A2

A3

Interface

and

Control

Circuitry

Data

Pot 0

R0

R1

Wiper
Counter
Register

R3

R1

R3

(WCR)

Wiper
Counter
Register

(WCR)

Register

Array
Pot 1

R2

8

R0

R2

V

H0/RH0

VL0/R
VW0/R

V

H1/RH1

VL1/R
VW1/R

L0

W0

L1

W1

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Inte

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

rsil Americas Inc. 2005-2006. All Rights Reserved

Ordering Information

www.BDTIC.com/Intersil

X9221A

V

LIMITS

PART NUMBER PART MARKING

X9221AYS X9221AYS 5 ±10% 2 0 to +70 20 Ld SOIC (300MIL) MDP0027
X9221AYSZ (Note) X9221AYS Z 0 to +70 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
X9221AYSI* X9221AYSI -40 to +85 20 Ld SOIC (300MIL) MDP0027
X9221AYSIZ* (Note) X9221AYSI Z -40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
X9221AWS* X9221AWS 10 0 to +70 20 Ld SOIC (300MIL) MDP0027
X9221AWSZ* (Note) X9221AWS Z 0 to +70 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
X9221AWSI* X9221AWSI -40 to +85 20 Ld SOIC (300MIL) MDP0027
X9221AWSIZ* (Note) X9221AWSI Z -40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
X9221AUP X9221AUP 50 0 to +70 20 Ld PDIP MDP0031
X9221AUPZ (Note) X9221AUPZ 0 to +70 20 Ld PDIP (Pb-Free) MDP0031
X9221AUPI X9221AUPI -40 to +85 20 Ld PDIP MDP0031
X9221AUPIZ (Note) X9221AUPIZ -40 to +85 20 Ld PDIP (Pb-Free) MDP0031
X9221AUSI* X9221AUSI -40 to +85 20 Ld SOIC (300MIL) MDP0027
X9221AUSIZ* (Note) X9221AUSI Z -40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-

100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

CC

(V) R

(k)

TOTAL

free material sets; molding compounds/die attach materials and

TEMP

R

ANGE (°C) PACKAGE

PKG.

DWG. #

PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)

The SCL input is used to clock data into and out of the
X9221A.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical val­ues, refer to the guidelines for calculating typical val­ues on the bus pull-up resistors graph.

Address

The Address inputs are used to set the least signifi­cant 4 bits of the 8-bit slave address. A match in the
slave address serial data stream must be made with
the Address input in order to initiate communication
with the X9221A

Potentiometer Pins

V

H/RH(VH0/RH0-VH1/RH1

The V

and VL/RL inputs are equivalent to the ter-

H/RH

), VL/RL (VL0/RL0-VL1/RL1)

minal connections on either end of a mechanical
potentiometer.

V

(VW0/RW0-VW1/RW1)

W/RW

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

PIN CONFIGURATION

DIP/SOIC

VW0/RW0

V

L0/RL0

V

H0/RL0

V

W1/RW1

V

L1/RL1

V

H1/RH1

SDA

V

A0

A2

SS

1

2

3

4

5

6

7

8

9

10

X9221A

20

19

18

17

16

15

14

13

12

11

V

CC

RES

RES

RES

A1

A3

SCL

RES

RES

RES

2

FN8163.2

August 30, 2006

X9221A

www.BDTIC.com/Intersil

PIN NAMES

Symbol Description

SCL Serial Clock

SDA Serial Data

A0–A3 Address

V

H0/RH0-VH1/RH1

V

L0/RH0-VL1/RL0

V

W0/RW0-VW1/RW1

RES Reserved (Do not connect)

,

Potentiometers
(terminal equivalent)

Potentiometers
(wiper equivalent)

PRINCIPLES OF OPERATION

The X9221A is a highly integrated microcircuit incor­porating two resistor arrays, their associated registers
and counters and the serial interface logic providing
direct communication between the host and the XDCP
potentiometers.

Serial Interface

The X9221A supports a bidirectional bus oriented pro­tocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and pro­vide the clock for both transmit and receive operations.
Therefore, the X9221A will be considered a slave
device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods (t

). SDA state changes during

LOW

SCL HIGH are reserved for indicating start and stop
conditions.

Start Condition

All commands to the X9221A are preceded by the
start condition, which is a HIGH to LOW transition of
SDA while SCL is HIGH (t

). The X9221A continu-

HIGH

ously monitors the SDA and SCL lines for the start
condition, and will not respond to any command until
this condition is met.

Stop Condition

All communications must be terminated by a stop con­dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data. See Figure 7.

The X9221A will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the com­mand byte. If the command is followed by a data byte
the X9221A will respond with a final acknowledge.

Array Description

The X9221A is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

and VL/RL inputs).

H/RH

At both ends of each array and between each resistor
segment is a FET switch connected to the wiper
(V

) output. Within each individual array only one

W/RW

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six least significant bits of the WCR are decoded to
select, and enable, one of sixty-four switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most signifi­cant four bits of the slave address are the device type
identifier (refer to Figure 1 below). For the X9221A this
is fixed as 0101[B].

Figure 1. Slave Address

Device Type

Identifier

10 0 A3 A2 A1 A0

1

Device Address

3

FN8163.2

August 30, 2006

X9221A

www.BDTIC.com/Intersil

The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0-A3 inputs. The X9221A compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9221A to respond with an acknowledge.

Acknowledge Polling

The disabling of the inputs, during the internal nonvol­atile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the
stop condition is issued to indicate the end of the non­volatile write command the X9221A initiates the inter­nal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9221A is
still busy with the write operation no ACK will be
returned. If the X9221A has completed the write oper­ation an ACK will be returned and the master can then
proceed with the next operation.

Flow 1. ACK Polling Sequence

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

YES

NO

Issue STOP

Instruction Structure

The next byte sent to the X9221A contains the instruc­tion and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of two pots and when applicable they
point to one of four associated registers. The format is
shown below in Figure 2.

Figure 2. Instruction Byte Format

t

Potentiometer

Select

I1I2I3 I0 0 P0 R1 R0

Instructions

Register

Select

The four high order bits define the instruction. The
sixth bit (P0) selects which one of the two potentiome­ters is to be affected by the instruction. The last two
bits (R1 and R0) select one of the four registers that is
to be acted upon when a register oriented instruction
is issued.

Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illus­trated in Figure 3. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a data register to a WCR is
essentially a write to a static RAM. The response of
the wiper to this action will be delayed t

STPWV

. A
transfer from WCR’s current wiper position to a data
register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

WR

between either potentiometer and their associated
registers or it may occur between both of the potenti­ometers and one of their associated registers.

Further

Operation?

NO

complete. These instructions transfer data between
the host and the X9221A; either between the host and
one of the data registers or directly between the host

Four instructions require a three-byte sequence to

YES

Issue

Instruction

Issue STOP

and the WCR. These instructions are: Read WCR,
read the current wiper position of the selected pot;
Write WCR, change current wiper position of the
selected pot; Read Data Register, read the contents of
the selected nonvolatile register; Write Data Register,

Proceed

Proceed

write a new value to the selected data register. The
sequence of operations is shown in Figure 4.

The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9221A has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine

4

FN8163.2

August 30, 2006

X9221A

www.BDTIC.com/Intersil

tuning capability to the host. For each SCL clock pulse

) while SDA is HIGH, the selected wiper will

(t

HIGH

move one resistor segment towards the V

H/RH

termi-

nal. Similarly, for each SCL clock pulse while SDA is

Figure 3. Two-Byte Command Sequence

SCL

SDA

0101A3A2A1A0

S

T
A
R

T

Figure 4. Three-Byte Command Sequence

SCL

SDA

LOW, the selected wiper will move one resistor seg­ment towards the V

terminal. A detailed illustra-

L/RL

tion of the sequence and timing for this operation are
shown in Figures 5 and 6 respectively.

I3 I2 I1 I0 0 P0 R1 R0

A
C
K

S

A

T

C

O

K

P

S

0 1 0 1 A3 A2 A1 A0
T
A
R
T

Figure 5. Increment/Decrement Command Sequined

e

SCL

SDA

S

0 1 0 1 A3 A2 A1 A0 I3 I2 I1 I0 0 P0 R1 R0
T
A
R

T

I3 I2 I1 I0 0 P0 R1 R0

A
C
K

A
C
K

0 0 D5 D4 D3 D2 D1 D0

A
C
K

XX

I

A
C
K

I

N

N

C

C

1

2

I

N
C

n

S

A

T

C

O

K

P

D
E

C

1

S

D

E

T

C

O

n

P

5

FN8163.2

August 30, 2006