intersil X9119 DATA SHEET

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X9119

Single Supply/Low Power/1024-Tap/2-Wire Bus

Data Sheet July 9, 2008

Single Digitally-Controlled (XDCP™) Potentiometer

The X9119 integrates a single digitally controlled potentiometer (XDCP™) on a monolithic CMOS integrated circuit.

The digital controlled potentiometer is implemented using 1023 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR.

The XDCP™ can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

FN8162.4

Features

• 1024 Resistor Taps – 10-Bit Resolution

• 2-Wire Serial Interface for Write, Read, and Transfer Operations of the Potentiometer

• Wiper Resistance, 40Ω Typical @ VCC = 5V

• Four Non-Volatile Data Registers

• Non-Volatile Storage of Multiple Wiper Positions

• Power-on Recall. Loads Saved Wiper Position on Power-up.

• Standby Current < 3µA Max

: 2.7V to 5.5V Operation

•V

•100kΩ End-to-End Resistance

• 100 yr. Data Retention

• Endurance: 100,000 Data Changes Per Bit Per Register

• 14 Ld TSSOP

• Low Power CMOS

• Single Supply Version of the X9118

Functional Diagram

ADDRESS

2-WIRE

BUS

INTERFACE

STATUS

DATA

BUS

INTERFACE

AND

CONTROL

WRITE

READ

TRANSFER

CONTROL

NC NC

• Pb-Free available (RoHS compliant)

POWER-ON RECALL

WIPER COUNTER REGISTER (WCR)

WIPER

DATA REGISTERS

(DR0-DR3)

100kΩ 1024-TAPS

POT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners

Ordering Information

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X9119

POTENTIOMETER

PART

PART NUMBER

X9119TV14I X9119 TVI 5 ±10% 100 -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9119TV14IZ (Note) X9119 TVZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9119TV14 X9119 TV 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9119TV14Z (Note) X9119 TVZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9119TV14-2.7* X9119 TVF 2.7 to 5.5 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9119TV14Z-2.7* (Note) X9119 TVZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9119TV14I-2.7 X9119 TVG -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9119TV14IZ-2.7* (Note) X9119 TVZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173

*Add "T1" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach

materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING

LIMITS

(V)

ORGANIZATION

(kΩ)

TEMP

RANGE

(°C) PACKAGE

PKG. DWG.#

Detailed Functional Diagram

POWER ON

RECALL

SCL

SDA

INTERFACE

AND

CONTROL

CIRCUITRY

DATA

CONTROL

DR0 DR1

DR2 DR3

WIPER COUNTER REGISTER

(WCR)

100KΩ 1024-TAPS

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July 9, 2008

Applications

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Circuit Level

• Vary the gain of a voltage amplifier

• Provide programmable DC reference voltages for comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the DC biasing of a pin diode attenuator in RF circuits

• Provide a control variable (I, V, or R) in feedback circuits

System Level

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in communication systems

• Set and regulate the DC biasing point in an RF power amplifier in wireless systems

• Control the gain in audio and home entertainment systems

• Provide the variable DC bias for tuners in RF wireless systems

• Set the operating points in temperature control systems

• Control the operating point for sensors in industrial systems

• Trim offset and gain errors in artificial intelligent systems

Pinout

X9119

(14 LD TSSOP)

TOP VIEW

SCL

SDA

NC A1

9 8

X9119

Pin Assignments

NUMBER PIN NAME FUNCTION

1, 3, 10 NC No Connect

2 A0 Device Address for 2-wire bus 4 A2 Device Address for 2-wire bus 5 SCL Serial Clock for 2-wire bus 6 SDA Serial Data Input/Output for 2-wire bus 7V 8WP

9 A1 Device Address for 2-wire bus 11 R 12 R 13 R 14 V

System Ground

Hardware Write Protect

Wiper terminal of the Potentiometer

High terminal of the Potentiometer

Low terminal of the Potentiometer

System Supply Voltage

Bus Interface Pins

SERIAL DATA INPUT/OUTPUT (SDA)

The SDA is a bidirectional serial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from an 2-wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL.

It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph.

SERIAL CLOCK (SCL)

This input is used by 2-wire master to supply 2-wire serial clock to the X9119.

DEVICE ADDRESS (A

The Address inputs are used to set the least significant 3 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9119. A maximum of 8 devices may occupy the 2-wire serial bus.

HARDWARE WRITE PROTECT INPUT (WP

The WP

pin when LOW prevents nonvolatile writes to the

Data Registers.

2–A0

)

Potentiometer Pins

RH, RL

The R connections on a mechanical potentiometer.

and RL pins are equivalent to the terminal

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X9119

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The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer.

Bias Supply Pins

SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (V

The V

)

pin is the system supply voltage. The VSS pin is

the system ground.

Other Pins

NO CONNECT

No connect pins should be left open. These pins are used for Intersil manufacturing and testing purposes.

Principals of Operation

The X9119 is an integrated microcircuit incorporating a resistor array and its associated registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometer. This section provides detail description of the following:

• Resistor Array Description

• Serial Interface Description

• Instruction and Register Descripti o n

Resistor Array Description

The X9119 is comprised of a resistor array. The array contains, in effect, 1023 discrete resistive segments that are connected in series (Figure 1). The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R

and RL inputs).

At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select, and enable, one of 1024 switches.

The WCR may be written directly. The Data Registers and the WCR can be read and written by the host system.

Serial Interface Description

SERIAL INTERFACE

The X9119 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9119 will be considered a slave device in all applications.

CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figure 3).

START CONDITION

All commands to the X9119 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9119 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met (Figure 3).

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

IF WCR = 000[HEX] THEN RW = R IF WCR = 3FF[HEX] THEN RW = R

FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM SERIAL INTERFACE DESCRIPTION

(DR0)

(DR2)

L H

(DR1)

10 10

(DR3)

SERIAL BUS INPUT

PARALLEL

BUS INPUT

WIPER

COUNTER

(WCR)

C O U N T E R

D E C O D E R

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X9119

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STOP CONDITION

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 3).

ACKNOWLEDGE

Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ST AR T

FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER

release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data.

The X9119 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9119 will respond with a final acknowledge (see Figure 2).

ACKNOWLEDGE

ACKNOWLEDGE POLLING

The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9119 initiates the internal write cycle. ACK polling, Flow 1, can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9119 is still busy with the write operation, no ACK will be returned. If the X91 19 has completed the write operation, an ACK will be returned and the master can then proceed with the next operation.

FLOW 1. ACK Polling Sequence

NONVOLATILE WRITE

COMMAND COMPLETED

ENTERACK POLLING

ISSUE

START

ISSUE SLAVE

ADDRESS

ACK

RETURNED?

YES

FURTHER

OPERATION?

YES

ISSUE

INSTRUCTION

ISSUE STOP

PROCEED

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X9119

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Instruction and Register Description

slave address matches the incoming device address sent by the master executes the instruction. The A2–A0 inputs can

Device Addressing: Identification Byte (ID and A)

Following a start condition, the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier. The ID[3:0] bits is the device id for the X9119; this is fixed as 0101[B] (refer to Table 1).

The A2–A0 bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A2–A0 input pins. The slave address is externally specified by the user. The X9119 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9119 to successfully

be actively driven by CMOS input signals or tied to V V

. The R/W bit is the LSB and is be used to program the

device for read or write operations.

INSTRUCTION BYTE AND REGISTER SELECTION

The next byte sent to the X9119 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (IOP[2:0]). The RB and RA bits point to one of the four registers. The format is shown below in Table 2.

Table 3 provides a complete summary of the instruction set opcodes.

continue the command sequence. Only the device which

TABLE 1. IDENTIFICATION BYTE FORMAT

DEVICE TYPE

IDENTIFIES

ID3 ID2 ID1 ID0 A2 A1 A0 R/W

0101

(MSB) (LSB)

INTERNAL SLAVE

ADDRESS

READ OR

WRITE BIT

TABLE 2. INSTRUCTION BYTE FORMAT

INSTRUCTION

OPCODE

I2 I1 I0 0 RB RA 0 0

(MSB) (LSB)

DR0 0 0 DR1 0 1 DR2 1 0 DR3 1 1

TABLE 3. INSTRUCTION SET

INSTRUCTION SET

INSTRUCTION

Read Wiper Counter Register

Write Wiper Counter Register

Read Data Register 1 1 0 1 0 1/0 1/0 0 0 Read the contents of the Data Register pointed to

Write Data Register 0 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register

XFR Data Register to Wiper Counter Register

XFR Wiper Counter Register to Data Register

NOTE: 1/0 = data is one or zero.

1 1 0 0 0 0 0 0 0 Read the contents of the Wiper Counter

0 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter

1 1 1 0 0 1/0 1/0 0 0 Transfer the contents of the Data Register

0 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter

1I0

0RBRA 0 0

SELECTION

OPERATIONR/W I

RB-RA.

pointed to RB-RA.

pointed to by RB-RA.to the Wiper Counter Register

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