intersil X9118 DATA SHEET

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X9118

Dual Supply/Low Power/1024-Tap/2-Wire Bus

Data Sheet January 18, 2008

Single Digitally-Controlled (XDCP™) Potentiometer

The X9118 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit.

The digital controlled potentiometer is implemented using 1023 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power-up recalls the contents of the default data register (DR0) to the WCR.

The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

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Features

• 1024 Resistor Taps – 10-Bit Resolution

• 2-Wire Serial Interface for Write, Read and Transfer Operations of the Potentiometer

• Wiper Resistance, 40Ω Typical @ 5V

• Four Non-Volatile Data Registers for Each Potentiometer

• Non-Volatile Storage of Multiple Wiper Positions

• Power On Recall: Loads Saved Wiper Position on Power-Up

• Standby Current < 3µA Max

• System V

• Analog V+/V-:

•100kΩ End to End Resistance

• Endurance: 100,000 Data Changes Per Bit Per Register

• 100 yr. Data Retention

• 14 Ld TSSOP

• Low Power CMOS

2.7V to 5.5V Operation

CC:

-5V to +5V

• Pb-Free Available (RoHS Compliant)

Ordering Information

PART

PART NUMBER

X9118TV14 X9118 TV 5 ±10% 100 0 to +70 14 Ld TSSOP M14.173 X9118TV14Z (Note) X9118 TVZ 0 to +70 14 Ld TSSOP (Pb-free) M14.173 X9118TV14I X9118 TVI -40 to +85 14 Ld TSSOP M14.173 X9118TV14IZ (Note) X9118 TVZI -40 to +85 14 Ld TSSOP (Pb-free) M14.173 X9118TV14-2.7 X9118 TVF 2.7 to 5.5 0 to +70 14 Ld TSSOP M14.173 X9118TV14Z-2.7 (Note) X9118 TVZF 0 to +70 14 Ld TSSOP (Pb-free) M14.173 X9118TV14I-2.7 X9118 TVG -40 to +85 14 Ld TSSOP M14.173 X9118TV14IZ-2.7 (Note) X9118 TVZG -40 to +85 14 Ld TSSOP (Pb-free) M14.173

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-

020.

MARKING

LIMITS

(V)

POTENTIOMETER

ORGANIZATION

(kΩ)

TEMP RANGE

(°C) PACKAGE

PKG.

DWG. #

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Functional Diagram

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X9118

V+

ADDRESS

DATA

2-WIRE

BUS

INTERFACE

STATUS

INTERFACE

Detailed Functional Diagram

SCL

SDA

INTERFACE

AND

CONTROL

CIRCUITRY

BUS

AND

CONTROL

TRANSFER

CONTROL

DATA

CONTROL

WRITE

READ

NC NC

POWER ON

DR0 DR1

DR2 DR3

POWER ON RECALL

WIPER COUNTER REGISTER (WCR)

DATA REGISTERS

(DR0-DR3)

RECALL

WIPER COUNTER REGISTER

(WCR)

WIPER

V+

100kΩ 1024-TAPS

POT

100KΩ 1024-TAPS

V-

Circuit Level Applications

• Vary the gain of a voltage amplifier

• Provide programmable DC reference voltages for comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the DC biasing of a pin diode attenuator in RF circuits

• Provide a control variable (I, V, or R) in feedback circuits

V-

System Level Applications

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in communication systems

• Set and regulate the DC biasing point in an RF power amplifier in wireless systems

• Control the gain in audio and home entertainment systems

• Provide the variable DC bias for tuners in RF wireless systems

• Set the operating points in temperature control systems

• Control the operating point for senso rs in in d ust ri al systems

• Trim offset and gain errors in artificial intelligent systems

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January 18, 2008

X9118

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Pin Configuration

X9118

(14 LD TSSOP)

TOP VIEW

V+

SCL

SDA

1 2 3 4 5 6 7

13 12 11 10

NC A1

9 8

V-

Pin Assignments

(TSSOP) SYMBOL FUNCTION

1 V+ Analog Supply Voltage 2 NC No Connect 3 A0 Device Address for 2-wire bus 4 SCL Serial Clock for 2-wire bus 5WP 6 SDA Serial Data Input/Output for 2-wire bus 7V 8V

9 A1 Device Address for 2-wire bus 10 NC No Connect 11 R 12 R 13 R 14 V

Hardware Write Protect

System Ground

- Analog Supply Voltage

Wiper terminal of the Potentiometer

High terminal of the Potentiometer

Low terminal of the Potentiometer

System Supply Voltage

Pin Descriptions

Bus Interface Pins

SERIAL DATA INPUT/OUTPUT (SDA)

The SDA is a bidirectional serial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from a 2-wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL.

It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph.

SERIAL CLOCK (SCL)

This input is used by 2-wire master to supply 2-wire serial clock to the X9118.

DEVICE ADDRESS (A1–A0)

The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9118. A maximum of 4 XDCP devices may occupy the 2-wire serial bus.

HARDWARE WRITE PROTECT INPUT (WP

The WP

pin when LOW prevents nonvolatile writes to the

)

Data Registers.

Potentiometer Pins

RH, RL

The R

and RL pins are equivalent to the terminal

connections on a mechanical potentiometer.

The wiper pin is equivalent to the wiper terminal of a mechanical potentiometer.

Bias Supply Pins

SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (V

The V

)

pin is the system or digital supply voltage. The VSS

pin is the system ground.

ANALOG SUPPLY VOLTAGES (V+ AND V

These supplies are the analog voltage supplies for the potentiometer. The V+ supply is tied to the wiper switches while the V- supply is used to bias the switches and the internal P+ substrate of the integrated circuit. Both of these supplies set the voltage limits of the potentiometer.

Other Pins

NO CONNECT

No connect pins should be left open. These pins are used for Intersil manufacturing and testing purposes.

Principles of Operation

The X9118 is an integrated microcircuit incorporating a resistor array and its registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometer. This section provides a detailed description of the following:

• Resistor Array Description

• Serial Interface Description

• Instruction and Register Description

Resistor Array Description

The X9118 is comprised of a resistor array. The array contains 1023, in effect, discrete resistive segments that are connected in series (see Figure 1). The physical ends of each array are equivalent to the fixed te rmi nals of a mechanical potentiometer (R

and RL inputs).

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X9118

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SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

If WCR = 000[HEX] then RW = R

If WCR = 3FF[HEX] then RW = R

(DR0)

10 10

(DR2)

FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM

(DR1)

(DR3)

At both ends of each array and between each resistor segment is a CMOS switch (transmission gate) connected to the wiper (R

) output. Within each individual array only one

switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select, and enable, one of 1024 switches.

The WCR may be written directly. The Data Registers and the WCR can be read and written by the host system.

Serial Interface Description

SERIAL BUS INPUT

PARALLEL

BUS INPUT

WIPER

COUNTER

(WCR)

C O U N T E R

D E C O D E

START CONDITION

All commands to the X9118 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9118 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. See Figure 3.

STOP CONDITION

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. See Figure 3.

SERIAL INTERFACE – 2-WIRE

The X9118 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9118 will be considered a slave device in all applications.

CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 3.

ACKNOWLEDGE

Acknowledge is a software convention used to provide a positive handshake between the master an d slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data.

The X9118 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of th e co mma nd byte. If the command is followed by a data byte, the X9118 will respond with a final acknowledge. See Figure 2.

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X9118

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SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ST AR T

FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER

ACKNOWLEDGE POLLING

The disabling of the inputs during the internal nonvolatile write operation can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9118 initiates the internal write cycle. ACK polling, Flow 1, can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9118 is still busy with the write operation no ACK will be returned. If the X9118 has completed the write operation an ACK will be returned and the master can then proceed with the next operation.

Flow 1. ACK Polling Sequence

NONVOLATILE WRITE

COMMAND COMPLETED

ENTERACK POLLING

ISSUE

START

ACKNO WLEDGE

INSTRUCTION AND REGISTER DESCRIPTION DEVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A)

Following a start condition, the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier. The ID[3:0] bits is the device ID for the X9118; this is fixed as 0101[B] (refer to Table 1).

The A[1:0] bits in the ID byte are the internal slave address. The physical device address is defined by the state of the A1-A0 input pins. The slave address is externally specified by the user. The X9118 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9118 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A1-A0 inputs can be actively driven by CMOS input signals or tied to V V

. The R/W bit is the LSB and is used to set the device for

read or write operations.

ISSUE SLAVE

ADDRESS

ACK

RETURNED?

YES

FURTHER

OPERATION?

YES

ISSUE

INSTRUCTION

PROCEED

INSTRUCTION BYTE AND REGISTER SELECTION

ISSUE STOP

The next byte sent to the X9118 contains the instruction and register pointer information. The three most significant bits are used to provide the instruction opcode (I[2:0]). The RB and RA bits point to one of the four registers. The format is shown in Table 2.

Table 3 provides a complete summary of the instruction set opcodes.

ISSUE STOP

PROCEED

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X9118

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TABLE 1. IDENTIFICATION BYTE FORMAT

DEVICE TYPE

IDENTIFIES

ID3 ID2 ID1 ID0 0 A1 A0 R/W

01010A1A0R/W

(MSB) (LSB)

TABLE 2. INSTRUCTION BYTE FORMAT

SET TO 0 FOR PROPER OPERATION

INTERNAL SLAVE

ADDRESS

READ OR WRITE BIT

INSTRUCTION

OPCODE

I2 I1 I0 0 RB RA 0 0

(MSB) (LSB)

DR0 0 0 DR1 0 1 DR2 1 0 DR3 1 1

INSTRUCTION

Read Wiper Counter Register 1 1 0 0 0 0 0 0 0 Read the contents of the Wiper Counter Register Write Wiper Counter Register 0 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register Read Data Register 1 1 0 1 0 1/0 1/0 0 0 Read the contents of the Data Register pointed to

Write Data Register 0 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register pointed to

XFR Data Register to Wiper Counter Register

XFR Wiper Counter Register to Data Register

NOTE:

1. 1/∅ = data is one or zero.

2I1

1 1 1 0 0 1/0 1/0 0 0 Transfer the contents of the Data Register pointed to

0 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counte r Regist e r

SET TO 0 FOR PROPER OPERATION

TABLE 3. INSTRUCTION SET

INSTRUCTION SET

0RBRA 0 0

SELECTION

RB-RA.

by RB-RA to the Wiper Counter Register

to the Data Register pointed to by RB-RA.

SET TO 0 FOR

PROPER OPERATION

OPERATIONR/W

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