intersil X9118 DATA SHEET

®

www.BDTIC.com/Intersil

X9118

Dual Supply/Low Power/1024-Tap/2-Wire Bus

Data Sheet January 18, 2008

Single Digitally-Controlled (XDCP™)
Potentiometer

The X9118 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.

The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and a four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.

The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.

FN8161.3

Features

• 1024 Resistor Taps – 10-Bit Resolution

• 2-Wire Serial Interface for Write, Read and Transfer
Operations of the Potentiometer

• Wiper Resistance, 40Ω Typical @ 5V

• Four Non-Volatile Data Registers for Each Potentiometer

• Non-Volatile Storage of Multiple Wiper Positions

• Power On Recall: Loads Saved Wiper Position on
Power-Up

• Standby Current < 3µA Max

• System V

• Analog V+/V-:

•100kΩ End to End Resistance

• Endurance: 100,000 Data Changes Per Bit Per Register

• 100 yr. Data Retention

• 14 Ld TSSOP

• Low Power CMOS

2.7V to 5.5V Operation

CC:

-5V to +5V

• Pb-Free Available (RoHS Compliant)

Ordering Information

PART

PART NUMBER

X9118TV14 X9118 TV 5 ±10% 100 0 to +70 14 Ld TSSOP M14.173
X9118TV14Z (Note) X9118 TVZ 0 to +70 14 Ld TSSOP (Pb-free) M14.173
X9118TV14I X9118 TVI -40 to +85 14 Ld TSSOP M14.173
X9118TV14IZ (Note) X9118 TVZI -40 to +85 14 Ld TSSOP (Pb-free) M14.173
X9118TV14-2.7 X9118 TVF 2.7 to 5.5 0 to +70 14 Ld TSSOP M14.173
X9118TV14Z-2.7 (Note) X9118 TVZF 0 to +70 14 Ld TSSOP (Pb-free) M14.173
X9118TV14I-2.7 X9118 TVG -40 to +85 14 Ld TSSOP M14.173
X9118TV14IZ-2.7 (Note) X9118 TVZG -40 to +85 14 Ld TSSOP (Pb-free) M14.173

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-

020.

MARKING

V

CC

LIMITS

(V)

POTENTIOMETER

ORGANIZATION

(kΩ)

TEMP RANGE

(°C) PACKAGE

PKG.

DWG. #

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Functional Diagram

www.BDTIC.com/Intersil

X9118

V

CC

R

H

V+

ADDRESS

DATA

2-WIRE

BUS

INTERFACE

STATUS

INTERFACE

Detailed Functional Diagram

V

CC

SCL

SDA

A1

A0

WP

INTERFACE

AND

CONTROL

CIRCUITRY

BUS

AND

CONTROL

V

SS

TRANSFER

CONTROL

DATA

CONTROL

WRITE

READ

NC NC

POWER ON

DR0 DR1

DR2 DR3

POWER ON RECALL

WIPER COUNTER
REGISTER (WCR)

DATA REGISTERS

(DR0-DR3)

RECALL

WIPER
COUNTER
REGISTER

(WCR)

R

WIPER

W

V+

100kΩ
1024-TAPS

POT

R

L

100KΩ
1024-TAPS

V-

R

H

R

L

R

W

V

SS

Circuit Level Applications

• Vary the gain of a voltage amplifier

• Provide programmable DC reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier
circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and Q-factor in
filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the DC biasing of a pin diode attenuator in RF circuits

• Provide a control variable (I, V, or R) in feedback circuits

2

V-

System Level Applications

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems

• Control the gain in audio and home entertainment systems

• Provide the variable DC bias for tuners in RF wireless
systems

• Set the operating points in temperature control systems

• Control the operating point for senso rs in in d ust ri al
systems

• Trim offset and gain errors in artificial intelligent systems

FN8161.3

January 18, 2008

X9118

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Pin Configuration

X9118

(14 LD TSSOP)

TOP VIEW

V+

NC

A0

SCL

WP

SDA

V

SS

1
2
3
4
5
6
7

14

V

CC

R

13
12
11
10

L

R

H

R

W

NC
A1

9
8

V-

Pin Assignments

PIN

(TSSOP) SYMBOL FUNCTION

1 V+ Analog Supply Voltage
2 NC No Connect
3 A0 Device Address for 2-wire bus
4 SCL Serial Clock for 2-wire bus
5WP
6 SDA Serial Data Input/Output for 2-wire bus
7V
8V

9 A1 Device Address for 2-wire bus
10 NC No Connect
11 R
12 R
13 R
14 V

Hardware Write Protect

System Ground

SS

- Analog Supply Voltage

Wiper terminal of the Potentiometer

W

High terminal of the Potentiometer

H

Low terminal of the Potentiometer

L

System Supply Voltage

CC

Pin Descriptions

Bus Interface Pins

SERIAL DATA INPUT/OUTPUT (SDA)

The SDA is a bidirectional serial data input/output pin for a
2-wire slave device and is used to transfer data into and out
of the device. It receives device address, opcode, wiper
register address and data sent from a 2-wire master at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock SCL.

It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs. An open
drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.

SERIAL CLOCK (SCL)

This input is used by 2-wire master to supply 2-wire serial
clock to the X9118.

DEVICE ADDRESS (A1–A0)

The address inputs are used to set the least significant 2 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the Address input in
order to initiate communication with the X9118. A maximum
of 4 XDCP devices may occupy the 2-wire serial bus.

HARDWARE WRITE PROTECT INPUT (WP

The WP

pin when LOW prevents nonvolatile writes to the

)

Data Registers.

Potentiometer Pins

RH, RL

The R

and RL pins are equivalent to the terminal

H

connections on a mechanical potentiometer.

R

W

The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.

Bias Supply Pins

SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (V

The V

CC

)

SS

pin is the system or digital supply voltage. The VSS

pin is the system ground.

ANALOG SUPPLY VOLTAGES (V+ AND V

-)

These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper switches
while the V- supply is used to bias the switches and the
internal P+ substrate of the integrated circuit. Both of these
supplies set the voltage limits of the potentiometer.

Other Pins

NO CONNECT

No connect pins should be left open. These pins are used for
Intersil manufacturing and testing purposes.

Principles of Operation

The X9118 is an integrated microcircuit incorporating a
resistor array and its registers and counters and the serial
interface logic providing direct communication between the
host and the digitally controlled potentiometer. This section
provides a detailed description of the following:

• Resistor Array Description

• Serial Interface Description

• Instruction and Register Description

Resistor Array Description

The X9118 is comprised of a resistor array. The array
contains 1023, in effect, discrete resistive segments that are
connected in series (see Figure 1). The physical ends of
each array are equivalent to the fixed te rmi nals of a
mechanical potentiometer (R

and RL inputs).

H

3

FN8161.3

January 18, 2008

X9118

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SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

If WCR = 000[HEX] then RW = R

If WCR = 3FF[HEX] then RW = R

REGISTER 0

(DR0)

10 10

REGISTER 2

(DR2)

L

H

FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM

REGISTER 1

(DR1)

REGISTER 3

(DR3)

At both ends of each array and between each resistor
segment is a CMOS switch (transmission gate) connected to
the wiper (R

) output. Within each individual array only one

W

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
10-bits of the WCR (WCR[9:0]) are decoded to select, and
enable, one of 1024 switches.

The WCR may be written directly. The Data Registers and
the WCR can be read and written by the host system.

Serial Interface Description

SERIAL
BUS
INPUT

PARALLEL

BUS
INPUT

WIPER

COUNTER

REGISTER

(WCR)

C
O
U
N
T
E
R

D
E
C
O
D
E

R

H

R

L

R

W

START CONDITION

All commands to the X9118 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X9118 continuously monitors the SDA
and SCL lines for the start condition and will not respond to
any command until this condition is met. See Figure 3.

STOP CONDITION

All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH. See Figure 3.

SERIAL INTERFACE – 2-WIRE

The X9118 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9118 will be
considered a slave device in all applications.

CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 3.

4

ACKNOWLEDGE

Acknowledge is a software convention used to provide a
positive handshake between the master an d slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.

The X9118 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of th e co mma nd byte. If
the command is followed by a data byte, the X9118 will
respond with a final acknowledge. See Figure 2.

FN8161.3

January 18, 2008

X9118

www.BDTIC.com/Intersil

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ST AR T

FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER

1

ACKNOWLEDGE POLLING

The disabling of the inputs during the internal nonvolatile write
operation can be used to take advantage of the typical 5ms
EEPROM write cycle time. Once the stop condition is issued to
indicate the end of the nonvolatile write command the X9118
initiates the internal write cycle. ACK polling, Flow 1, can be
initiated immediately. This involves issuing the start condition
followed by the device slave address. If the X9118 is still busy
with the write operation no ACK will be returned. If the X9118
has completed the write operation an ACK will be returned and
the master can then proceed with the next operation.

Flow 1. ACK Polling Sequence

NONVOLATILE WRITE

COMMAND COMPLETED

ENTERACK POLLING

ISSUE

START

89

ACKNO WLEDGE

INSTRUCTION AND REGISTER DESCRIPTION
DEVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A)

Following a start condition, the master must output the
address of the slave it is accessing. The most significant four
bits of the slave address are the device type identifier. The
ID[3:0] bits is the device ID for the X9118; this is fixed as
0101[B] (refer to Table 1).

The A[1:0] bits in the ID byte are the internal slave address.
The physical device address is defined by the state of the
A1-A0 input pins. The slave address is externally specified
by the user. The X9118 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9118 to successfully
continue the command sequence. Only the device which
slave address matches the incoming device address sent by
the master executes the instruction. The A1-A0 inputs can
be actively driven by CMOS input signals or tied to V
V

. The R/W bit is the LSB and is used to set the device for

SS

CC

or

read or write operations.

ISSUE SLAVE

ADDRESS

ACK

RETURNED?

YES

FURTHER

OPERATION?

YES

ISSUE

INSTRUCTION

PROCEED

NO

NO

INSTRUCTION BYTE AND REGISTER SELECTION

ISSUE STOP

The next byte sent to the X9118 contains the instruction and
register pointer information. The three most significant bits
are used to provide the instruction opcode (I[2:0]). The RB
and RA bits point to one of the four registers. The format is
shown in Table 2.

Table 3 provides a complete summary of the instruction set
opcodes.

ISSUE STOP

PROCEED

5

FN8161.3

January 18, 2008

X9118

www.BDTIC.com/Intersil

TABLE 1. IDENTIFICATION BYTE FORMAT

DEVICE TYPE

IDENTIFIES

ID3 ID2 ID1 ID0 0 A1 A0 R/W

01010A1A0R/W

(MSB) (LSB)

TABLE 2. INSTRUCTION BYTE FORMAT

SET TO 0
FOR PROPER
OPERATION

INTERNAL SLAVE

ADDRESS

READ OR
WRITE BIT

INSTRUCTION

OPCODE

I2 I1 I0 0 RB RA 0 0

(MSB) (LSB)

REGISTER SELECTED RB RA

DR0 0 0
DR1 0 1
DR2 1 0
DR3 1 1

INSTRUCTION

Read Wiper Counter Register 1 1 0 0 0 0 0 0 0 Read the contents of the Wiper Counter Register
Write Wiper Counter Register 0 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register
Read Data Register 1 1 0 1 0 1/0 1/0 0 0 Read the contents of the Data Register pointed to

Write Data Register 0 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register pointed to

XFR Data Register to Wiper
Counter Register

XFR Wiper Counter Register
to Data Register

NOTE:

1. 1/∅ = data is one or zero.

I

2I1

1 1 1 0 0 1/0 1/0 0 0 Transfer the contents of the Data Register pointed to

0 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counte r Regist e r

SET TO 0
FOR PROPER
OPERATION

TABLE 3. INSTRUCTION SET

INSTRUCTION SET

I

0RBRA 0 0

0

REGISTER

SELECTION

RB-RA.

RB-RA.

by RB-RA to the Wiper Counter Register

to the Data Register pointed to by RB-RA.

SET TO 0 FOR

PROPER OPERATION

OPERATIONR/W

6

FN8161.3

January 18, 2008

X9118

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Instruction and Register Description

DEVICE ADDRESSING
Wiper Counter Register (WCR)

The X9118 contains a Wiper Counter Register (see Table 4)
for the XDCP potentiometer. The WCR is equivalent to a
serial-in, parallel-out register/counter with its outputs
decoded to select one of 1024 switches along its resistor
array. The contents of the WCR can be altered in one of
three ways:

1. It may be written directly by the host via the write Wiper
Counter Register instruction (serial load)

2. It may be written indirectly by transferring the contents of
one of four associated Data Registers via the XFR Data
register

3. It is loaded with the contents of its Data Register zero
(R0) upon power-up.

The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9118 is powered-down.
Although the register is automatically loaded with the value
in DR0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loadings of the DR0 value
into the WCR.

Data Registers (DR)

The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four data
registers and the Wiper Counter Register. All operations
changing data in one of the Data Registers is a nonvolatile
operation and will take a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.

Bit 9–Bit 0 are used to store one of the 1024 wiper position
(0 ~1023).

Four of the six instructions are four bytes in length. These
instructions are:

• Read Wiper Counter Register – read the current wiper
position of the potentiometer,

• Write Wiper Counter Register – change current wiper
position of the potentiometer,

• Read Data Register – read the contents of the selected
Data Register;

• Write Dat a Register – write a new value to the selected
Data Register.

The basic sequence of the four byte instructions is illustrated
in Figure 3. These four-byte instructions exchange data
between the WCR and one of the Data Registers. A transfer
from a data register to a WCR is essentially a write to a static
RAM, with the static RAM controlling the wiper position. The
response of the wiper to this action will be delayed by t
transfer from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a min imum
of t

to complete. The transfer can occur between the

WR

potentiometer and one of its associated registers.
Two instructions (see Figure 4) require a two-byte sequence

to complete. These instructions transfer data between the
host and the X9118; either between the host and one of the
Data Registers or directly between the host and the Wiper
Counter Register. These instructions are:

• XFR Data Register to Wiper Counter Register – This
transfers the contents of one specified Data Register to
the Wiper Counter Register.

• XFR Wiper Counter Register to Data Register –This
transfers the contents of the specified Wiper Counter
Register to the specified Data Register.

See “Instruction Format” on page 8 for more details.

WRL

. A

Other

POWER-UP AND DOWN REQUIREMENTS

At all times, the V+ voltage must be greater than or equal to
the voltage at R
greater than or equal to the voltage at V-. During power-up
and power down, V
values within 1ms of e ac h ot he r.

or RL, and the voltage at RH or RL must be

H

, V+, and V- must reach their final

CC

TABLE 4. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V)

WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0

VVVVVVVVVV

(MSB) (LSB)

TABLE 5. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE, NV)

BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

NV NV NV NV NV NV NV NV NV NV

MSB LSB

7

FN8161.3

January 18, 2008

SCL

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X9118

SDA

01 0 1

S

ID3 ID2 ID1 ID0
T
A

DEVICE ID

R
T

FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE

SCL

SDA

0101 0

ID3 ID2 ID1 ID0 0 A1A0R/W

S
T
A
R

T

DEVICE ID

INTERNAL
ADDRESS

0

A
C
K

INSTRUCTION

I1

I2

OPCODE

FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)

Instruction Format

Read Wiper Counter Register (WCR)

Device Type

S

Identifier

T
A

R

01010A 1A 0

T

Device

Addresses

Instruction

Opcode

S
A
C

10000000 XXXXXX

K

R/W = 1

0A1A0R/W

INTERNAL

ADDRESS

0XX0

RB RA

0

I0

0

REGISTER
ADDRESS

Register

Addresses

I2

A
C
K

0

I1

INSTRUCTION

OPCODE

XX

A
C
K

XX X

Wiper Position

(Sent by Slave on SDA)

S
A
C
K

0

I0

0RBRA0

REGISTER
ADDRESS

X

W
C

R
9

W
C

R
8

W

C
R

9

00

A

W

W

C

C

C

R

R

K

7

6

WIPER OR DATA

POSITION

M
A

W

W

C

C

C

K

R

R

7

8

A

S
T

C

O

K

P

W

W

W

C
R
5

W

C

C

C

R

R

R

4

3

2

A

W

W

C

C

C
K

R

R

1

0

Wiper Position

(Sent by Slave on SDA)

W

W

W

W

W

C

C

C

R

R

R

6

5

4

W

C

C

C

R

R

R

3

2

1

S
T
O
P

M

S

A

T

W

C

O

C

K

P

R

0

Write Wiper Counter Register (WCR)

Device Type

S

Identifier
T
A
R

01010A 1A 0

T

Device

Addresses

Instruction

Opcode

S

A
C
K

10100000 XXXXXX

R/W = 0

Read Data Register (DR)

Device Type

S

Identifier
T
A

R

01010A 1A 0

T

Device

Addresses

Instruction

Opcode

S
A
C
K

1010RBRA00 XXXXXX

R/W = 1

Write Data Register (DR)

Device

Type

S

Identifier

T
A

R

01010A 1A 0

T

Device

Addresses

Instruction

Opcode

S
A
C
K

1100RBRA0 0 XXXXXX

R/W = 0

Register

Addresses

Register

Addresses

Register

Addresses

Wiper Position

(Sent by Master on SDA)

S

A
C
K

Wiper Position

(Sent by Slave on SDA)

S
A
C
K

Wiper Position or Data

(Sent by Master on SDA)

S
A
C
K

Wiper Position

(Sent by Master on SDA)

S
A

W

W

W

W

W

W

W

C

C

C

C

C

K

R

R

9

8

M
A

W

W

C

C

C

K

R

R

9

8

Wiper Position or Data

(Sent by Master on SDA)

S
A

W

W

W

W

C

C

C

C

C

K

R

R

R

9

8

R

7

6

C

R

R

R

7

6

5

Wiper Position or Data

(Sent by Slave on SDA)

W

W

W

C

C

C

R

R

R

7

6

5

W

W

W

C

C

C

R

R

R

5

4

3

W

C

C

C

R

R

R

4

3

2

W

W

W

C

C

C

R

R

R

4

3

2

W

W

W

C

C

C

R

R

R

2

1

0

S

S

A

W

C
R
1

W

C
R

1

S
A
C
K

T

W

C

O

C

K

P

R

0

M

S

A

T

W

C

O

C

K

P

R

0

S
T
O
P

WRITE CYCLE

HIGH-VOLTAGE

8

FN8161.3

January 18, 2008

X9118

www.BDTIC.com/Intersil

Transfer Wiper Counter Register (WCR) to Data Register (DR)

Device Type

S

Identifier

T
A

R

01010A 1A 0

T

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Device Type

S

Identifier

T
A

R

T

NOTES:

1. “A1 ~ A0”: stands for the device addresses sent by the master.

2. WCRx refers to wiper position data in the Wiper Counter Register.

Device

Addresses

Device

Addresses

Instruction

Opcode

S
A
C

1110RBRA00

K

R/W = 0

Instruction

Opcode

S
A
C

1100RBRA00

K

R/W = 1

Register

Addresses

Register

Addresses

S

S

A

T

C

O

K

P

S

S

A

T

C

O

K

P01010A 1A 0

HIGH-VOLTAGE

WRITE CYCLE

9

FN8161.3

January 18, 2008

X9118

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Voltage on SCL, SDA, or Any Address Input

with Respect to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

Voltage on V+ (referenced to V
Voltage on V- (referenced to V

(V+) – (V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V

Any Voltage on R
Any Voltage on R
Supply Voltage (VCC) Limits (Note 7)

X9118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%

X9118-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTE:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3. θ

JA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+

H/RL

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-

L/RH

) (Note 7) . . . . . . . . . . . . . . . .10V

SS

) (Note 7) . . . . . . . . . . . . . . . . -10V

SS

Thermal Resistance (Typical, Note 3) θ

14 Ld TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Analog Specifications (Over the recommended operating conditions unless otherwise specified.)

LIMITS

SYMBOL PARAMETER TEST CONDITIONS

R

TOTAL

I

W

R
R

Vv+ Voltage on V+ Pin X9118 (Note 7) +4.5 +5.5 V

Vv- Voltage on V- Pin X9118 -5.5 -4.5 V

V

TERM

C

H/CL/CW

NOTES:

4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.

5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.

6. MI = R

7. V

CC

8. n = 0, 1, 2, …,1023; m = 0, 1, 2, …, 1022.

End to End Resistance 100 kΩ
End to End Resistance Tolerance ±20 %
Power Rating +25°C, each pot 50 mW
Wiper Current ±3 mA
Wiper Resistance Wiper Current = ± 3mA, VCC = 3V 150 500 W

W

Wiper Resistance IW = ± 3mA, VCC = 5V 40 100 W

W

X9118-2.7 (Note 7) +2.7 +5.5

X9118-2.7 -5.5 -2.7
Voltage on any RH or RL Pin V
Noise Ref: 1V -120 dBV
Resolution 0.1 %
Absolute Linearity (Note 4) R

Relative Linearity (Note 5) R

Temperature Coefficient of R
Ratiometric Temp. Coefficient 20 ppm/°C
Potentiometer Capacitances See Macro model 10/10/25 pF

/1023 or (RH – RL)/1023, single pot

TOT

, V+, V- must reach their final values within 1ms of each other.

TOTAL

= 0V V- V+ V

SS

w(n)(actual)

n = 8 to 1006

R

w(n)(actual)

– [R

w(m + 1)

1006

R

w(m + 1)

– [R

– R

w(n)(expected)

– R

w(n)(expected)

+ MI], where m = 8 to

w(m)

+ MI] (Note 8) ±1 MI

w(m)

, where

(Note 8) ±1.5 MI

MIN TYP MAX UNITS

±1 MI

±0.5 MI

±300 ppm/°C

(°C/W)

JA

(Note 6)

(Note 6)

(Note 6)

(Note 6)

10

FN8161.3

January 18, 2008

X9118

www.BDTIC.com/Intersil

DC Operating Specifications (Over the recommended operating conditions unless otherwise specified.)

LIMITS

SYMBOL PARAMETER TEST CONDITIONS

V

I

CC1

I

CC2

I

SB

I

I

LO

V

V
V
V

OH

Supply Current

CC

(active)

V

Supply Current

CC

(nonvolatile write)

VCC Current
(standby)

Input Leakage Current VIN = VSS to V

LI

Output Leakage Current V
Input HIGH Voltage VCC x 0.7 VCC + 1 V

IH

Input LOW Voltage -1 VCC x 0.3 V

IL

Output LOW Voltage IOL = 3mA 0.4 V

OL

Output HIGH Voltage

f

= 400kHz; VCC = +5.5V;

SCL

SDA = Open; (for 2-wire, Active, Read and
Volatile Write States only)

f

= 400kHz; VCC = +5.5V;

SCL

SDA = Open; (for 2-wire, Active,
Non-volatile Write State only)

V

= +5.5V; VIN = VSS or VCC; SDA = VCC;

CC

(for 2-wire, Standby State only)

CC

= VSS to V

OUT

CC

Endurance and Data Retention

PARAMETER MIN UNITS

Minimum Endurance 100,000 Data changes per bit per register

Data Retention 100 years

MIN TYP MAX UNITS

3mA

5mA

3 μA

10 μA
10 μA

Capacitance

SYMBOL TEST MAX UNITS TEST CONDITIONS

C

(Note 9) Input/Output Capacitance (SI) 8 pF V

IN/OUT

(Note 9) Input Capacitance (SCL, WP, A2, A1 and A0) 6 pF VIN = 0V

C

IN

OUT

Power-Up Timing

SYMBOL PARAMETER MIN MAX UNITS

(Note 9) VCC Power-up Rate 0.2 50 V/ms

t

r VCC

(Note 10) Power-up to Initiation of Read Operation 1 ms

t

PUR

(Note 10) Power-up to Initiation of Write Operation 50 ms

t

PUW

NOTES:

9. This parameter is not 100% tested

10. t

and t

PUR

parameters are periodically sampled and not 100% tested.

are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These

PUW

AC Test Conditions

Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times 10ns
Input and Output Timing Level V

CC

x 0.5

= 0V

11

FN8161.3

January 18, 2008

Equivalent A.C. Load Circuit

www.BDTIC.com/Intersil

X9118

SDA OUTPUT

5V

1533Ω

SDA OUTPUT

100pF

3V

867Ω

100pF

SPICE MACROMODEL

R

H

C

L

10pF

R

TOTAL

R

W

C

W

25pF

C

L

10pF

AC Timing High-Voltage Write Cycle Timing

SYMBOL PARAMETER MIN MAX UNITS

f

SCL

t

CYC

t

HIGH

t

LOW

t

SU:STA

t

HD:STA

t

SU:STO

t

SU:DAT

t

HD:DAT

t

R

t

F

t

AA

t

DH

T

I

t

BUF

t

SU:WPA

t

HD:WPA

Clock Frequency 400 kHz
Clock Cycle Time 2500 ns
Clock High Time 600 ns
Clock Low Time 1300 ns
Start Setup Time 600 ns
Start Hold Time 600 ns
Stop Setup Time 600 ns
SDA Data Input Setup Time 100 ns
SDA Data Input Hold Time 0 ns
SCL and SDA Rise Time 300 ns
SCL and SDA Fall Time 300 ns
SCL Low to SDA Data Output Valid Time 250 ns
SDA Data Output Hold Time 0 ns
Noise Suppression Time Constant at SCL and SDA inputs 50 ns
Bus Free Time (Prior to Any Transmission) 1300 ns
A0, A1 Setup Time 0 ns
A0, A1 Hold Time 0ns

R

L

High-Voltage Write Cycle Timing

SYMBOL PARAMETER TYP MAX UNITS

t

WR

High-Voltage Write Cycle Time (store instructions) 5 10 ms

XDCP Timing

SYMBOL PARAMETER MIN MAX UNITS

t

WRPO

t

WRL

Wiper Response Time After the Third (last) Power Supply is Stable 5 10 µs
Wiper Response Time After Instruction Issued (all load instructions) 5 10 µs

12

FN8161.3

January 18, 2008

Symbol Table

www.BDTIC.com/Intersil

WAVEFORM INPUTS OUTPUTS

X9118

Timing Diagrams

Start and Stop Timing

SCL

t

SU:STA

SDA

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

(START) (STOP)

t

F

t

SU:STO

t

F

t

HD:STA

t

R

t

R

Input Timing

SCL

SDA

Output Timing

SCL

SDA

t

CYC

t

SU:DAT

t

HIGH

t

LOW

t

HD:DAT

t

AA

t

DH

t

BUF

13

FN8161.3

January 18, 2008

XDCP Timing (For All Load Instructions)

www.BDTIC.com/Intersil

SCL

X9118

(STOP)

SDA

R

W

Write Protect and Device Address Pins Timing

(START) (STOP)

SCL

SDA

t

SU:WPA

WP

A0, A1

Applications information

Basic Configurations of Electronic Potentiometers

LSB

t

...

(Any Instruction)

...

...

WRL

t

HD:WPA

V

R

Three terminal Potentiometer;
Variable voltage divider

RW

+V

R

I

Two terminal Variable Resistor;
Variable current

14

FN8161.3

January 18, 2008

Application Circuits

www.BDTIC.com/Intersil

NONINVERTING AMPLIFIER VOLTAGE REGULATOR

X9118

V

S

VO = (1+R2/R1)V

OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERISIS

V

S

10kΩ

R

R

1

100kΩ

-12V+12V

+

–

R

1

S

–

+

TL072

10κΩ10kΩ

V

O

2

R

2

V

O

IN

VO (REG) = 1.25V (1+R2/R1)+I

V

S

VUL = {R1/(R1+R2)} VO(max)

= {R1/(R1+R2)} VO(min)

RL

L

317

R

I

adj

R

2

–

+

}

}

R

R

2

1

1

adj R2

VO (REG)V

V

O

15

FN8161.3

January 18, 2008

Application Circuits (Continued)

www.BDTIC.com/Intersil

ATTENUATOR FILTER

R

1

V

S

V

S

R

3

R

4

VO = G V

-1/2 ≤ G ≤ +1/2

INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT

R

R

2

1

}

}

R

2

–

+

R1 = R2 = R3 = R4 = 10kΩ

S

–

+

X9118

C

V

S

V

O

V

V

O

S

R

C

1

G

= 1 + R2/R

O

fc = 1/(2πRC)

+

–

R

R

1

1

R

2

+

–

V

O

2

VO = G V
G = - R2/R

FUNCTION GENERATOR

frequency ∝ R1, R2, C
amplitude ∝ R

S

1

–

+

, R

A

B

R

Z

IN

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R

R

2

R

}

A

R

}

B

R

1

–

+

1

R

3

+ R3) >> R

1

C

2

16

FN8161.3

January 18, 2008

X9118

www.BDTIC.com/Intersil

Thin Shrink Small Outline Plastic Packages (TSSOP)

N

INDEX
AREA

123

0.05(0.002)

-A­D

e

b

0.10(0.004) C AM BS

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen­sion at maximum material condition. Minimum space between protru­sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)

E1

-B-

SEATING PLANE

A

-C-

M

0.25(0.010) BM M

E

α

A1

0.10(0.004)

GAUGE

PLANE

0.25

0.010

A2

L

c

M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.041 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.195 0.199 4.95 5.05 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N14 147

o

α

0

o

8

o

0

o

8

NOTESMIN MAX MIN MAX

-

Rev. 2 4/06

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

17

FN8161.3

January 18, 2008