intersil X9116 DATA SHEET

®

www.BDTIC.com/Intersil

X9116

Low Noise, Low Power, Low Cost

Data Sheet September 26, 2006

Digitally Controlled Potentiometer
(XDCP™)

The Intersil X9116 is a digitally controlled nonvolatile
potentiometer designed to be used in trimmer applications.
The pot consists of 15 equal resistor segments that connect
to the wiper pin through programmable CMOS switches. The
tap position is programmed through a 3-wire up/down serial
port. The last position of the wiper is stored in a nonvolatile
memory location which is recalled at the time of pow er up of
the device.

The wiper moves through sequential tap positions with
inputs on the serial port. A falling edge on INC (bar) causes
the tap position to increment one position up or down based
on whether the U/D (bar) pin is held high or low.

The X9116 can be used in many applications requiring a
variable resistance. In many cases it can replace a
mechanical trimmer and offers many advantages such as
temperature and time stability as well as the reliability of a
solid state solution.

FN8160.2

Features

• Solid-state nonvolatile

• 16 wiper taps

• 3-wire up/down serial interface
= 2.7V and 5V

•V

CC

• Active current < 50µA max.

• Standby current < 1µA max.

TOTAL

= 10kΩ

•R

• Packages: 8LdMSOP, 8LdSOIC

• Pb-free plus anneal available (RoHS compliant)

Pinout

SOIC/MSOP

INC

U/D

VH/R

V

SS

1

2

X9116

3

H

4

V

8

CC

CS

7

VL/R

VW/R

L

W

6

5

Block Diagram

V

CC

Up/Down

(U/D

)

Increment

(INC

)

Device Select

(CS)

(Supply Voltage)

Control

and

Memory

V

(Ground)

SS

General

R

H/VH

RW/V

RL/V

R

W

L

RW-RL Resistance

R

H

*

3

2

1

0

L

15

14

13

10kΩ

9.34kΩ

8.68kΩ
* kΩ

2.08kΩ

1.42kΩ

760Ω
100Ω

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Ordering Information

www.BDTIC.com/Intersil

X9116

PART NUMBER

(BRAND) PART MARKING

X9116WM8T1 AAZ 5V ±10% 10 0 to +70 8 Ld MSOP Tape and Reel M8.118
X9116WM8ZT1 (Note) AKY 0 to +70 8 Ld MSOP (Pb-free)

X9116WM8I* AFL -40 to +85 8 Ld MSOP M8.118
X9116WM8IZ* (Note) DCG -40 to +85 8 Ld MSOP (Pb-free) M8.118
X9116WS8* X9116W 0 to +70 8 Ld SOIC M8.15
X9116WS8Z* (Note) X9116W Z 0 to +70 8 Ld SOIC (Pb-free) M8.15
X9116WS8I* X9116W I -40 to +85 8 Ld SOIC M8.15
X9116WS8IZ* (Note) X9116W ZI -40 to +85 8 Ld SOIC (Pb-free) M8.15
X9116WM8-2.7** AFK -2.7-5.5 0 to +70 8 Ld MSOP M8.118
X9116WM8Z-2.7* (Note) AOJ 0 to +70 8 Ld MSOP (Pb-free) M8.118
X9116WM8I-2.7* ABA -40 to +85 8 Ld MSOP M8.118
X9116WM8IZ-2.7* (Note) AKS -40 to +85 8 Ld MSOP (Pb-free) M8.118
X9116WS8-2.7* X9116W F 0 to +70 8 Ld SOIC M8.15
X9116WS8Z-2.7* (Note) X9116W ZF 0 to +70 8 Ld SOIC (Pb-free) M8.15
X9116WS8I-2.7* X9116W G -40 to +85 8 Ld SOIC M8.15
X9116WS8IZ-2.7* (Note) X9116W ZG -40 to +85 8 Ld SOIC (Pb-free) M8.15

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.

*Add "T1" suffix for tape and reel.
**Add “T2” suffix for tape and reel.

VCC LIMITS

(V)

R

TOTAL

(kΩ)

TEMP. RANGE

(°C) PACKAGE

M8.118

Tape and Reel

PKG.

DWG. #

Pin Descriptions

VH /RH and VL /RL

The high (VH/RH) and low (VL/RL) terminals of the X9116
are equivalent to the fixed terminals of a mechanical
potentiometer. The minimum voltage is V
maximum is V

VW/R

W

CC

.

Rw/Rw is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs.
The wiper terminal series resistance is typically 200Ω to
400Ω depending upon V

CC

.

Up/Down (U/D)

The U/D input controls the direction of the wiper movement
and whether the counter is incremented (up) or decremented
(down).

Increment (INC)

The INC input is negative-edge triggered. Toggl ing INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the
U/D

input.

and the

SS

Chip Select (CS)

The device is selected when the CS input is LOW. The
current counter value is stored in nonvolatile memory when
CS

is returned HIGH while the INC input is also HIGH. After
the store operation is complete the X9116 will be placed in
the low power standby mode until the device is selected
once again.

Pin Descriptions

SYMBOL DESCRIPTION

VH/R

VW/R

VL/R

V

SS

V

CC

U/D
INC

CS

H
W
L

High Terminal
Wiper Terminal
Low Terminal
Ground
Supply Voltage
Up/Down Control Input
Increment Control Input
Chip Select Input

2

FN8160.2

September 26, 2006

X9116

www.BDTIC.com/Intersil

Principles of Operation

There are three sections of the X9116: the input control,
counter and decode section; the nonvolatile memory; and
the resistor array. The input control section operates just like
an up/down counter. The output of this counter is decoded to
turn on a single electronic switch connecting a point on the
resistor array to the wiper output. Under the proper
conditions the contents of the counter can be stored in
nonvolatile memory and retained for future use. The resistor
array is comprised of 15 individual resistors connected in
series. At either end of the array and between each resistor
is an electronic switch that transfers the potential at that
point to the wiper pin.

The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.

The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
connected to the wiper for t
R
a significant amount if the wiper is moved several positions.

When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is set to the value last stored.

value for the device can temporarily be reduced by

TOTAL

(INC to VW change). The

IW

Instructions and Programming

The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS
is selected and enabled to respond to the U/D
inputs. HIGH to LOW transitions on INC
decrement (depending on the state of the U/D
bit counter. The output of this counter is decoded to select
one of 16 wiper positions along the resistive array.

set LOW, the device

and INC

will increment or

input) a four

This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation, minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, etc.

The state of U/D
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.

may be changed while CS remains LOW.

Mode Selection

CS INC U/D MODE

L H Wiper Up
L L Wiper Down

H X Store Wiper Position

H X X Standby Current

L X No Store, Return to Standby

Symbol Table

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

The value of the counter is stored in nonvolatile memory
whenever CS
HIGH.

The system may select the X9116, move the wiper, and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as described above and once the new position is
reached, the system must keep INC
HIGH. The new wiper position will be maintained until
changed by the system or until a power-up/down cycle
recalls the previously stored data.

transitions HIGH while the INC input is also

LOW while taking CS

3

FN8160.2

September 26, 2006

X9116

www.BDTIC.com/Intersil

Absolute Maximum Ratings Recommended Operating Conditions

Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on CS

and V
ΔV = |V

Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . .+300°C

(10 seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±10.0mA

I

W

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

, INC, U/D, VH/RH, VL/RL

with respect to VSS. . . . . . . . . . . . . . . . . . . . . -1V to +7V

CC

H/RH-VL/RL

|. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V

Potentiometer Specifications Over recommended operating conditions unless o therwise stated

SYMBOL PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT

R

TOTAL

V

VH

V

VL

R

W

R

W

I

W

C

H/CL/CW

NOTES:

1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (V

2. Relative linearity is a measure of the error in step size between taps = V

3. 1 Ml = Minimum Increment = R

End to end resistance variation -20 +20 %
VH/RH terminal voltage VSS = 0V V
VL/RL terminal voltage VSS = 0V V
Power rating R
Wiper resistance IW = 1mA, VCC = 5V 200 400 Ω
Wiper resistance IW = 1mA, VCC = 2.7V 400 1000 Ω
Wiper current -5.0 +5.0 mA
Noise Ref: 1kHz -120 dBV√Hz
Resolution 6%
Absolute linearity (Note 1) V
Relative linearity (Note 2) V

temperature coefficient ±300 ppm/°C

R

TOTAL

Ratiometric temperature coefficient ±20 ppm/°C
Potentiometer capacitances See Circuit #3 10/10/25 pF

/15.

TOT

TOTAL

w(n)(actual)
w(n+1)

Temperature Range

Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage (V

X9116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%

X9116-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

= 10kΩ 10 mW

- V

w(n)(expected)

- [V

]-0.2 +0.2MI

w(n) + MI

-[V

W(n+1 )

+ Ml] = ±0.2 Ml.

w(n)

) Limits

CC

SS
SS

-1 +1 MI (Note 3)

(actual) - V

w(n)

(expected)) = ±1 Ml Maximum.

w(n)

V

CC

V

CC

V
V

(Note 3)

4

FN8160.2

September 26, 2006

X9116

www.BDTIC.com/Intersil

DC Electrical Specifications Over recommended operating conditions unless otherwise specified

SYMBOL PARAMETER TEST CONDITIONS MIN TYP (Note 4) MAX UNIT

I

CC1

I

CC2

I

SB

I

LI

V

IH

V

(Note 5) CS, INC, U/D input capacitance VCC = 5V, VIN = VSS, TA= 25°C,

C

IN

4. Typical values are for T

VCC active current (Increment) CS = VIL, U/D = VIL or VIH and

INC

= 0.4V/2.4V @ max t

VCC active current (Store) (EEPROM Store) CS = VIH, U/D = VIL or VIH and

=V

INC

@ max t

IH

WR

Standby supply current CS = VCC–0.3V, U/D and INC =VSS or

–0.3V

V

CC

CS, INC, U/D input leakage current VIN = V

SS

to V

CC

CS, INC, U/D input HIGH voltage 2V VCC + 0.5 V
CS, INC, U/D input LOW voltage -0.5 0.8 V

IL

f=1MHz

= +25°C and nominal supply voltage.

A

5. This parameter is periodically sampled and not 100% tested.

Endurance And Data Retention

PARAMETER MIN UNIT

Minimum endurance 100,000 Data changes per bit

Data retention 100 Years

CYC

150 µA

400 µA

1µA

±10 µA

10 pF

Test Circuit #1 Test Circuit #2 Circuit #3 SPICE Macro Model

VH/R

H

V

S

VL/R

L

Test Point

VW/R

W

VH/R

V

VL/R

L

H

VW/R

VW

L

Test Point

W

Force
Current

R

R

H

10pF

TOTAL

C

C

H

W

25pF

R

W

C

10pF

A.C. Conditions of Test

Input pulse levels 0V to 3V
Input rise and fall times 10ns
Input reference levels 1.5V

R

L

L

5

FN8160.2

September 26, 2006

X9116

www.BDTIC.com/Intersil

DC Electrical Specifications Over recommended operating conditions unless otherwise specified

SYMBOL PARAMETER MIN TYP (NOTE 6) MAX UNIT

t

Cl

t

lD

t

DI

t

lL

t

lH

t

lC

t

CPH

t

IW

t

CYC

(Note 7) INC input rise and fall time 500 µs

t

R, tF

t

(Note 7) Power up to wiper stable 5 µs

PU

(Note 7) VCC Power-up rate 15 50 mV/µs

t

R VCC

t

WR

Power Up and Down Requirements

There are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins
provided that V
always in effect.

CC

CS to INC setup 100 ns
INC HIGH to U/D change 100 ns
U/D to INC setup 2.9 µs
INC LOW period 1 µs
INC HIGH period 1 µs
INC inactive to CS inactive 1 µs
CS deselect time (STORE) 10 ms
INC to Vw change 1 5 µs
INC cycle time 4 µs

Store cycle 5 10 ms

is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC ramp rate spec is

A.C. Timing

CS

t

CYC

INC

U/D

V

t

CI

t

IW

W

t

IL

t

ID

t

IH

t

DI

NOTES:

6. Typical values are for T

= +25°C and nominal supply voltage.

A

7. This parameter is not 100% tested.

8. MI in the A.C. timing diagram refers to the minimum incremental change in the V

(store)

t

IC

(NOTE 8)

MI

t

CPH

90% 90%

10%

t

F

output due to a change in the wiper position.

W

t

R

6

FN8160.2

September 26, 2006

Basic Configurations of Electronic Potentiometers

www.BDTIC.com/Intersil

V

R

V

H

V

L

VW/R

W

X9116

V

R

I

Basic Circuits

R

+V

1

V

REF

THREE-TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER

+5V

V

W

V

+

–

OUT

OP-07

–5V

= VW/R

V

OUT

W

VOLTAGE REGULATOR

CASCADING TECHNIQUESBUFFERED REFERENCE VOLTAGE

+V +V

VW/R

W

+V

(a) (b)

TWO-TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT

NONINVERTING AMPLIFIER

+5V

V

S

X

V

W

+

–

R

1

VO = (1+R2/R1)V

COMPARATOR WITH HYSTERESIS

-5V

LM308A

R

2

S

V

O

IN

317

R

I

adj

R

2

VO (REG) = 1.25V (1+R2/R1)+Iadj R

1

VO (REG)V

2

LT311A

V

S

}

R

1

= {R1/(R1+R2)} VO(max)

V

UL

= {R1/(R1+R2)} VO(min)

V

LL

(FOR ADDITIONAL CIRCUITS, SEE AN115)

7

–

+

}

R

2

V

O

FN8160.2

September 26, 2006

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

X9116

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

8

FN8160.2

September 26, 2006

X9116

www.BDTIC.com/Intersil

Mini Small Outline Plastic Packages (MSOP)

N

EE1

INDEX

AREA

AA1A2

-H-

SIDE VIEW

12

TOP VIEW

b

e

D

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

.

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only.

-B-

0.20 (0.008) A

GAUGE

PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING
PLANE

a

0.20 (0.008) C

- H -

B

4X θ

C

D

4X θ

L1

C

C

L

E

1

END VIEW

R1

R

L

-B-

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.010 0.014 0.25 0.36 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.026 BSC 0.65 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N8 87

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

05

α

o

o

0

15

o

o

6

o

5

o

0

15

o

o

6

Rev. 2 01/03

NOTESMIN MAX MIN MAX

-

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

9

FN8160.2

September 26, 2006