intersil X9111 DATA SHEET

®
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Single Supply/Low Power/1024-Tap/SPI Bus
Data Sheet September 15, 2006
Single Digitally-Controlled (XDCP™) Potentiometer
The X9111 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit.
The digital controlled potentiometer is implemented using 1023 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
FN8159.4
Features
• 1024 Resistor Taps – 10-Bit Resolution
• SPI Serial Interface for Write, Read, And Transfer Operations Of The Potentiometer
• Wiper Resistance, 40 Typical @ 5V
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on Power-Up.
• Standby Current <3µA Max
: 2.7V to 5.5V Operation
•V
CC
•100kΩ End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes Per Bit Per Register
• 14 Ld TSSOP
• Low Power CMOS
• Single Supply Version of the X9110
Functional Diagram
SPI Bus
Interface
Address
Data
Status
V
CC
Bus
Interface &
Control
Write Read
Transfer
Control
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
TSSOP
14
V
CC
R
13
12
11
10
L
R
H
R
W
HOLD A1
9 8
WP
Power On Recall
Wiper Counter
Register (WCR)
Data Registers
(DR0-DR3)
SO
A0
NC
CS
SCK
V
SS
SI
1
2
3
4
5
6
7
Wiper
X9111
R
H
100k 1024-taps
POT
V
SS
1
XDCP is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
NC
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
R
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
R
W
L
X9111
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Ordering Information
POTENTIOMETER
PART NUMBER PART MARKING VCC LIMITS (V)
X9111TV14I X9111TV I 5 ±10% 100 -40 to +85 14 Ld TSSOP (4.4mm) X9111TV14IZ (Note) X9111TV ZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) X9111TV14 X9111TV 0 to +70 14 Ld TSSOP (4.4mm) X9111TV14Z (Note) X9111TV Z 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) X9111TV14-2.7 X9111TV F 2.7 to 5.5 0 to +70 14 Ld TSSOP (4.4mm) X9111TV14Z-2.7 (Note) X9111TV ZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) X9111TV14I-2.7* X9111TV G -40 to +85 14 Ld TSSOP (4.4mm) X9111TV14IZ-2.7* (Note) X9111TV ZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free)
*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ORGANIZATION (k) TEMP RANGE (°C) PACKAGE
Detailed Functional Diagram
V
CC
HOLD
CS
SCK
SO
SI
A0
A1
WP
Interface
and
Control
Circuitry
V
SS
Data
Control
Circuit Level Applications
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
Power On
Recall
DR0 DR1
DR2 DR3
Wiper
Counter Register
(WCR)
100k 1024-taps
R
H
R
L
R
W
System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for senso rs in in d ust ri al systems
• Trim offset and gain errors in artificial intelligent systems
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Pin Descriptions
PIN
(TSSOP) SYMBOL FUNCTION
1 SO Serial Data Output 2 A0 Device Address 3 NC No Connect 4CS 5 SCK Serial Clock 6 SI Serial Data Input 7V 8WPHardware Write Protect
9 A1 Device Address 10 HOLD 11 R 12 R 13 R 14 V
SS
CC
Chip Select
System Ground
Device Select. Pause the Serial Bus Wiper Terminal of the Potentiometer
W
High Terminal of the Potentiometer
H
Low Terminal of the Potentiometer
L
System Supply Voltage
Pin Descriptions
Bus Interface Pins
SERIAL OUTPUT (SO)
SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.
SERIAL INPUT (SI)
SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the X9111.
HOLD (HOLD
is used in conjunction with the CS pin to select the
HOLD device. Once the part is selected and a serial sequence is underway , HOLD communication with the controller without resetting the serial sequence. To pause, HOLD LOW. To resume communication, HOLD while SCK is LOW. If the p ause feature is not used, HOLD be held HIGH at all times.
DEVICE ADDRESS (A
The address inputs are used to set the 8-bit slave address. A match in the slave address serial data stream must be made with the address input (A1–A0) in order to initiate communication with the X9111.
)
may be used to pause the serial
must be brought LOW while SCK is
is brought HIGH, again
, A1)
0
should
CHIP SELECT (CS
When CS high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS enables the X9111, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS
HARDWARE WRITE PROTECT INPUT (WP
The WP Data Registers.
is HIGH, the X9111 is deselected and the SO pin is at
pin when LOW prevents nonvolatile writes to the
)
LOW
is required prior to the start of any operation.
)
Potentiometer Pins
RH, RL
and RL pins are equivalent to the terminal connections
The R
H
on a mechanical potentiometer.
R
W
The wiper pin is equivalent to the wiper terminal of a mechanical potentiometer.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (V
The V
CC
the system ground.
)
SS
pin is the system supply voltage. The VSS pin is
Other Pins
NO CONNECT (NC)
Pin should be left open. This pin is used for Intersil manufacturing and test purposes.
Principles of Operation Device Description
Serial Interface
The X9111 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked-in on the rising SCK. CS must be HIGH during the entire operation.
The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count.
Array Description
The X9111 is comprised of a resistor array (see Figure 1). The array contains the equivalent of 1023 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed te rmi nals of a mechanical potentiometer (R
At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (R output. Within the individual array only one switch may be turned on at a time.
must be LOW and the HOLD and WP pins
and RL inputs).
H
)
W
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Serial Data Path
From Interface
Circuitry
If WCR = 000[HEX] then RW = R If WCR = 3FF[HEX] then RW = R
Register 0
(DR0)
10 10
Register 2
(DR2)
L
H
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
Register 1
(DR1)
Register 3
(DR3)
These switches are controlled by a Wiper Counter Register (WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select, and enable, one of 1024 switches.
Wiper Counter Register (WCR)
The X9111 contains a Wiper Counter Register (see Table 1) for the XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 1024 switches along its resistor array. The contents of the WCR can be altered in one of three ways: (1) it may be written directly by the host via the write Wiper Counter Register instruction (serial load); (2) it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register; (3) it is loaded with the contents of its Data Register zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9111 is powered-down. Although the register is automatically loaded with the value in R0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the R0 value into the WCR.
Data Registers (DR3 to DR0)
The potentiometer has four 10-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms.
Serial Bus Input
Parallel Bus Input
Wiper
Counter
Register
(WCR)
C O U N T E R
D E C O D E
R
H
R
L
R
W
If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data.
A DR[9:0] is used to store one of the 1024 wiper position (0 ~1023). Table 2
Status Register (SR)
This 1-bit status register is used to store the system status (see Table 3).
WIP: Write In Progress status bit, read only.
• When WIP=1, indicates that high-voltage write cycle is in progress.
• When WIP=0, indicates that no high-voltage write cycle is in progress.
Device Instructions
Identification Byte (ID and A)
The first byte sent to the X9111 from the host, following a CS going HIGH to LOW, is called the Identification Byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device ID for the X9111; this is fixed as 0101[B] (refer to Table 4).
The A1–A0 bits in the ID byte are the internal slave address. The physical device address is defined by the state of the A1–A0 input pins. The slave address is externally specified by the user. The X9111 compares the serial data stream with the address input state; a successful compare of the address
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bits is required for the X9111 to successfully continue the command sequence. Only the device whose slave address matches the incoming device address sent by the master executes the instruction. The A1–A0 inputs can be actively driven by CMOS input signals or tied to V R/W
bit is used to set the device to either read or write
or VSS. The
CC
Instruction Byte and Register Selection
The next byte sent to the X9111 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (I[2:0]). The RB and RA bits point to one of the four registers. The format is shown in Table 5.
mode.
TABLE 1. WIPER LATCH, WL (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V)
WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
VVVVVVVVVV
(MSB) (LSB)
TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE, NV)
BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NV NV NV NV NV NV NV NV NV NV
MSB LSB
TABLE 3. STATUS REGISTER, SR (1-BIT)
WIP
(LSB)
TABLE 3. IDENTIFICATION BYTE FORMAT
DR0 DR1 DR2 DR3
Internal Slave
Address
Read or Write Bit
Device Type
Identifier
ID3 ID2 ID1 ID0 0 A1 A0 R/W
0101
(MSB) (LSB)
TABLE 4. INSTRUCTION BYTE FORMAT
Instruction
Opcode
I2 I1 I0 0 RB RA 0 0
(MSB) (LSB)
Register
Selection
RB RA REGISTER
0 0 1 1
0 1 0 1
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Five of the seven instructions are four bytes in length. These instructions are:
Read Wiper Counter Register – read the current wiper position of the selected pot,
Write Wiper Counter Register – change current wiper position of the selected pot,
Read Data Register – read the contents of the selected data register;
Write Data Register – write a new value to the selected data register.
Read Status – This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress.
The basic sequence of the four byte instructions is illustrated in Figure 3. These four-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between the potentiometer and one of its associated registers. The Read Status Register instruction is the only unique format (see Figure 4).
Two instructions require a two-byte sequence to complete (see Figure 2). These instructions transfer data between the
host and the X9111; either between the host and one of th e Data Registers or directly between the host and the Wiper Counter Register. These instructions are:
XFR Data Register to Wiper Counter Register –This transfers the contents of one specified Data Register to the associated Wiper Counter Register.
XFR Wiper Counter Register to Data Register – This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register.
See Instruction format for more details.
Write in Process (WIP bit)
The contents of the Data Registers are saved to nonvolatile memory when the CS
pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a Write In Process bit (WIP). The WIP bit is read with a Read Status command (see Figure 4).
Power Up and Down Requirements
There are no restrictions on the power-up condition of VCC and the voltages applied to the potentiometer pins provided that the V voltages at R are no restrictions on the power-down condition. However, the datasheet parameters for the DCP do not apply until 1millisecond after V
is always more positive than or equal to the
CC
, RL, and RW, i.e., VCC RH, RL, RW. There
H
reaches its final value.
CC
CS
SCK
SI
ID3 ID2 ID1 ID0 0
CS
SCK
SI
0101 0
Device ID
FIGURE 3. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)
0101
ID3 ID2 ID1 ID0 0 A1 A0
Device ID Internal Instruction
FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE
0
A1
A0
I2
R/W
I1I00 RB RA
Internal Address
Instruction
Opcode
0
0
X
Register Address
X0
00
0
R/W
XX
I2
I1 I0 RB RA
OpcodeAddress
XXX
0
Register Address
X
W
W
W
W
C R 7
W
C
C
R
R
6
5
Wiper
Position
C
C
R
R
9
8
0
0
0
0
W
W
W
W
C
C
R
R
4
3
W
C
C
C
R
R
R
2
1
0
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CS
SCK
SI
01010
ID3 ID2 ID1ID0 0 A0R/W
Device ID
Internal
Address
A1
1
I2
I1
Instruction
Opcode
I0
0
X
RB RA
0
Register
Address
X0
00
0
XX
XXX
X
X
X
0
00
0
0
0
0
WIP
Status
Bit
FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)
TABLE 5. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
Read Wiper Counter Register
Write Wiper Counter Register
I
I
I
3
2
0RBRA0 0
1
1 1 0 0 0 0 0 0 0 Read the contents of the Wiper Counter
Register
0 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter
Register
OPERATIONR/W
Read Data Register 1 1 0 1 0 1/0 1/0 0 0 Read the contents of the Data Register
pointed to RB-RA
Write Data Register 0 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register
pointed to RB-RA
XFR Data Register to Wiper Counter Register
1 1 1 0 0 1/0 1/0 0 0 Transfer the contents of the Data Register
pointed to by RB-RA to the Wiper Counter Register
XFR Wiper Counter Register to Data Register
0 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Coun ter
Register to the Data Register pointed to by RB-RA
Read Status (WIP bit) 1 0 1 0 0 0 0 0 1 Read the status of the internal write cycle,
by checking the WIP bit (read status register).
NOTE: 1/0 = data is one or zero
Instruction Format
Read Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
01010A1A0
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by X9111 on SO)
10000000XXXXXX
R/ W = 1
Write Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
01010A1A0
Device
Addresses
7
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by Master on SI)
10100000XXXXXX
R/ W = 0
Wiper Position
(sent by X9111 on SO)
W
W
W
W
W
W
W
W
C
C
C
C
C
R
R
R
9
8
7
(Sent by Master on SI)
W
W
W
C
C
C
R
R
R
9
8
7
C
R
R
R
6
5
4
Wiper Position
W
W
W
C
C
C
R
R
R
6
5
4
W
C
C
C
R
R
R
3
2
1
W
W
W
C
C
C
R
R
R
3
2
1
CS
W
Rising
C
Edge
R
0
CS
W
Rising
C
Edge
R
0
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Read Data Register (DR)
Device
Type
Identifier
CS
Falling
Edge
01010A1A0
Write Data Register (DR)
Device Type
Identifier
CS
Falling
Edge
01010A1A0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
CS
Falling
Edge
Identifier
01010A1A0
Device
Addresses
Device
Addresses
Addresses
Instruction
Opcode
1010RBRA00XXXXXX
R/ W = 1
Instruction
Opcode
1100
R/ W = 0
Device
Instruction
1100RBRA00
R/ W = 1
Addresses
RBR
Opcode
Register
Addresses
Register
0 0XXXXXX
A
(Sent by X9111 on SO)
Wiper Position or Data (Sent by Master on SI)
Register
Addresses
Wiper Position
W C R
CS
Rising
Edge
Wiper Position
(sent by X9111 on SO)
W
W
W
W
W
W
W
W
C
C
C
C
C
R
R
R
9
8
7
Wiper Position or Data (Sent by Master on SI)
W
W
W C R
9
8
W
C
C
C
R
R
R
7
6
5
C
R
R
R
6
5
4
W
W
W
C
C
C
R
R
R
4
3
2
W
C
C
C
R
R
R
3
2
1
Rising
W
W
Edge
C
C
R
R
1
0
CS
CS
Rising
W
Edge
C R 0
WRITE CYCLE
HIGH-VOLTAGE
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
01010A1A0
Device
Addresses
Instruction
Opcode
1110 RB RA 0 0
R/ W = 0
Register Addresses
Read Status Register (SR)
Device Type
Identifier
CS
Falling
Edge
01010A1A0
NOTES:
1. “A0 and A1”: stand for the device address sent by the master.
2. WCRx refers to wiper position data in the Wiper Counter Register
3. “X”: Don’t Care.
Device
Addresses
Instruction
Opcode
01000001XXXXXXXX00 00000
R/ W = 1
Register
Addresses
(Sent by Slave on SO)
CS
Rising
Edge
Status Data
HIGH-VOLTAGE
WRITE CYCLE
(Sent by Slave on SO)
Status Data
WI
P
CS
Rising
Edge
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Absolute Maximum Ratings Recommended Operating Conditions
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on SCK any address input
with respect to V
V = | (VH–VL) |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to Vcc
Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . .+300°C
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
I
W
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
. . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
SS
Analog Characteristics Over recommended industrial operation conditions unless otherwise st at ed.
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
R
TOTAL
I
W
R
W
V
TERM
C
H/CL/CW
End to End Resistance 100 k End to End Resistance Tolerance ±20 % Power Rating +25°C, each pot 50 mW Wiper Current ±3 mA Wiper Resistance Wiper Current = ±50µA,
= 5V
V
CC
Wiper Current = ±50µA,
= 3V
V
CC
Voltage on any RH or RL Pin V Noise Ref: 1V -120 dBV Resolution 1.6 % Absolute Linearity (Note 1) R
Relative Linearity (Note 2) R
Temperature Coefficient of R Ratiometric Temp. Coefficient 20 ppm/°C Potentiometer Capacitancies See Macro model 10/10/25 pF
TOTAL
= 0V V
SS
w(n)(actual)
n = 8 to 1006 R
w(n)(actual)
-[R
w(m + 1)
1006
w(m + 1)
-[R
R
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (V
X9111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
X9111-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
-R
w(n)(expected)
-R
w(n)(expected)
+ MI], where m = 8 to
w(m)
+ MI] (Note 4) ±0.5 ±1.0 MI (Note 3)
w(m)
, where
(Note 4) ±1.5 ±2.0 MI (Note 3)
CC
) Limits
SS
40 110
150 300
V
CC
±1 MI (Note 3)
±0.5 MI (Note 3)
±300 ppm/°C
V
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size.
3. MI = RTOT/1023 or (R
4. n = 0, 1, 2, …,1023; m =0, 1, 2, …, 1022.
5. ESD Rating on RH, RL, RW pins is 1.5kV (HBM, 1.0µA leakage maximum), ESD rating on all other pins is 2.0kV.
– RL)/1023, single pot
H
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X9111
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D.C. Operating Characteristics Over the recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNITS
I
CC1
I
CC2
I
I I V V
V V V
SB
LO
VCC supply current (active)
VCC supply current (nonvolatile write)
VCC current (standby) SCK = SI = VSS, Addr. = VSS,
Input leakage current VIN = VSS to V
LI
Output leakage current V Input HIGH voltage VCC x 0.7 VCC + 1 V
IH
Input LOW voltage -1 VCC x 0.3 V
IL
Output LOW voltage IOL = 3mA 0.4 V
OL
Output LOW voltage IOH = -1mA, VCC +3V VCC - 0.8 V
OL
Output LOW voltage IOH = -0.4mA, VCC +3V VCC - 0.4 V
OL
Endurance And Data Retention
PARAMETER MIN UNITS
Minimum Endurance 100,000 Data changes per bit per register
Data Retention 100 years
f
= 2.5 MHz, SO = Open, V
SCK
Other Inputs = V f
= 2.5MHz, SO = Open, V
SCK
Other Inputs = V
= VCC = 5.5V
CS
= VSS to V
OUT
SS
SS
CC
CC
CC
CC
= 5.5V
= 5.5V
400 µA
15mA
3 µA
10 µA 10 µA
Capacitance
SYMBOL TEST TEST CONDITIONS MAX UNITS
C
(Note 6) Input/Output capacitance (SI) V
IN/OUT
(Note 6) Output capacitance (SO) V
C
OUT
(Note 6) Input capacitance (A0, CS, WP, HOLD, and SCK) VIN = 0V 6 pF
C
IN
= 0V 8 pF
OUT
= 0V 8 pF
OUT
Power-Up Timing
SYMBOL PARAMETER MIN MAX UNITS
(Note 6) VCC power-up rate 0.2 50 V/ms
t
r VCC
(Note 7) Power-up to initiation of read operation 1 ms
t
PUR
(Note 7) Power-up to initiation of write operation 50 ms
t
PUW
NOTES:
6. This parameter is not 100% tested. and t
7. t
PUR
parameters are not 100% tested.
are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These
PUW
A.C. Test Conditions
nput pulse levels VCC x 0.1 to VCC x 0.9
I
Input rise and fall times 10ns Input and output timing level V
CC
x 0.5
10
FN8159.4
September 15, 2006
Equivalent A.C. Load Circuit
www.BDTIC.com/Intersil
X9111
1217
3V
1382
100pF
SPICE Macromodel
R
H
C
10pF
L
R
TOTAL
R
W
C
W
25pF
C
L
10pF
SO pin
2714
5V
1462
SO pin
100pF
AC Timing
SYMBOL PARAMETER MIN MAX UNITS
f
SCK
t
CYC
t
WH
t
WL
t
LEAD
t
LAG
t
SU
t
H
t
RI
t
FI
t
DIS
t
V
t
HO
t
RO
t
FO
t
HOLD
t
HSU
t
HH
t
HZ
t
LZ
T
t
CS
t
WPASU
t
WPAH
I
SSI/SPI clock frequency 2.0 MHz SSI/SPI clock cycle time 400 ns SSI/SPI clock high time 150 ns SSI/SPI clock low time 150 ns Lead time 150 ns Lag time 150 ns SI, SCK, HOLD and CS input setup time 50 ns SI, SCK, HOLD and CS input hold time 50 ns SI, SCK, HOLD and CS input rise time 50 ns SI, SCK, HOLD and CS input fall time 50 ns SO output disable time 0 500 ns SO output valid time 100 ns SO output hold time 0 ns SO output rise time 50 ns SO output fall time 50 ns HOLD time 400 ns HOLD setup time 50 ns HOLD hold time 50 ns HOLD low to output in high Z 100 ns HOLD high to output in low Z 100 ns Noise suppression time constant at
SI, SCK, HOLD CS deselect time 100 ns WP, A0, A1 setup time 0 ns WP, A0, A1 hold time 0 ns
and CS inputs
20 ns
R
L
11
FN8159.4
September 15, 2006
X9111
www.BDTIC.com/Intersil
High-voltage Write Cycle Timing
SYMBOL PARAMETER TYP MAX UNITS
t
WR
High-voltage write cycle time (store instructions) 5 10 ms
XDCP Timing
SYMBOL PARAMETER MIN MAX UNITS
t
WRPO
t
WRL
Wiper response time after the third (last) power supply is stable 5 10 µs Wiper response time after instruction issued (all load instructions) 5 10 µs
Symbol Table
WAVEFORM INPUTS OUTPUTS
Must be steady
May change from Low to High
May change from High to Low
Don’t Care: Changes Allowed
N/A Center Line
Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
is High Impedance
12
FN8159.4
September 15, 2006
Timing Diagrams
www.BDTIC.com/Intersil
Input Timing
CS
t
LEAD
X9111
t
CYC
t
CS
t
LAG
SCK
SI
SO
Output Timing
CS
SCK
SO
ADDR
SI
t
SU
MSB LSB
High Impedance
t
H
t
V
MSB LSB
t
WL
t
HO
t
...
WH
...
...
...
t
FI
t
RI
t
DIS
Hold Timing
CS
SCK
SO
SI
HOLD
t
HSU
t
RO
t
FO
t
HOLD
t
HZ
13
t
HH
...
t
LZ
FN8159.4
September 15, 2006
XDCP Timing (for All Load Instructions)
www.BDTIC.com/Intersil
CS
X9111
SCK
MSB LSB
R
SO
SI
W
High Impedance
Write Protect and Device Address Pins Timing
CS
t
WP
A0
A1
WPASU
Applications information
Basic Configurations of Electronic Potentiometers
...
...
(Any Instruction)
t
WPAH
t
WRL
V
R
Three terminal Potentiometer; Variable voltage divider
RW
+V
R
I
Two terminal Variable Resistor; Variable current
14
FN8159.4
September 15, 2006
Application Circuits
www.BDTIC.com/Intersil
Noninverting Amplifier Voltage Regulator
X9111
V
S
VO = (1+R2/R1)V
+
R
R
1
S
V
O
2
IN
VO (REG) = 1.25V (1+R2/R1)+I
317
R
I
adj
R
2
Offset Voltage Adjustment Comparator with Hysterisis
+
R
2
TL072
V
S
V
O
}
R
VUL = {R1/(R1+R2)} VO(max)
= {R1/(R1+R2)} VO(min)
RL
L
+
}
R
2
1
V
S
10k
R
1
100k
-12V+12V
10k10k
1
adj R2
V
VO (REG)V
O
15
FN8159.4
September 15, 2006
Application Circuits (Continued)
www.BDTIC.com/Intersil
Attenuator Filter
R
1
V
S
R
3
R
VO = G V
-1/2 G +1/2
+
4
R1 = R2 = R3 = R4 = 10k
S
Inverting Amplifier Equivalent L-R Circuit
R
R
V
S
2
1
}
}
X9111
C
V
R
2
V
O
+
V
O
S
R
G
O
fc = 1/(2πRC)
C
1
V
S
+
R
1
= 1 + R2/R
R
V
O
R
2
1
2
+
VO = G V G = - R2/R
S
1
Function Generator
+
frequency R1, R2, C amplitudeR
, R
A
B
R
Z
IN
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R
R
2
R
}
A
R
}
B
R
1
+
1
R
3
+ R3) >> R
1
C
2
16
FN8159.4
September 15, 2006
X9111
www.BDTIC.com/Intersil
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
INDEX AREA
123
0.05(0.002)
-A­D
e
b
0.10(0.004) C AM BS
NOTES:
1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen­sion at maximum material condition. Minimum space between protru­sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
E1
-B-
SEATING PLANE
A
-C-
M
0.25(0.010) BM M
E
α
A1
0.10(0.004)
GAUGE PLANE
0.25
0.010
A2
L
c
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.041 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.195 0.199 4.95 5.05 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N14 147
o
α
0
o
8
o
0
o
8
NOTESMIN MAX MIN MAX
-
Rev. 2 4/06
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or i t s sub sidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
FN8159.4
September 15, 2006
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