intersil X9111 DATA SHEET

®

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X9111

Single Supply/Low Power/1024-Tap/SPI Bus

Data Sheet September 15, 2006

Single Digitally-Controlled (XDCP™)
Potentiometer

The X9111 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.

The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.

The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.

FN8159.4

Features

• 1024 Resistor Taps – 10-Bit Resolution

• SPI Serial Interface for Write, Read, And Transfer
Operations Of The Potentiometer

• Wiper Resistance, 40Ω Typical @ 5V

• Four Non-Volatile Data Registers

• Non-Volatile Storage of Multiple Wiper Positions

• Power On Recall. Loads Saved Wiper Position on
Power-Up.

• Standby Current <3µA Max

: 2.7V to 5.5V Operation

•V

CC

•100kΩ End to End Resistance

• 100 yr. Data Retention

• Endurance: 100,000 Data Changes Per Bit Per Register

• 14 Ld TSSOP

• Low Power CMOS

• Single Supply Version of the X9110

Functional Diagram

SPI
Bus

Interface

Address

Data

Status

V

CC

Bus

Interface &

Control

Write
Read

Transfer

Control

• Pb-Free Plus Anneal Available (RoHS Compliant)

Pinout

TSSOP

14

V

CC

R

13

12

11

10

L

R

H

R

W

HOLD
A1

9
8

WP

Power On Recall

Wiper Counter

Register (WCR)

Data Registers

(DR0-DR3)

SO

A0

NC

CS

SCK

V

SS

SI

1

2

3

4

5

6

7

Wiper

X9111

R

H

100kΩ
1024-taps

POT

V

SS

1

XDCP is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

NC

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

R

Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

R

W

L

X9111

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Ordering Information

POTENTIOMETER

PART NUMBER PART MARKING VCC LIMITS (V)

X9111TV14I X9111TV I 5 ±10% 100 -40 to +85 14 Ld TSSOP (4.4mm)
X9111TV14IZ (Note) X9111TV ZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free)
X9111TV14 X9111TV 0 to +70 14 Ld TSSOP (4.4mm)
X9111TV14Z (Note) X9111TV Z 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free)
X9111TV14-2.7 X9111TV F 2.7 to 5.5 0 to +70 14 Ld TSSOP (4.4mm)
X9111TV14Z-2.7 (Note) X9111TV ZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free)
X9111TV14I-2.7* X9111TV G -40 to +85 14 Ld TSSOP (4.4mm)
X9111TV14IZ-2.7* (Note) X9111TV ZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free)

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE

Detailed Functional Diagram

V

CC

HOLD

CS

SCK

SO

SI

A0

A1

WP

Interface

and

Control

Circuitry

V

SS

Data

Control

Circuit Level Applications

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier
circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and
Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF circuits

• Provide a control variable (I, V, or R) in feedback circuits

Power On

Recall

DR0 DR1

DR2 DR3

Wiper

Counter
Register

(WCR)

100kΩ
1024-taps

R

H

R

L

R

W

System Level Applications

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems

• Control the gain in audio and home entertainment systems

• Provide the variable DC bias for tuners in RF wireless
systems

• Set the operating points in temperature control systems

• Control the operating point for senso rs in in d ust ri al
systems

• Trim offset and gain errors in artificial intelligent systems

2

FN8159.4

September 15, 2006

X9111

www.BDTIC.com/Intersil

Pin Descriptions

PIN

(TSSOP) SYMBOL FUNCTION

1 SO Serial Data Output
2 A0 Device Address
3 NC No Connect
4CS
5 SCK Serial Clock
6 SI Serial Data Input
7V
8WPHardware Write Protect

9 A1 Device Address
10 HOLD
11 R
12 R
13 R
14 V

SS

CC

Chip Select

System Ground

Device Select. Pause the Serial Bus
Wiper Terminal of the Potentiometer

W

High Terminal of the Potentiometer

H

Low Terminal of the Potentiometer

L

System Supply Voltage

Pin Descriptions

Bus Interface Pins

SERIAL OUTPUT (SO)

SO is a serial data output pin. During a read cycle, data is
shifted out on this pin. Data is clocked out by the falling edge
of the serial clock.

SERIAL INPUT (SI)

SI is the serial data input pin. All opcodes, byte addresses and
data to be written to the pots and pot registers are input on this
pin. Data is latched by the rising edge of the serial clock.

SERIAL CLOCK (SCK)

The SCK input is used to clock data into and out of the
X9111.

HOLD (HOLD

is used in conjunction with the CS pin to select the

HOLD
device. Once the part is selected and a serial sequence is
underway , HOLD
communication with the controller without resetting the serial
sequence. To pause, HOLD
LOW. To resume communication, HOLD
while SCK is LOW. If the p ause feature is not used, HOLD
be held HIGH at all times.

DEVICE ADDRESS (A

The address inputs are used to set the 8-bit slave address. A
match in the slave address serial data stream must be made
with the address input (A1–A0) in order to initiate
communication with the X9111.

)

may be used to pause the serial

must be brought LOW while SCK is

is brought HIGH, again

, A1)

0

should

CHIP SELECT (CS

When CS
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state. CS
enables the X9111, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS

HARDWARE WRITE PROTECT INPUT (WP

The WP
Data Registers.

is HIGH, the X9111 is deselected and the SO pin is at

pin when LOW prevents nonvolatile writes to the

)

LOW

is required prior to the start of any operation.

)

Potentiometer Pins

RH, RL

and RL pins are equivalent to the terminal connections

The R

H

on a mechanical potentiometer.

R

W

The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.

Bias Supply Pins

SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (V

The V

CC

the system ground.

)

SS

pin is the system supply voltage. The VSS pin is

Other Pins

NO CONNECT (NC)

Pin should be left open. This pin is used for Intersil
manufacturing and test purposes.

Principles of Operation
Device Description

Serial Interface

The X9111 supports the SPI interface hardware conventions.
The device is accessed via the SI input with data clocked-in on
the rising SCK. CS
must be HIGH during the entire operation.

The SO and SI pins can be connected together, since they
have three state outputs. This can help to reduce system pin
count.

Array Description

The X9111 is comprised of a resistor array (see Figure 1).
The array contains the equivalent of 1023 discrete resistive
segments that are connected in series. The physical ends of
each array are equivalent to the fixed te rmi nals of a
mechanical potentiometer (R

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (R
output. Within the individual array only one switch may be
turned on at a time.

must be LOW and the HOLD and WP pins

and RL inputs).

H

)

W

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FN8159.4

September 15, 2006

X9111

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Serial Data Path

From Interface

Circuitry

If WCR = 000[HEX] then RW = R
If WCR = 3FF[HEX] then RW = R

Register 0

(DR0)

10 10

Register 2

(DR2)

L

H

FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM

Register 1

(DR1)

Register 3

(DR3)

These switches are controlled by a Wiper Counter Register
(WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to
select, and enable, one of 1024 switches.

Wiper Counter Register (WCR)

The X9111 contains a Wiper Counter Register (see Table 1)
for the XDCP potentiometer. The WCR is equivalent to a
serial-in, parallel-out register/counter with its outputs
decoded to select one of 1024 switches along its resistor
array. The contents of the WCR can be altered in one of
three ways: (1) it may be written directly by the host via the
write Wiper Counter Register instruction (serial load); (2) it
may be written indirectly by transferring the contents of one
of four associated Data Registers via the XFR Data Register;
(3) it is loaded with the contents of its Data Register zero
(DR0) upon power-up.

The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9111 is powered-down.
Although the register is automatically loaded with the value
in R0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loadings of the R0 value into
the WCR.

Data Registers (DR3 to DR0)

The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the Wiper Counter Register. All operations
changing data in one of the Data Registers is a nonvolatile
operation and will take a maximum of 10ms.

Serial
Bus
Input

Parallel
Bus
Input

Wiper

Counter

Register

(WCR)

C
O
U
N
T
E
R

D
E
C
O
D
E

R

H

R

L

R

W

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.

A DR[9:0] is used to store one of the 1024 wiper position (0
~1023). Table 2

Status Register (SR)

This 1-bit status register is used to store the system status
(see Table 3).

WIP: Write In Progress status bit, read only.

• When WIP=1, indicates that high-voltage write cycle is in
progress.

• When WIP=0, indicates that no high-voltage write cycle is
in progress.

Device Instructions

Identification Byte (ID and A)

The first byte sent to the X9111 from the host, following a CS
going HIGH to LOW, is called the Identification Byte. The
most significant four bits of the slave address are a device
type identifier. The ID[3:0] bits is the device ID for the X9111;
this is fixed as 0101[B] (refer to Table 4).

The A1–A0 bits in the ID byte are the internal slave address.
The physical device address is defined by the state of the
A1–A0 input pins. The slave address is externally specified
by the user. The X9111 compares the serial data stream with
the address input state; a successful compare of the address

4

FN8159.4

September 15, 2006

X9111

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bits is required for the X9111 to successfully continue the
command sequence. Only the device whose slave address
matches the incoming device address sent by the master
executes the instruction. The A1–A0 inputs can be actively
driven by CMOS input signals or tied to V
R/W

bit is used to set the device to either read or write

or VSS. The

CC

Instruction Byte and Register Selection

The next byte sent to the X9111 contains the instruction and
register pointer information. The three most significant bits
are used provide the instruction opcode (I[2:0]). The RB and
RA bits point to one of the four registers. The format is
shown in Table 5.

mode.

TABLE 1. WIPER LATCH, WL (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V)

WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0

VVVVVVVVVV

(MSB) (LSB)

TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE, NV)

BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

NV NV NV NV NV NV NV NV NV NV

MSB LSB

TABLE 3. STATUS REGISTER, SR (1-BIT)

WIP

(LSB)

TABLE 3. IDENTIFICATION BYTE FORMAT

DR0
DR1
DR2
DR3

Internal Slave

Address

Read or
Write Bit

Device Type

Identifier

ID3 ID2 ID1 ID0 0 A1 A0 R/W

0101

(MSB) (LSB)

TABLE 4. INSTRUCTION BYTE FORMAT

Instruction

Opcode

I2 I1 I0 0 RB RA 0 0

(MSB) (LSB)

Register

Selection

RB RA REGISTER

0
0
1
1

0
1
0
1

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FN8159.4

September 15, 2006

X9111

www.BDTIC.com/Intersil

Five of the seven instructions are four bytes in length. These
instructions are:

• Read Wiper Counter Register – read the current wiper
position of the selected pot,

• Write Wiper Counter Register – change current wiper
position of the selected pot,

• Read Data Register – read the contents of the selected
data register;

• Write Data Register – write a new value to the selected
data register.

• Read Status – This command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress.

The basic sequence of the four byte instructions is illustrated
in Figure 3. These four-byte instructions exchange data
between the WCR and one of the Data Registers. A transfer
from a Data Register to a WCR is essentially a write to a
static RAM, with the static RAM controlling the wiper
position. The response of the wiper to this action will be
delayed by tWRL. A transfer from the WCR (current wiper
position), to a Data Register is a write to nonvolatile memory
and takes a minimum of tWR to complete. The transfer can
occur between the potentiometer and one of its associated
registers. The Read Status Register instruction is the only
unique format (see Figure 4).

Two instructions require a two-byte sequence to complete
(see Figure 2). These instructions transfer data between the

host and the X9111; either between the host and one of th e
Data Registers or directly between the host and the Wiper
Counter Register. These instructions are:

• XFR Data Register to Wiper Counter Register –This
transfers the contents of one specified Data Register to
the associated Wiper Counter Register.

• XFR Wiper Counter Register to Data Register – This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.

See Instruction format for more details.

Write in Process (WIP bit)

The contents of the Data Registers are saved to nonvolatile
memory when the CS

pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
progress of this internal write operation can be monitored by
a Write In Process bit (WIP). The WIP bit is read with a Read
Status command (see Figure 4).

Power Up and Down Requirements

There are no restrictions on the power-up condition of VCC
and the voltages applied to the potentiometer pins provided
that the V
voltages at R
are no restrictions on the power-down condition. However,
the datasheet parameters for the DCP do not apply until
1millisecond after V

is always more positive than or equal to the

CC

, RL, and RW, i.e., VCC ≥ RH, RL, RW. There

H

reaches its final value.

CC

CS

SCK

SI

ID3 ID2 ID1 ID0 0

CS

SCK

SI

0101 0

Device ID

FIGURE 3. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)

0101

ID3 ID2 ID1 ID0 0 A1 A0

Device ID Internal Instruction

FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE

0

A1

A0

I2

R/W

I1I00 RB RA

Internal
Address

Instruction

Opcode

0

0

X

Register
Address

X0

00

0

R/W

XX

I2

I1 I0 RB RA

OpcodeAddress

XXX

0

Register
Address

X

W

W

W

W

C
R
7

W

C

C

R

R

6

5

Wiper

Position

C

C

R

R

9

8

0

0

0

0

W

W

W

W

C

C

R

R

4

3

W

C

C

C

R

R

R

2

1

0

6

FN8159.4

September 15, 2006