The X9111 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.
The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
FN8159.4
Features
• 1024 Resistor Taps – 10-Bit Resolution
• SPI Serial Interface for Write, Read, And Transfer
Operations Of The Potentiometer
• Wiper Resistance, 40Ω Typical @ 5V
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
Power-Up.
• Standby Current <3µA Max
: 2.7V to 5.5V Operation
•V
CC
•100kΩ End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes Per Bit Per Register
• 14 Ld TSSOP
• Low Power CMOS
• Single Supply Version of the X9110
Functional Diagram
SPI
Bus
Interface
Address
Data
Status
V
CC
Bus
Interface &
Control
Write
Read
Transfer
Control
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
TSSOP
14
V
CC
R
13
12
11
10
L
R
H
R
W
HOLD
A1
9
8
WP
Power On Recall
Wiper Counter
Register (WCR)
Data Registers
(DR0-DR3)
SO
A0
NC
CS
SCK
V
SS
SI
1
2
3
4
5
6
7
Wiper
X9111
R
H
100kΩ
1024-taps
POT
V
SS
1
XDCP is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
NC
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
R
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
R
W
L
X9111
www.BDTIC.com/Intersil
Ordering Information
POTENTIOMETER
PART NUMBERPART MARKING VCC LIMITS (V)
X9111TV14IX9111TV I5 ±10%100-40 to +8514 Ld TSSOP (4.4mm)
X9111TV14IZ (Note)X9111TV ZI-40 to +8514 Ld TSSOP (4.4mm) (Pb-free)
X9111TV14X9111TV0 to +7014 Ld TSSOP (4.4mm)
X9111TV14Z (Note)X9111TV Z0 to +7014 Ld TSSOP (4.4mm) (Pb-free)
X9111TV14-2.7X9111TV F2.7 to 5.50 to +7014 Ld TSSOP (4.4mm)
X9111TV14Z-2.7 (Note)X9111TV ZF0 to +7014 Ld TSSOP (4.4mm) (Pb-free)
X9111TV14I-2.7*X9111TV G-40 to +8514 Ld TSSOP (4.4mm)
X9111TV14IZ-2.7* (Note) X9111TV ZG-40 to +8514 Ld TSSOP (4.4mm) (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ORGANIZATION (kΩ) TEMP RANGE (°C)PACKAGE
Detailed Functional Diagram
V
CC
HOLD
CS
SCK
SO
SI
A0
A1
WP
Interface
and
Control
Circuitry
V
SS
Data
Control
Circuit Level Applications
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
Power On
Recall
DR0 DR1
DR2 DR3
Wiper
Counter
Register
(WCR)
100kΩ
1024-taps
R
H
R
L
R
W
System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control systems
• Control the operating point for senso rs in in d ust ri al
systems
• Trim offset and gain errors in artificial intelligent systems
2
FN8159.4
September 15, 2006
X9111
www.BDTIC.com/Intersil
Pin Descriptions
PIN
(TSSOP) SYMBOLFUNCTION
1SOSerial Data Output
2A0Device Address
3NCNo Connect
4CS
5SCKSerial Clock
6SISerial Data Input
7V
8WPHardware Write Protect
9A1Device Address
10HOLD
11R
12R
13R
14V
SS
CC
Chip Select
System Ground
Device Select. Pause the Serial Bus
Wiper Terminal of the Potentiometer
W
High Terminal of the Potentiometer
H
Low Terminal of the Potentiometer
L
System Supply Voltage
Pin Descriptions
Bus Interface Pins
SERIAL OUTPUT (SO)
SO is a serial data output pin. During a read cycle, data is
shifted out on this pin. Data is clocked out by the falling edge
of the serial clock.
SERIAL INPUT (SI)
SI is the serial data input pin. All opcodes, byte addresses and
data to be written to the pots and pot registers are input on this
pin. Data is latched by the rising edge of the serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the
X9111.
HOLD (HOLD
is used in conjunction with the CS pin to select the
HOLD
device. Once the part is selected and a serial sequence is
underway , HOLD
communication with the controller without resetting the serial
sequence. To pause, HOLD
LOW. To resume communication, HOLD
while SCK is LOW. If the p ause feature is not used, HOLD
be held HIGH at all times.
DEVICE ADDRESS (A
The address inputs are used to set the 8-bit slave address. A
match in the slave address serial data stream must be made
with the address input (A1–A0) in order to initiate
communication with the X9111.
)
may be used to pause the serial
must be brought LOW while SCK is
is brought HIGH, again
, A1)
0
should
CHIP SELECT (CS
When CS
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state. CS
enables the X9111, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS
HARDWARE WRITE PROTECT INPUT (WP
The WP
Data Registers.
is HIGH, the X9111 is deselected and the SO pin is at
pin when LOW prevents nonvolatile writes to the
)
LOW
is required prior to the start of any operation.
)
Potentiometer Pins
RH, RL
and RL pins are equivalent to the terminal connections
The R
H
on a mechanical potentiometer.
R
W
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (V
The V
CC
the system ground.
)
SS
pin is the system supply voltage. The VSS pin is
Other Pins
NO CONNECT (NC)
Pin should be left open. This pin is used for Intersil
manufacturing and test purposes.
Principles of Operation
Device Description
Serial Interface
The X9111 supports the SPI interface hardware conventions.
The device is accessed via the SI input with data clocked-in on
the rising SCK. CS
must be HIGH during the entire operation.
The SO and SI pins can be connected together, since they
have three state outputs. This can help to reduce system pin
count.
Array Description
The X9111 is comprised of a resistor array (see Figure 1).
The array contains the equivalent of 1023 discrete resistive
segments that are connected in series. The physical ends of
each array are equivalent to the fixed te rmi nals of a
mechanical potentiometer (R
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (R
output. Within the individual array only one switch may be
turned on at a time.
must be LOW and the HOLD and WP pins
and RL inputs).
H
)
W
3
FN8159.4
September 15, 2006
X9111
www.BDTIC.com/Intersil
Serial Data Path
From Interface
Circuitry
If WCR = 000[HEX] then RW = R
If WCR = 3FF[HEX] then RW = R
Register 0
(DR0)
1010
Register 2
(DR2)
L
H
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
Register 1
(DR1)
Register 3
(DR3)
These switches are controlled by a Wiper Counter Register
(WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to
select, and enable, one of 1024 switches.
Wiper Counter Register (WCR)
The X9111 contains a Wiper Counter Register (see Table 1)
for the XDCP potentiometer. The WCR is equivalent to a
serial-in, parallel-out register/counter with its outputs
decoded to select one of 1024 switches along its resistor
array. The contents of the WCR can be altered in one of
three ways: (1) it may be written directly by the host via the
write Wiper Counter Register instruction (serial load); (2) it
may be written indirectly by transferring the contents of one
of four associated Data Registers via the XFR Data Register;
(3) it is loaded with the contents of its Data Register zero
(DR0) upon power-up.
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9111 is powered-down.
Although the register is automatically loaded with the value
in R0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loadings of the R0 value into
the WCR.
Data Registers (DR3 to DR0)
The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the Wiper Counter Register. All operations
changing data in one of the Data Registers is a nonvolatile
operation and will take a maximum of 10ms.
Serial
Bus
Input
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
C
O
U
N
T
E
R
D
E
C
O
D
E
R
H
R
L
R
W
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
A DR[9:0] is used to store one of the 1024 wiper position (0
~1023). Table 2
Status Register (SR)
This 1-bit status register is used to store the system status
(see Table 3).
WIP: Write In Progress status bit, read only.
• When WIP=1, indicates that high-voltage write cycle is in
progress.
• When WIP=0, indicates that no high-voltage write cycle is
in progress.
Device Instructions
Identification Byte (ID and A)
The first byte sent to the X9111 from the host, following a CS
going HIGH to LOW, is called the Identification Byte. The
most significant four bits of the slave address are a device
type identifier. The ID[3:0] bits is the device ID for the X9111;
this is fixed as 0101[B] (refer to Table 4).
The A1–A0 bits in the ID byte are the internal slave address.
The physical device address is defined by the state of the
A1–A0 input pins. The slave address is externally specified
by the user. The X9111 compares the serial data stream with
the address input state; a successful compare of the address
4
FN8159.4
September 15, 2006
X9111
www.BDTIC.com/Intersil
bits is required for the X9111 to successfully continue the
command sequence. Only the device whose slave address
matches the incoming device address sent by the master
executes the instruction. The A1–A0 inputs can be actively
driven by CMOS input signals or tied to V
R/W
bit is used to set the device to either read or write
or VSS. The
CC
Instruction Byte and Register Selection
The next byte sent to the X9111 contains the instruction and
register pointer information. The three most significant bits
are used provide the instruction opcode (I[2:0]). The RB and
RA bits point to one of the four registers. The format is
shown in Table 5.
mode.
TABLE 1. WIPER LATCH, WL (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V)
WCR9WCR8WCR7WCR6WCR5WCR4WCR3WCR2WCR1WCR0
VVVVVVVVVV
(MSB)(LSB)
TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE, NV)
Five of the seven instructions are four bytes in length. These
instructions are:
• Read Wiper Counter Register – read the current wiper
position of the selected pot,
• Write Wiper Counter Register – change current wiper
position of the selected pot,
• Read Data Register – read the contents of the selected
data register;
• Write Data Register – write a new value to the selected
data register.
• Read Status – This command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress.
The basic sequence of the four byte instructions is illustrated
in Figure 3. These four-byte instructions exchange data
between the WCR and one of the Data Registers. A transfer
from a Data Register to a WCR is essentially a write to a
static RAM, with the static RAM controlling the wiper
position. The response of the wiper to this action will be
delayed by tWRL. A transfer from the WCR (current wiper
position), to a Data Register is a write to nonvolatile memory
and takes a minimum of tWR to complete. The transfer can
occur between the potentiometer and one of its associated
registers. The Read Status Register instruction is the only
unique format (see Figure 4).
Two instructions require a two-byte sequence to complete
(see Figure 2). These instructions transfer data between the
host and the X9111; either between the host and one of th e
Data Registers or directly between the host and the Wiper
Counter Register. These instructions are:
• XFR Data Register to Wiper Counter Register –This
transfers the contents of one specified Data Register to
the associated Wiper Counter Register.
• XFR Wiper Counter Register to Data Register – This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
See Instruction format for more details.
Write in Process (WIP bit)
The contents of the Data Registers are saved to nonvolatile
memory when the CS
pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
progress of this internal write operation can be monitored by
a Write In Process bit (WIP). The WIP bit is read with a Read
Status command (see Figure 4).
Power Up and Down Requirements
There are no restrictions on the power-up condition of VCC
and the voltages applied to the potentiometer pins provided
that the V
voltages at R
are no restrictions on the power-down condition. However,
the datasheet parameters for the DCP do not apply until
1millisecond after V
is always more positive than or equal to the
CC
, RL, and RW, i.e., VCC ≥ RH, RL, RW. There
H
reaches its final value.
CC
CS
SCK
SI
ID3 ID2 ID1 ID0 0
CS
SCK
SI
0101 0
Device ID
FIGURE 3. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)
0101
ID3 ID2 ID1 ID00A1 A0
Device IDInternal Instruction
FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE
0
A1
A0
I2
R/W
I1I00 RB RA
Internal
Address
Instruction
Opcode
0
0
X
Register
Address
X0
00
0
R/W
XX
I2
I1I0RB RA
OpcodeAddress
XXX
0
Register
Address
X
W
W
W
W
C
R
7
W
C
C
R
R
6
5
Wiper
Position
C
C
R
R
9
8
0
0
0
0
W
W
W
W
C
C
R
R
4
3
W
C
C
C
R
R
R
2
1
0
6
FN8159.4
September 15, 2006
X9111
www.BDTIC.com/Intersil
CS
SCK
SI
01010
ID3 ID2 ID1ID0 0A0R/W
Device ID
Internal
Address
A1
1
I2
I1
Instruction
Opcode
I0
0
X
RB RA
0
Register
Address
X0
00
0
XX
XXX
X
X
X
0
00
0
0
0
0
WIP
Status
Bit
FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)
TABLE 5. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
Read Wiper Counter
Register
Write Wiper Counter
Register
I
I
I
3
2
0RBRA0 0
1
110000000Read the contents of the Wiper Counter
Register
010100000Write new value to the Wiper Counter
Register
OPERATIONR/W
Read Data Register110101/01/000Read the contents of the Data Register
pointed to RB-RA
Write Data Register011001/01/000Write new value to the Data Register
pointed to RB-RA
XFR Data Register to
Wiper Counter Register
111001/01/000Transfer the contents of the Data Register
pointed to by RB-RA to the Wiper Counter
Register
XFR Wiper Counter
Register to Data Register
011101/01/000Transfer the contents of the Wiper Coun ter
Register to the Data Register pointed to by
RB-RA
Read Status (WIP bit)101000001Read the status of the internal write cycle,
by checking the WIP bit (read status
register).
NOTE: 1/0 = data is one or zero
Instruction Format
Read Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
01010A1A0
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by X9111 on SO)
10000000XXXXXX
R/ W = 1
Write Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
01010A1A0
Device
Addresses
7
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by Master on SI)
10100000XXXXXX
R/ W = 0
Wiper Position
(sent by X9111 on SO)
W
W
W
W
W
W
W
W
C
C
C
C
C
R
R
R
9
8
7
(Sent by Master on SI)
W
W
W
C
C
C
R
R
R
9
8
7
C
R
R
R
6
5
4
Wiper Position
W
W
W
C
C
C
R
R
R
6
5
4
W
C
C
C
R
R
R
3
2
1
W
W
W
C
C
C
R
R
R
3
2
1
CS
W
Rising
C
Edge
R
0
CS
W
Rising
C
Edge
R
0
FN8159.4
September 15, 2006
X9111
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Read Data Register (DR)
Device
Type
Identifier
CS
Falling
Edge
01010A1A0
Write Data Register (DR)
Device Type
Identifier
CS
Falling
Edge
01010A1A0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
CS
Falling
Edge
Identifier
01010A1A0
Device
Addresses
Device
Addresses
Addresses
Instruction
Opcode
1010RBRA00XXXXXX
R/ W = 1
Instruction
Opcode
1100
R/ W = 0
Device
Instruction
1100RBRA00
R/ W = 1
Addresses
RBR
Opcode
Register
Addresses
Register
0 0XXXXXX
A
(Sent by X9111 on SO)
Wiper Position or Data
(Sent by Master on SI)
Register
Addresses
Wiper Position
W
C
R
CS
Rising
Edge
Wiper Position
(sent by X9111 on SO)
W
W
W
W
W
W
W
W
C
C
C
C
C
R
R
R
9
8
7
Wiper Position or Data
(Sent by Master on SI)
W
W
W
C
R
9
8
W
C
C
C
R
R
R
7
6
5
C
R
R
R
6
5
4
W
W
W
C
C
C
R
R
R
4
3
2
W
C
C
C
R
R
R
3
2
1
Rising
W
W
Edge
C
C
R
R
1
0
CS
CS
Rising
W
Edge
C
R
0
WRITE CYCLE
HIGH-VOLTAGE
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
01010A1A0
Device
Addresses
Instruction
Opcode
1110 RB RA 0 0
R/ W = 0
Register Addresses
Read Status Register (SR)
Device Type
Identifier
CS
Falling
Edge
01010A1A0
NOTES:
1. “A0 and A1”: stand for the device address sent by the master.
2. WCRx refers to wiper position data in the Wiper Counter Register
3. “X”: Don’t Care.
Device
Addresses
Instruction
Opcode
01000001XXXXXXXX00 00000
R/ W = 1
Register
Addresses
(Sent by Slave on SO)
CS
Rising
Edge
Status Data
HIGH-VOLTAGE
WRITE CYCLE
(Sent by Slave on SO)
Status Data
WI
P
CS
Rising
Edge
8
FN8159.4
September 15, 2006
X9111
www.BDTIC.com/Intersil
Absolute Maximum Ratings Recommended Operating Conditions
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Characteristics Over recommended industrial operation conditions unless otherwise st at ed.
SYMBOLPARAMETERTEST CONDITIONSMINTYPMAXUNITS
R
TOTAL
I
W
R
W
V
TERM
C
H/CL/CW
End to End Resistance100kΩ
End to End Resistance Tolerance±20%
Power Rating+25°C, each pot50mW
Wiper Current±3mA
Wiper ResistanceWiper Current = ±50µA,
= 5V
V
CC
Wiper Current = ±50µA,
= 3V
V
CC
Voltage on any RH or RL PinV
NoiseRef: 1V-120dBV
Resolution1.6%
Absolute Linearity (Note 1)R
Relative Linearity (Note 2)R
Temperature Coefficient of R
Ratiometric Temp. Coefficient20ppm/°C
Potentiometer CapacitanciesSee Macro model10/10/25pF
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
3. MI = RTOT/1023 or (R
4. n = 0, 1, 2, …,1023; m =0, 1, 2, …, 1022.
5. ESD Rating on RH, RL, RW pins is 1.5kV (HBM, 1.0µA leakage maximum), ESD rating on all other pins is 2.0kV.
– RL)/1023, single pot
H
9
FN8159.4
September 15, 2006
X9111
www.BDTIC.com/Intersil
D.C. Operating Characteristics Over the recommended operating conditions unless otherwise specified.
SYMBOLPARAMETERTEST CONDITIONSMIN.TYP.MAX.UNITS
I
CC1
I
CC2
I
I
I
V
V
V
V
V
SB
LO
VCC supply current
(active)
VCC supply current
(nonvolatile write)
VCC current (standby)SCK = SI = VSS, Addr. = VSS,
Input leakage currentVIN = VSS to V
LI
Output leakage currentV
Input HIGH voltageVCC x 0.7VCC + 1V
(Note 7)Power-up to initiation of read operation1ms
t
PUR
(Note 7)Power-up to initiation of write operation50ms
t
PUW
NOTES:
6. This parameter is not 100% tested.
and t
7. t
PUR
parameters are not 100% tested.
are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These
PUW
A.C. Test Conditions
nput pulse levelsVCC x 0.1 to VCC x 0.9
I
Input rise and fall times10ns
Input and output timing levelV
CC
x 0.5
10
FN8159.4
September 15, 2006
Equivalent A.C. Load Circuit
www.BDTIC.com/Intersil
X9111
1217Ω
3V
1382Ω
100pF
SPICE Macromodel
R
H
C
10pF
L
R
TOTAL
R
W
C
W
25pF
C
L
10pF
SO pin
2714Ω
5V
1462Ω
SO pin
100pF
AC Timing
SYMBOLPARAMETERMINMAXUNITS
f
SCK
t
CYC
t
WH
t
WL
t
LEAD
t
LAG
t
SU
t
H
t
RI
t
FI
t
DIS
t
V
t
HO
t
RO
t
FO
t
HOLD
t
HSU
t
HH
t
HZ
t
LZ
T
t
CS
t
WPASU
t
WPAH
I
SSI/SPI clock frequency2.0MHz
SSI/SPI clock cycle time400ns
SSI/SPI clock high time150ns
SSI/SPI clock low time150ns
Lead time150ns
Lag time150ns
SI, SCK, HOLD and CS input setup time50ns
SI, SCK, HOLD and CS input hold time50ns
SI, SCK, HOLD and CS input rise time50ns
SI, SCK, HOLD and CS input fall time50ns
SO output disable time0500ns
SO output valid time100ns
SO output hold time0ns
SO output rise time50ns
SO output fall time50ns
HOLD time400ns
HOLD setup time50ns
HOLD hold time50ns
HOLD low to output in high Z100ns
HOLD high to output in low Z100ns
Noise suppression time constant at
SI, SCK, HOLD
CS deselect time100ns
WP, A0, A1 setup time0ns
WP, A0, A1 hold time0ns
and CS inputs
20ns
R
L
11
FN8159.4
September 15, 2006
X9111
www.BDTIC.com/Intersil
High-voltage Write Cycle Timing
SYMBOLPARAMETERTYPMAXUNITS
t
WR
High-voltage write cycle time (store instructions)510ms
XDCP Timing
SYMBOLPARAMETERMINMAXUNITS
t
WRPO
t
WRL
Wiper response time after the third (last) power supply is stable510µs
Wiper response time after instruction issued (all load instructions)510µs
Symbol Table
WAVEFORMINPUTSOUTPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/ACenter Line
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
is High
Impedance
12
FN8159.4
September 15, 2006
Timing Diagrams
www.BDTIC.com/Intersil
Input Timing
CS
t
LEAD
X9111
t
CYC
t
CS
t
LAG
SCK
SI
SO
Output Timing
CS
SCK
SO
ADDR
SI
t
SU
MSBLSB
High Impedance
t
H
t
V
MSBLSB
t
WL
t
HO
t
...
WH
...
...
...
t
FI
t
RI
t
DIS
Hold Timing
CS
SCK
SO
SI
HOLD
t
HSU
t
RO
t
FO
t
HOLD
t
HZ
13
t
HH
...
t
LZ
FN8159.4
September 15, 2006
XDCP Timing (for All Load Instructions)
www.BDTIC.com/Intersil
CS
X9111
SCK
MSBLSB
R
SO
SI
W
High Impedance
Write Protect and Device Address Pins Timing
CS
t
WP
A0
A1
WPASU
Applications information
Basic Configurations of Electronic Potentiometers
...
...
(Any Instruction)
t
WPAH
t
WRL
V
R
Three terminal Potentiometer;
Variable voltage divider
RW
+V
R
I
Two terminal Variable Resistor;
Variable current
14
FN8159.4
September 15, 2006
Application Circuits
www.BDTIC.com/Intersil
Noninverting AmplifierVoltage Regulator
X9111
V
S
VO = (1+R2/R1)V
+
–
R
R
1
S
V
O
2
IN
VO (REG) = 1.25V (1+R2/R1)+I
317
R
I
adj
R
2
Offset Voltage AdjustmentComparator with Hysterisis
–
+
R
2
TL072
V
S
V
O
}
R
VUL = {R1/(R1+R2)} VO(max)
= {R1/(R1+R2)} VO(min)
RL
L
–
+
}
R
2
1
V
S
10kΩ
R
1
100kΩ
-12V+12V
10kΩ10kΩ
1
adj R2
V
VO (REG)V
O
15
FN8159.4
September 15, 2006
Application Circuits (Continued)
www.BDTIC.com/Intersil
AttenuatorFilter
R
1
V
S
R
3
R
VO = G V
-1/2 ≤ G ≤ +1/2
–
+
4
R1 = R2 = R3 = R4 = 10kΩ
S
Inverting AmplifierEquivalent L-R Circuit
R
R
V
S
2
1
}
}
X9111
C
V
R
2
V
O
–
+
V
O
S
R
G
O
fc = 1/(2πRC)
C
1
V
S
+
–
R
1
= 1 + R2/R
R
V
O
R
2
1
2
+
–
VO = G V
G = - R2/R
S
1
Function Generator
–
+
frequency ∝ R1, R2, C
amplitude ∝ R
, R
A
B
R
Z
IN
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R
R
2
R
}
A
R
}
B
R
1
–
+
1
R
3
+ R3) >> R
1
C
2
16
FN8159.4
September 15, 2006
X9111
www.BDTIC.com/Intersil
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
INDEX
AREA
123
0.05(0.002)
-AD
e
b
0.10(0.004)C AMBS
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
E1
-B-
SEATING PLANE
A
-C-
M
0.25(0.010)BMM
E
α
A1
0.10(0.004)
GAUGE
PLANE
0.25
0.010
A2
L
c
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INCHESMILLIMETERS
SYMBOL
A-0.047-1.20-
A10.0020.0060.050.15-
A20.0310.0410.801.05-
b0.00750.01180.190.309
c0.00350.00790.090.20-
D0.1950.1994.955.053
E10.1690.1774.304.504
e0.026 BSC0.65 BSC-
E0.2460.2566.256.50-
L0.01770.02950.450.756
N14147
o
α
0
o
8
o
0
o
8
NOTESMINMAXMINMAX
-
Rev. 2 4/06
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or i t s sub sidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
FN8159.4
September 15, 2006
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