intersil X9110 DATA SHEET

®

www.BDTIC.com/Intersil

X9110

Dual Supply/Low Power/1024-Tap/SPI Bus

Data Sheet February 13, 2008

Single Digitally-Controlled (XDCP™)
Potentiometer

The X9110 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.

The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.

The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.

FN8158.3

Features

• 1024 Resistor Taps – 10-Bit Resolution

• SPI Serial Interface for write, read, and transfer operations
of the potentiometer

• Wiper Resistance, 40Ω Typical @ 5V

• Four Non-Volatile Data Registers

• Non-Volatile Storage of Multiple Wiper Positions

• Power-on Recall. Loads Saved Wiper Position on Power-up

• Standby Current < 3µA Max

• System V

• Analog V+/V-: -5V to +5V

•100kΩ End to End Resistance

• 100 yr. Data Retention

• Endurance: 100, 000 Data Changes Per Bit Per Register

• 14 Ld TSSOP

• Dual Supply Version of the X9111

• Low Power CMOS

: 2.7V to 5.5V Operation

CC

Functional Diagram

SPI

BUS

INTERFACE

ADDRESS

DATA

STATUS

V

CC

BUS

INTERFACE &

CONTROL

WRITE

READ

TRANSFER

CONTROL

• Pb-Free Available (RoHS Compliant)

Pinout

X9110

14 LD TSSOP

TOP VIEW

V+

1

S0

2

A0

3

POWER-ON RECALL

WIPER COUNTER

REGISTER (WCR)

DATA REGISTERS

(DR0-DR3)

SCK

V

WP

SS

SI

4

5

6

7

WIPER

R

H

POT

14

13

12

11

10

9
8

V+

100kΩ
1024-TAPS

V

CC

R

L

R

H

R

W

HOLD

CS

V-

V

SS

1

NC NC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas INC. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

R

W

R

L

V-

Ordering Information

www.BDTIC.com/Intersil

X9110

PART NUMBER PART MARKING

VCC LIMITS

(V)

POTENTIOMETE

R RANGE (kΩ)

TEMP

RANGE (°C) PACKAGE

PKG.

DWG. #

X9110TV14 X9110TV 5 ±10 100 0 to +70 14 Ld TSSOP M14.173
X9110TV14Z* (Note) X9110TV Z 0 to +70 14 Ld TSSOP (Pb-free) M14.173
X9110TV14I X9110TV I -40 to +85 14 Ld TSSOP M14.173
X9110TV14IZ (Note) X9110TV Z I -40 to +85 14 Ld TSSOP (Pb-free) M14.173
X9110TV14-2.7 X9110TV F 2.7 to 5.5 0 to +70 14 Ld TSSOP M14.173
X9110TV14Z-2.7 (Note) X9110TV Z F 0 to +70 14 Ld TSSOP (Pb-free) M14.173
X9110TV14I-2.7 X9110TV G -40 to +85 14 Ld TSSOP M14.173
X9110TV14IZ-2.7* (Note) X9110TV Z G -40 to +85 14 Ld TSSOP (Pb-free) M14.173
*Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.

Detailed Functional Diagram

V

CC

V+

HOLD

CS

SCK

SO

A0

WP

POWER ON

RECALL

DR0 DR1

INTERFACE

AND

SI

CONTROL

CIRCUITRY

V

SS

DATA

CONTROL

DR2 DR3

WIPER
COUNTER
REGISTER

(WCR)

100kΩ
1024-TAPS

V-

R

H

R

L

R

W

2

FN8158.3

February 13, 2008

X9110

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Circuit Level Applications

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier
circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and Q-factor in
filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF circuits

• Provide a control variable (I, V, or R) in feedback circuits

System Level Applications

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems

• Control the gain in audio and home entertainment systems

• Provide the variable DC bias for tuners in RF wireless
systems

• Set the operating points in temperature control systems

• Control the operating point for sensors in industrial
systems

• Trim offset and gain errors in artificial intelligent systems

Pin Descriptions

PIN

(TSSOP) SYMBOL FUNCTION

1 V+ Analog Supply Voltage
2 SO Serial Data Output
3 A0 Device Address
4 SCK Serial Clock
5WP
6 SI Serial Data Input
7V
8V
9CS

10 HOLD

SS

Hardware Write Protect

System Ground

- Analog Supply Voltage

Chip Select
Device Select. Pause the Serial Bus

Pin Descriptions (Continued)

PIN

(TSSOP) SYMBOL FUNCTION

11 R
12 R
13 R
14 V

W

CC

Bus Interface Pins

SERIAL OUTPUT (SO)

SO is a serial data output pin. During a read cycle, data is
shifted out on this pin. Data is clocked out on the falling edge
of the serial clock.

SERIAL INPUT (SI)

SI is the serial data input pin. All opcodes, byte addresses
and data to be written to the pots and pot registers are input
on this pin. Data is latched by the rising edge of the serial
clock.

SERIAL CLOCK (SCK)

The SCK input is used to clock data into and out of the
X9110.

HOLD (HOLD

is used in conjunction with the CS pin to select the

HOLD
device. Once the part is selected and a serial sequence is
underway , HOLD
communication with the controller without resetting the serial
sequence. To p ause, HOLD
LOW. To resume communication, HOLD
while SCK is LOW. If the p ause feature is not used, HOLD
be held HIGH at all times.

DEVICE ADDRESS (A0)

The address input is used to set the 8-bit slave address. A
match in the slave address serial data stream A0 must be
made with the address input (A0) in order to initiate
communication with the X9110.

CHIP SELECT (CS

When CS
is at high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state. CS
enables the X9110, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS
operation.

HARDWARE WRITE PROTECT INPUT (WP

The WP
Data Registers.

)

may be used to pause the serial

is HIGH, the X9110 is deselected and the SO pin

is required prior to the start of any

pin when LOW prevents nonvolatile writes to the

Wiper Terminal of the Potentiometer
High Terminal of the Potentiometer

H

Low Terminal of the Potentiometer

L

System Supply Voltage

must be brought LOW while SCK is

is brought HIGH, again

)

should

LOW

)

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FN8158.3

February 13, 2008

X9110

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SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

If WCR = 000[HEX] then RW = R
If WCR = 3FF[HEX] then RW = R

REGISTER 0

(DR0)

10 10

REGISTER 2

(DR2)

L

H

FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM

REGISTER 1

(DR1)

REGISTER 3

(DR3)

Potentiometer Pins

RH, RL

The R

and RL pins are equivalent to the terminal

H

connections on a mechanical potentiometer.

R

W

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.

Bias Supply Pins

SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (V

The V

CC

)

SS

pin is the system supply voltage. The VSS pin is

the system ground.

ANALOG SUPPLY VOLTAGES (V+ AND V

-)

These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper switches
while the V- supply is used to bias the switches and the
internal P+ substrate of the integrated circuit. Both of these
supplies set the voltage limits of the potentiometer.

Principles Of Operation

Device Description

SERIAL INTERFACE

The X91 10 supports the SPI interface hardware conventions.
The device is accessed via the SI input with data clocked-in

SERIAL
BUS
INPUT

PARALLEL
BUS
INPUT

WIPER
COUNTER
REGISTER

(WCR)

on the rising SCK. CS

C
O
U
N
T
E
R

D
E
C
O
D
E

must be LOW and the HOLD and WP

R

H

R

L

R

W

pins must be HIGH during the entire operation.
The SO and SI pins can be connected together, since they

have three state outputs. This can help to reduce system pin
count.

ARRAY DESCRIPTION

The X9110 is comprised of a resistor array (Figure 1). The
array contains the equivalent of 1023 discrete resistive
segments that are connected in series. The physical ends of
each array are equivalent to the fixed te rmi nals of a
mechanical potentiometer (R

and RL inputs).

H

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (R

)

W

output. Within the individual array only one switch may be
turned on at a time.

These switches are controlled by a Wiper Counter Register
(WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to
select, and enable, one of 1024 switches.

WIPER COUNTER REGISTER (WCR)

The X9110 contains a Wiper Counter Register (see Table 1)
for the XDCP potentiometer. The WCR is equivalent to a
serial-in, parallel-out register/counter with its outputs
decoded to select one of 1024 switches along its resistor
array. The contents of the WCR can be altered in one of
three ways: (1) it may be written directly by the host via the
write Wiper Counter Register instruction (serial load); (2) it

4

FN8158.3

February 13, 2008

X9110

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may be written indirectly by transferring the contents of one
of four associated Data Registers via the XFR Data Register;
(3) it is loaded with the contents of its data register zero
(DR0) upon power-up.

The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X91 10 is powered-down. Although
the register is automatically loaded with the value in DR0 upon
power-up, this may be different from the value present at
power-down. Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR.

DATA REGISTERS (DR)

The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the Wiper Counter Register. All operations
changing data in one of the Data Registers is a nonvolatile
operation and will take a maximum of 10ms.

TABLE 1. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: Used To Store The Current Wiper Position (Volatile, V)

WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0

VVVVVVVVVV

(MSB) (LSB)

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.

DR[9:0] is used to store one of the 1024 wiper position
(0~1023) (see Table 2).

STATUS REGISTER (SR)

This 1-bit status register is used to store the system status
(see Table 3).

WIP: Write In Progress status bit, read only.

• When WIP = 1, indicates that high-voltage write cycle is in
progress.

• When WIP=0, indicates that no high-voltage write cycle is
in progress.

TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: Used to store wiper positions or data (Non-Volatile, NV)

BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

NV NV NV NV NV NV NV NV NV NV

MSB LSB

TABLE 3. STATUS REGISTER, SR (1-BIT)

WIP

(LSB)

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February 13, 2008

X9110

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TABLE 4. IDENTIFICATION BYTE FORMAT

DEVICE TYPE

IDENTIFIER

ID3 ID2 ID1 ID0 0 0 A0 R/W

0101

(MSB) (LSB)

TABLE 5. INSTRUCTION BYTE FORMAT

0
0
1
1

REGISTER

SELECTION

0
1
0
1

DR0
DR1
DR2
DR3

INSTRUCTION

OPCODE

I2 I1 I0 0 RB RA 0 0

(MSB) (LSB)

RB RA REGISTER

INTERNAL SLAVE

ADDRESS

READ OR
WRITE BIT

Device Instructions

Identification Byte (ID and A)

The first byte sent to the X9110 from the host, following a CS
going HIGH to LOW, is called the Identification Byte. The
most significant four bits of the slave address are a device
type identifier. The ID[3:0] bits is the device ID for the X9110;
this is fixed as 0101[B] (refer to Table 4).

The A0 bit in the ID byte is the internal slave address. The
physical device address is defined by the state of the A0 input
pin. The slave address is externally specified by the user. The
X911 0 compares the serial dat a stream with the address input
state; a successful compare of the address bit is required for
the X911 0 to successfully continu e the co mmand seq uence.
Only the device whose slave address matches the incoming
device address sent by the master executes the instruction.
The A0 input can be actively driven by CMOS input signals or
tied to V
either read or write mode.

Instruction Byte and Register Selection

The next byte sent to the X9110 contains the instruction and
register pointer information. The three most significant bits
are used provide the instruction opcode (I[2:0]). The RB and
RA bits point to one of the four registers. The format is
shown in Table 5.

Five of the seven instructions are four bytes in length. These
instructions are:

• Read Wiper Counter Register – read the current wiper
position of the selected pot

or VSS. The R/W bit is used to set the device to

CC

• Write Dat a Register – write a new value to the sel ected
data register

• Read Status – This command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress

The basic sequence of the four byte instructions is illustrated
in Figure 3. These four-byte instructions exchange data
between the WCR and one of the Data Registers. A transfer
from a Data Register to a WCR is essentially a write to a
static RAM, with the static RAM controlling the wiper
position. The response of the wiper to this action will be
delayed by t

. A transfer from the WCR (current wiper

WRL

position), to a Data Register is a write to nonvolatile memory
and takes a minimum of t

to complete. The transfer can

WR

occur between the potentiometer and one of its associated
registers. The Read Status Register instruction is the only
unique format (see Figure 4).

Two instructions require a two-byte sequence to complete
(See Figure 2). These instructions transfer data between the
host and the X9110; either between the host and one of the
Data Registers or directly between the host and the Wiper
Counter Register. These instructions are:

• XFR Data Register to Wiper Counter Register – This
transfers the contents of one specified Data Register to
the associated Wiper Counter Register

• XFR Wiper Counter Register to Data Register – This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register

See Instruction format for more details.

• Write Wiper Counter Register – change current wiper
position of the selected pot

• Read Data Register – read the contents of the selected
data register

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FN8158.3

February 13, 2008

X9110

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Write in Process (WIP bit)

The contents of the Data Registers are saved to nonvolatile
memory when the CS
complete write sequence is received by the device. The
progress of this internal write operation can be monitored by
a Write In Process bit (WIP). The WIP bit is read with a Read
Status command (See Figure 4).

CS

pin goes from LOW to HIGH after a

CS

SCK

SI

0101

ID3 ID2 ID1 ID0 0 0 A0

DEVICE ID INTERNAL INSTRUCTION

FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE

0

0

Power-up and Down Requirements

At all times, the V+ voltage must be greater than or equal to
the voltage at R
greater than or equal to the voltage at V-. During power-up
and power-down, V
values within 1msec of each other.

I2

R/W

I1 I0 RB RA

OPCODEADDRESS

or RL, and the voltage at RH or RL must be

H

, V+, and V- must reach their final

CC

0

REGISTER
ADDRESS

0

0

0

0

SCK

CS

SCK

SI

SI

0101 0

ID3 ID2 ID1 ID0 0

DEVICE ID

INTERNAL
ADDRESS

0

A0

0

I2

R/W

I1I00 RB RA

INSTRUCTION

OPCODE

0

X

REGISTER
ADDRESS

X0

00

0

XX

XX X

X

W

W

W

W

W

W

W

W

W

C

C

C

C

C

C

R

R

R

9

R

8

7

6

C

R

R

R

5

4

3

WIPER

POSITION

W

C

C

C

R

R

R

2

1

0

FIGURE 3. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)

0

01010

ID3 ID2ID1ID0 0 A0 R/W

DEVICE ID

INTERNAL

ADDRESS

1

0

I2

I1

I0

INSTRUCTION

OPCODE

0

X

RB RA

0

REGISTER

ADDRESS

X0

00

0

XX

XXX

X

X

X

0

00

0

0

0

0

WIP

STATUS

BIT

FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)

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FN8158.3

February 13, 2008

X9110

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TABLE 6. INSTRUCTION SET

INSTRUCTION SET

I

I

I

INSTRUCTION

Read Wiper Counter
Register

Write Wiper Counter
Register

Read Data Register 1 1 0 1 0 1/0 1/0 0 0 Read the contents of the Data Register

Write Data Register 0 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register

XFR Data Register to
Wiper Counter Register

XFR Wiper Counter
Register to Data Register

Read Status (WIP bit) 1 0 1 0 0 0 0 0 1 Read the status of the internal write cycle,

NOTE: 1/0 = data is one or zero

2

1

1 1 0 0 0 0 0 0 0 Read the contents of the Wiper Counter

0 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter

1 1 1 0 0 1/0 1/0 0 0 Transfer the contents of the Data Register

0 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Cou n ter

0RBRA0 0

0

OPERATIONR/W

Register

Register

pointed to RB-RA

pointed to RB-RA

pointed to by RB-RA to the Wiper Counter
Register

Register to the Data Register pointed to by
RB-RA

by checking the WIP bit (read status
register).

Instruction Format
Read Wiper Counter Register (WCR)

CS

Falling

Edge

Device Type

Identifier

010100A0

Device

Addresses

Instruction

Opcode

10000000XXXXXX

R/ W = 1

Write Wiper Counter Register (WCR)

CS

Falling

Edge

Device Type

Identifier

010100A0

Device

Addresses

Instruction

Opcode

10100000XXXXXX

R/ W = 0

Read Data Register (DR)

CS

Falling

Edge

Device Type

Identifier

010100A0

Device

Addresses

Instruction

Opcode

1010RBRA00XXXXXX

R/ W = 1

Register

Addresses

Register

Addresses

Register

Addresses

Wiper Position

(Sent by X9110 on SO)

W

C
R
9

Wiper Position

(Sent by Master on SI)

W

C
R
9

Wiper Position

(Sent by X9110 on SO)

Wiper Position

(sent by X9110 on SO)

W

W

W
C
R

8

W

C
R
8

W

C
R
9

W

C

C

C

R

R

R

7

6

5

Wiper Position

(Sent by Master on SI)

W

W

W

C

C

C

R

R

R

7

6

5

Wiper Position

(sent by X9110 on SO)

W

W

W

C

C

C

R

R

R

8

7

6

W

W

W
C
R

4

W

C
R
4

W
C
R

5

W

C

C

C

R

R

R

3

2

1

W

W

W

C

C

R

R

3

2

W

W

W

C

C

C

R

R

R

4

3

2

CS

W

Rising

C

Edge

R

0

CS

W

Rising

C

C

Edge

R

R

1

0

W

C
R
0

CS

Rising

Edge

W

C
R
1

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FN8158.3

February 13, 2008

Write Data Register (DR)

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X9110

CS

Falling

Edge

Device Type

Identifier

010100A0

Device

Addresses

Instruction

Opcode

11 0 0RBRA00 XXXXXX

R/ W = 0

Register
Address

Wiper Position or Data
(Sent by Master on SI)

W

W

C

C

R

R

9

8

Transfer Data Register (DR) to Wiper Counter Register (WCR)

CS

Falling

Edge

Device Type

Identifier

010100A0

Device

Addresses

Instruction

Opcode

1100RBRA00

R/ W = 1

Register
Address

CS

Rising

Edge

Transfer Wiper Counter Register (WCR) to Data Register (DR)

CS

Falling

Edge

Device Type

Identifier

010100A0

Device

Addresses

Instruction

Opcode

1 1 1 0 RB RA 0 0

R/ W = 0

Register
Address

CS

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

Read Status Register (SR)

Wiper Position or Data
(Sent by Master on SI)

W

W

W

W

C

C

R

R

7

6

W

C

C

C

R

R

R

5

4

3

CS

W

C
R
2

Rising

W

W

Edge

C

C

R

R

1

0

WRITE CYCLE

HIGH-VOLTAGE

Device Type

CS

Falling

Edge

NOTES:

1. “A0”: stands for the device address sent by the master.

2. WCRx refers to wiper position data in the Wiper Counter Register

3. “X”: Don’t Care.

Identifier

010100A0

Device

Addresses

Instruction

Opcode

010X0001XXXXXXXX0000000WIP

R/ W = 1

Register

Addresses

Status Data

(Sent by Slave on SO)

Status Data

(Sent by Slave on SO)

CS

Rising

Edge

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FN8158.3

February 13, 2008

X9110

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Absolute Maximum Ratings Thermal Information

Voltage on SCK any Address Input

with Respect to V
Voltage on V+ (referenced to V
Voltage on V- (referenced to V

(V+) - (V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V

Any Voltage on R
Any Voltage on R
I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product relia bility and
result in failures not covered by warranty.

NOTE:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

4. θ

JA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

SS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+

H/RL

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-

L/RH

) (Note 8) . . . . . . . . . . . . . . . .10V

SS

) (Note 8) . . . . . . . . . . . . . . . . -10V

SS

Analog Specifications Over recommended industrial (2.7V) operation conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS

R

TOTAL

R
R

Vv+ Voltage on V+ Pin X9110 (Note 8) +4.5 +5.5 V

Vv- Voltage on V- Pin X9110 (Note 8) -5.5 -4.5 V

V

TERM

C

H/CL/CW

NOTES:

5. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.

6. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a
measure of the error in step size.

7. MI = RTOT/1023 or (R

8. V

9. n = 0, 1, 2, …,1023; m = 0, 1, 2, …, 1022.

End to End Resistance 100 kΩ
End to End Resistance Tolerance ±20 %
Power Rating +25°C, each potentiometer 50 mW

I

Wiper Current ±3 mA

W

Wiper Resistance Wiper Current = ±3mA, VCC = 3V 150 500 Ω

W

Wiper Resistance IW = ±3mA, VCC = 5V 100 Ω

W

X9110-2.7 (Note 8) +2.7 +5.5 V

X9110-2.7 (Note 8) -5.5 -2.7 V
Voltage on any RH or RL Pin V
Noise Ref: 1V -120 dBV
Resolution 0.1 %
Absolute Linearity (Note 5) R

Relative Linearity (Note 6) R

T emperature Coefficient of R
Ratiometric Temp. Coefficient 20 ppm/°C
Potentiometer Capacitancies See macro model 10/10/25 pF

– RL)/1023, single pot

H

, V+, V- must reach their final values within 1ms of each other.

CC

TOTAL

= 0V V- V+ V

SS

– [R
– [R

– R
– R

w(m)
w(m)

w(n)(expected)
w(n)(expected)

+ MI], where m = 8 to 1006 ±0.5 MI (Note 7)
+ MI] (Note 9) ±1 MI (Note 7)

w(n)(actual)

R

w(n)(actual)
w(m + 1)

R

w(m + 1)

Thermal Resistance (Typical, Note 4) θ

14 Lead TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

JA

(°C/W)

Recommended Operating Conditions

Temperature Range

Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage (V

X9110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%

X9110-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

, where n = 8 to 1006 ±1 MI (Note 7)

(Note 9) ±1.5 MI (Note 7)

) Limits (Note 8)

CC

MIN

(Note 13) TYP

MAX

(Note 13) UNITS

±300 ppm/°C

10

FN8158.3

February 13, 2008

X9110

www.BDTIC.com/Intersil

D.C. Operating Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

CC2

I

I
V

V

V
V
V

SB

I

LO

OH
OH

VCC Supply Current
(active)

VCC Supply Current
(nonvolatile write)

VCC Current (standby) SCK = SI = VSS, Addr. = VSS,

Input Leakage Current VIN = VSS to V

LI

Output Leakage Current V
Input HIGH Voltage VCC x 0.7 VCC + 1 V

IH

Input LOW Voltage -1 VCC x 0.3 V

IL

Output LOW Voltage IOL = 3mA 0.4 V

OL

Output HIGH Voltage IOH = -1mA, VCC ≥ +3V VCC - 0.8 V
Output HIGH Voltage IOH = -0.4mA, VCC ≤ +3V VCC - 0.4 V

f

= 2.5 MHz, SO = Open, VCC = 5.5V

SCK

Other Inputs = V
f

= 2.5MHz, SO = Open, VCC = 5.5V

SCK

Other Inputs = V

CS

= VCC = 5.5V

= VSS to V

OUT

SS

SS

CC

CC

Endurance and Data Retention

PARAMETER MIN UNITS

Minimum Endurance 100,000 Data changes per bit per register

Data Retention 100 years

(Note 13) TYP

MIN

MAX

(Note 13) UNITS

400 µA

15mA

3µA

10 µA
10 µA

Capacitance

SYMBOL TEST TEST CONDITIONS MAX UNITS

C

IN/OUT

C

(Notes 8, 10) Input/Output Capacitance (SI) V

(Note 10) Output Capacitance (SO) V

OUT

(Note 10) Input Capacitance (A0, CS, WP, HOLD, and SCK) VIN = 0V 6 pF

C

IN

= 0V 8 pF

OUT

= 0V 8 pF

OUT

Power-up Timing

SYMBOL PARAMETER MIN MAX UNITS

(Note 10) VCC Power-up Rate 0.2 50 V/ms

t

r VCC

(Notes 10, 11) Power-up to Initiation of Read Operation 1 ms

t

PUR

(Note 11) Power-up to Initiation of Write Operation 50 ms

t

PUW

NOTES:

10. Limits established by characterization and are not production tested.

PUR

and t

11. t

12. ESD Rating on R

13. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.

are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued.

PUW

, RL, RW pins is 1.5kV (HBM, 1.0µA leakage maximum), ESD rating on all other pins is 2.0kV.

H

A.C. Test Conditions

nput Pulse Levels VCC x 0.1 to VCC x 0.9

I

Input Rise and Fall Times 10ns
Input and Output Timing Level V

CC

x 0.5

11

FN8158.3

February 13, 2008

Equivalent A.C. Load Circuit

www.BDTIC.com/Intersil

X9110

1217Ω

2.7V

1382Ω

100pF

SPICE MACRO MODEL

R

H

C

L

10pF

R

TOTAL

R

L

C

25pF

R

W

C

W

L

10pF

SO pin

2714Ω

5V

1462Ω

SO pin

100pF

AC Timing

SYMBOL PARAMETER MIN MAX UNITS

f

SCK

t

CYC

t

WH

t

WL

t

LEAD

t

LAG

t

SU

t

H

t

RI

t

FI

t

DIS

t

V

t

HO

t

RO

t

FO

t

HOLD

t

HSU

t

HH

t

HZ

t

LZ

T

I

t

CS

t

WPASU

t

WPAH

SSI/SPI Clock Frequency 2.0 MHz
SSI/SPI Clock Cycle Time 400 ns
SSI/SPI Clock High Time 150 ns
SSI/SPI Clock Low Time 150 ns
Lead Time 150 ns
Lag Time 150 ns
SI, SCK, HOLD and CS Input Setup Time 50 ns
SI, SCK, HOLD and CS Input Hold Time 50 ns
SI, SCK, HOLD and CS Input Rise Time 50 ns
SI, SCK, HOLD and CS Input Fall Time 50 ns
SO Output Disable Time 0 500 ns
SO Output Valid Time 100 ns
SO Output Hold Time 0 ns
SO Output Rise Time 50 ns
SO Output Fall Time 50 ns
HOLD Time 400 ns
HOLD Setup Time 50 ns
HOLD Hold Time 50 ns
HOLD Low to Output in High Z 100 ns
HOLD High to Output in Low Z 100 ns
Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs 20 ns
CS Deselect Time 100 ns
WP, A0 Setup Time 0 ns
WP, A0 Hold Time 0 ns

12

FN8158.3

February 13, 2008

X9110

www.BDTIC.com/Intersil

High-Voltage Write Cycle Timing

SYMBOL PARAMETER TYP MAX UNITS

t

WR

High-Voltage Write Cycle Time (store instructions) 5 10 ms

XDCP Timing

SYMBOL PARAMETER MIN MAX UNITS

t

WRPO

t

WRL

Wiper Response Time After the Third (last) Power Supply is Stable 5 10 µs
Wiper Response Time After Instruction Issued (all load instructions) 5 10 µs

Symbol Table

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

13

FN8158.3

February 13, 2008

Timing Diagrams

www.BDTIC.com/Intersil

Input Timing

CS

t

LEAD

X9110

t

CYC

t

CS

t

LAG

SCK

SI

SO

Output Timing

CS

SCK

SO

ADDR

SI

Hold Timing

t

SU

MSB LSB

HIGH IMPEDANCE

t

H

t

V

MSB LSB

t

WL

t

HO

t

...

WH

...

...

...

t

FI

t

RI

t

DIS

CS

SCK

SO

HOLD

t

HSU

t

RO

SI

t

t

HOLD

FO

t

HZ

14

t

HH

...

t

LZ

FN8158.3

February 13, 2008

XDCP Timing (For All Load Instructions)

www.BDTIC.com/Intersil

CS

X9110

SCK

MSB LSB

R

SO

SI

W

HIGH IMPEDANCE

Write Protect And Device Address Pins Ti ming

CS

WP

A0
A1

t

WPASU

(ANY INSTRUCTION)

Applications information

Basic Configurations Of Electronic Potentiometers

...

...

t

WPAH

t

WRL

V

R

Three terminal Potentiometer;
Variable voltage divider

RW

+V

R

I

Two terminal Variable Resistor;
Variable current

15

FN8158.3

February 13, 2008

Application Circuits

www.BDTIC.com/Intersil

NONINVERTING AMPLIFIER VOLTAGE REGULATOR

X9110

V

S

VO = (1+R2/R1)V

OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERISIS

V

S

10kΩ

R

100kΩ

+
–

R

R

1

S

1

–
+

TL072

10kΩ10kΩ

V

O

2

R

2

V

O

IN

VO (REG) = 1.25V (1+R2/R1)+I

V

S

VUL = {R1/(R1+R2)} VO(max)

= {R1/(R1+R2)} VO(min)

RL

L

317

I

adj

R

2

–
+

}

}

R

R

2

1

R

1

adj R2

VO (REG)V

V

O

-12V+12V

16

FN8158.3

February 13, 2008

Application Circuits (continued)

www.BDTIC.com/Intersil

ATTENUATOR FILTER

R

1

V

S

V

S

R

3

R

VO = G V

-1/2 ≤ G ≤ +1/2

INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT

R

R

1

}

–
+

4

R1 = R2 = R3 = R4 = 10kΩ

S

2

}

X9110

C

V

R

2

V

O

–
+

V

O

S

R

= 1 + R2/R

G

O

fc = 1/(2πRC)

C

1

V

S

+
–

R

R

1

1

R

2

+
–

V

O

2

VO = G V
G = - R2/R

FUNCTION GENERATOR

frequency ∝ R1, R2, C
amplitude ∝ R

S

1

–
+

, R

A

B

R

Z

IN

1

R

3

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R

R

2

R

}

A

R

}

B

R

1

+ R3) >> R

1

C

–
+

2

17

FN8158.3

February 13, 2008

X9110

www.BDTIC.com/Intersil

Thin Shrink Small Outline Plastic Packages (TSSOP)

N

INDEX
AREA

123

0.05(0.002)

-A­D

e

b

0.10(0.004) C AM BS

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen­sion at maximum material condition. Minimum space between protru­sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)

E1

-B-

SEATING PLANE

A

-C-

M

0.25(0.010) BM M

E

α

A1

0.10(0.004)

GAUGE
PLANE

0.25

0.010

A2

L

c

M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.041 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.195 0.199 4.95 5.05 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N14 147

o

α

0

o

8

o

0

o

8

NOTESMIN MAX MIN MAX

-

Rev. 2 4/06

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or i t s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

18

FN8158.3

February 13, 2008