intersil X9110 DATA SHEET

®

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X9110

Dual Supply/Low Power/1024-Tap/SPI Bus

Data Sheet February 13, 2008

Single Digitally-Controlled (XDCP™)
Potentiometer

The X9110 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.

The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.

The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.

FN8158.3

Features

• 1024 Resistor Taps – 10-Bit Resolution

• SPI Serial Interface for write, read, and transfer operations
of the potentiometer

• Wiper Resistance, 40Ω Typical @ 5V

• Four Non-Volatile Data Registers

• Non-Volatile Storage of Multiple Wiper Positions

• Power-on Recall. Loads Saved Wiper Position on Power-up

• Standby Current < 3µA Max

• System V

• Analog V+/V-: -5V to +5V

•100kΩ End to End Resistance

• 100 yr. Data Retention

• Endurance: 100, 000 Data Changes Per Bit Per Register

• 14 Ld TSSOP

• Dual Supply Version of the X9111

• Low Power CMOS

: 2.7V to 5.5V Operation

CC

Functional Diagram

SPI

BUS

INTERFACE

ADDRESS

DATA

STATUS

V

CC

BUS

INTERFACE &

CONTROL

WRITE

READ

TRANSFER

CONTROL

• Pb-Free Available (RoHS Compliant)

Pinout

X9110

14 LD TSSOP

TOP VIEW

V+

1

S0

2

A0

3

POWER-ON RECALL

WIPER COUNTER

REGISTER (WCR)

DATA REGISTERS

(DR0-DR3)

SCK

V

WP

SS

SI

4

5

6

7

WIPER

R

H

POT

14

13

12

11

10

9
8

V+

100kΩ
1024-TAPS

V

CC

R

L

R

H

R

W

HOLD

CS

V-

V

SS

1

NC NC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas INC. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

R

W

R

L

V-

Ordering Information

www.BDTIC.com/Intersil

X9110

PART NUMBER PART MARKING

VCC LIMITS

(V)

POTENTIOMETE

R RANGE (kΩ)

TEMP

RANGE (°C) PACKAGE

PKG.

DWG. #

X9110TV14 X9110TV 5 ±10 100 0 to +70 14 Ld TSSOP M14.173
X9110TV14Z* (Note) X9110TV Z 0 to +70 14 Ld TSSOP (Pb-free) M14.173
X9110TV14I X9110TV I -40 to +85 14 Ld TSSOP M14.173
X9110TV14IZ (Note) X9110TV Z I -40 to +85 14 Ld TSSOP (Pb-free) M14.173
X9110TV14-2.7 X9110TV F 2.7 to 5.5 0 to +70 14 Ld TSSOP M14.173
X9110TV14Z-2.7 (Note) X9110TV Z F 0 to +70 14 Ld TSSOP (Pb-free) M14.173
X9110TV14I-2.7 X9110TV G -40 to +85 14 Ld TSSOP M14.173
X9110TV14IZ-2.7* (Note) X9110TV Z G -40 to +85 14 Ld TSSOP (Pb-free) M14.173
*Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.

Detailed Functional Diagram

V

CC

V+

HOLD

CS

SCK

SO

A0

WP

POWER ON

RECALL

DR0 DR1

INTERFACE

AND

SI

CONTROL

CIRCUITRY

V

SS

DATA

CONTROL

DR2 DR3

WIPER
COUNTER
REGISTER

(WCR)

100kΩ
1024-TAPS

V-

R

H

R

L

R

W

2

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February 13, 2008

X9110

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Circuit Level Applications

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage amplifier
circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and Q-factor in
filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF circuits

• Provide a control variable (I, V, or R) in feedback circuits

System Level Applications

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems

• Control the gain in audio and home entertainment systems

• Provide the variable DC bias for tuners in RF wireless
systems

• Set the operating points in temperature control systems

• Control the operating point for sensors in industrial
systems

• Trim offset and gain errors in artificial intelligent systems

Pin Descriptions

PIN

(TSSOP) SYMBOL FUNCTION

1 V+ Analog Supply Voltage
2 SO Serial Data Output
3 A0 Device Address
4 SCK Serial Clock
5WP
6 SI Serial Data Input
7V
8V
9CS

10 HOLD

SS

Hardware Write Protect

System Ground

- Analog Supply Voltage

Chip Select
Device Select. Pause the Serial Bus

Pin Descriptions (Continued)

PIN

(TSSOP) SYMBOL FUNCTION

11 R
12 R
13 R
14 V

W

CC

Bus Interface Pins

SERIAL OUTPUT (SO)

SO is a serial data output pin. During a read cycle, data is
shifted out on this pin. Data is clocked out on the falling edge
of the serial clock.

SERIAL INPUT (SI)

SI is the serial data input pin. All opcodes, byte addresses
and data to be written to the pots and pot registers are input
on this pin. Data is latched by the rising edge of the serial
clock.

SERIAL CLOCK (SCK)

The SCK input is used to clock data into and out of the
X9110.

HOLD (HOLD

is used in conjunction with the CS pin to select the

HOLD
device. Once the part is selected and a serial sequence is
underway , HOLD
communication with the controller without resetting the serial
sequence. To p ause, HOLD
LOW. To resume communication, HOLD
while SCK is LOW. If the p ause feature is not used, HOLD
be held HIGH at all times.

DEVICE ADDRESS (A0)

The address input is used to set the 8-bit slave address. A
match in the slave address serial data stream A0 must be
made with the address input (A0) in order to initiate
communication with the X9110.

CHIP SELECT (CS

When CS
is at high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state. CS
enables the X9110, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS
operation.

HARDWARE WRITE PROTECT INPUT (WP

The WP
Data Registers.

)

may be used to pause the serial

is HIGH, the X9110 is deselected and the SO pin

is required prior to the start of any

pin when LOW prevents nonvolatile writes to the

Wiper Terminal of the Potentiometer
High Terminal of the Potentiometer

H

Low Terminal of the Potentiometer

L

System Supply Voltage

must be brought LOW while SCK is

is brought HIGH, again

)

should

LOW

)

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X9110

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SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

If WCR = 000[HEX] then RW = R
If WCR = 3FF[HEX] then RW = R

REGISTER 0

(DR0)

10 10

REGISTER 2

(DR2)

L

H

FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM

REGISTER 1

(DR1)

REGISTER 3

(DR3)

Potentiometer Pins

RH, RL

The R

and RL pins are equivalent to the terminal

H

connections on a mechanical potentiometer.

R

W

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.

Bias Supply Pins

SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (V

The V

CC

)

SS

pin is the system supply voltage. The VSS pin is

the system ground.

ANALOG SUPPLY VOLTAGES (V+ AND V

-)

These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper switches
while the V- supply is used to bias the switches and the
internal P+ substrate of the integrated circuit. Both of these
supplies set the voltage limits of the potentiometer.

Principles Of Operation

Device Description

SERIAL INTERFACE

The X91 10 supports the SPI interface hardware conventions.
The device is accessed via the SI input with data clocked-in

SERIAL
BUS
INPUT

PARALLEL
BUS
INPUT

WIPER
COUNTER
REGISTER

(WCR)

on the rising SCK. CS

C
O
U
N
T
E
R

D
E
C
O
D
E

must be LOW and the HOLD and WP

R

H

R

L

R

W

pins must be HIGH during the entire operation.
The SO and SI pins can be connected together, since they

have three state outputs. This can help to reduce system pin
count.

ARRAY DESCRIPTION

The X9110 is comprised of a resistor array (Figure 1). The
array contains the equivalent of 1023 discrete resistive
segments that are connected in series. The physical ends of
each array are equivalent to the fixed te rmi nals of a
mechanical potentiometer (R

and RL inputs).

H

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (R

)

W

output. Within the individual array only one switch may be
turned on at a time.

These switches are controlled by a Wiper Counter Register
(WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to
select, and enable, one of 1024 switches.

WIPER COUNTER REGISTER (WCR)

The X9110 contains a Wiper Counter Register (see Table 1)
for the XDCP potentiometer. The WCR is equivalent to a
serial-in, parallel-out register/counter with its outputs
decoded to select one of 1024 switches along its resistor
array. The contents of the WCR can be altered in one of
three ways: (1) it may be written directly by the host via the
write Wiper Counter Register instruction (serial load); (2) it

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X9110

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may be written indirectly by transferring the contents of one
of four associated Data Registers via the XFR Data Register;
(3) it is loaded with the contents of its data register zero
(DR0) upon power-up.

The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X91 10 is powered-down. Although
the register is automatically loaded with the value in DR0 upon
power-up, this may be different from the value present at
power-down. Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR.

DATA REGISTERS (DR)

The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the Wiper Counter Register. All operations
changing data in one of the Data Registers is a nonvolatile
operation and will take a maximum of 10ms.

TABLE 1. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: Used To Store The Current Wiper Position (Volatile, V)

WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0

VVVVVVVVVV

(MSB) (LSB)

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.

DR[9:0] is used to store one of the 1024 wiper position
(0~1023) (see Table 2).

STATUS REGISTER (SR)

This 1-bit status register is used to store the system status
(see Table 3).

WIP: Write In Progress status bit, read only.

• When WIP = 1, indicates that high-voltage write cycle is in
progress.

• When WIP=0, indicates that no high-voltage write cycle is
in progress.

TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: Used to store wiper positions or data (Non-Volatile, NV)

BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

NV NV NV NV NV NV NV NV NV NV

MSB LSB

TABLE 3. STATUS REGISTER, SR (1-BIT)

WIP

(LSB)

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February 13, 2008

X9110

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TABLE 4. IDENTIFICATION BYTE FORMAT

DEVICE TYPE

IDENTIFIER

ID3 ID2 ID1 ID0 0 0 A0 R/W

0101

(MSB) (LSB)

TABLE 5. INSTRUCTION BYTE FORMAT

0
0
1
1

REGISTER

SELECTION

0
1
0
1

DR0
DR1
DR2
DR3

INSTRUCTION

OPCODE

I2 I1 I0 0 RB RA 0 0

(MSB) (LSB)

RB RA REGISTER

INTERNAL SLAVE

ADDRESS

READ OR
WRITE BIT

Device Instructions

Identification Byte (ID and A)

The first byte sent to the X9110 from the host, following a CS
going HIGH to LOW, is called the Identification Byte. The
most significant four bits of the slave address are a device
type identifier. The ID[3:0] bits is the device ID for the X9110;
this is fixed as 0101[B] (refer to Table 4).

The A0 bit in the ID byte is the internal slave address. The
physical device address is defined by the state of the A0 input
pin. The slave address is externally specified by the user. The
X911 0 compares the serial dat a stream with the address input
state; a successful compare of the address bit is required for
the X911 0 to successfully continu e the co mmand seq uence.
Only the device whose slave address matches the incoming
device address sent by the master executes the instruction.
The A0 input can be actively driven by CMOS input signals or
tied to V
either read or write mode.

Instruction Byte and Register Selection

The next byte sent to the X9110 contains the instruction and
register pointer information. The three most significant bits
are used provide the instruction opcode (I[2:0]). The RB and
RA bits point to one of the four registers. The format is
shown in Table 5.

Five of the seven instructions are four bytes in length. These
instructions are:

• Read Wiper Counter Register – read the current wiper
position of the selected pot

or VSS. The R/W bit is used to set the device to

CC

• Write Dat a Register – write a new value to the sel ected
data register

• Read Status – This command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress

The basic sequence of the four byte instructions is illustrated
in Figure 3. These four-byte instructions exchange data
between the WCR and one of the Data Registers. A transfer
from a Data Register to a WCR is essentially a write to a
static RAM, with the static RAM controlling the wiper
position. The response of the wiper to this action will be
delayed by t

. A transfer from the WCR (current wiper

WRL

position), to a Data Register is a write to nonvolatile memory
and takes a minimum of t

to complete. The transfer can

WR

occur between the potentiometer and one of its associated
registers. The Read Status Register instruction is the only
unique format (see Figure 4).

Two instructions require a two-byte sequence to complete
(See Figure 2). These instructions transfer data between the
host and the X9110; either between the host and one of the
Data Registers or directly between the host and the Wiper
Counter Register. These instructions are:

• XFR Data Register to Wiper Counter Register – This
transfers the contents of one specified Data Register to
the associated Wiper Counter Register

• XFR Wiper Counter Register to Data Register – This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register

See Instruction format for more details.

• Write Wiper Counter Register – change current wiper
position of the selected pot

• Read Data Register – read the contents of the selected
data register

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FN8158.3

February 13, 2008