The Intersil X9015 is a 32 tap potentiometer that is volatile.
The device consists of a string of 31 resistors that can be
programmed to connect the R
the nodes between the connecting resistors. The connection
point of the wiper is determined by information
communicated to the device on the 3-wire port. The 3-wire
port changes the tap position by a falling edge on the
increment pin. The direction the wiper moves is determined by
the state of the up/down pin. The wiper positi on at power up is
Tap #15.
The X9015 can be used in a wide variety of applications that
require a digitally controlled variable resistor to set analog
values.
wiper output with any of
W/VW
FN8157.5
Features
•32 taps
• Three-wire up/down serial interface
•VCC = 2.7V–5V
• Operating I
= 50µA max.
CC
• Standby current = 1µA max.
•R
TOTAL
= 10kΩ, 50kΩ
• Packages 8 Ld SOIC, 8 Ld MSOP
• Pb-free plus anneal available (RoHS compliant)
Pinout
SOIC/MSOP
V
CC
8
CS
7
R
L/VL
6
RW/V
5
W
RH/V
V
INC
U/D
SS
1
2
H
X9015
3
4
Block Diagram
V
(Supply Voltage)
CC
Up/Down
)
(U/D
Increment
(INC
Device Select
(CS
Control
)
)
(Ground)
V
SS
General
R
H/VH
RW/V
RL/V
U/D
INC
CS
W
L
V
CC
V
SS
5-Bit
Up/Down
Counter
Control
Circuitry
One
of
Thirty
Two
Decoder
31
30
29
28
2
1
0
Detailed
Transfer
Gates
Resistor
Array
RH/V
RL/V
RW/V
H
L
W
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Ordering Information
www.BDTIC.com/Intersil
X9015
TEMPERATURE
PART NUMBERPART MARKINGVCC LIMITS (V)R
X9015WS8T1X9015W5 ±10%100 to +708 Ld SOIC
X9015WS8ZT1 (Note)X9015W Z0 to +708 Ld SOIC (Pb-free)
X9015UM8ABB500 to +708 Ld MSOP M8.118
X9015UM8Z (Note)DCF0 to +708 Ld MSOP (Pb-free)M8.118
X9015UM8I*ABD-40 to +858 Ld MSOP M8.118
X9015UM8IZ* (Note)DCD-40 to +858 Ld MSOP (Pb-free)M8.118
X9015US8*X9015U0 to +708 Ld SOIC M8.15
X9015US8Z* (Note)X9015U Z0 to +708 Ld SOIC (Pb-free)M8.15
X9015US8I*X9015U I-40 to +858 Ld SOIC M8.15
X9015US8IZ* (Note)X9015U Z I-40 to +858 Ld SOIC (Pb-free)M8.15
X9015WS8-2.7*X9015W F2.7-5.5100 to +708 Ld SOIC M8.15
X9015WS8Z-2.7* (Note)X9015W ZF0 to +70 8 Ld SOIC (Pb-free)M8.15
X9015UM8-2.7*ABC500 to +708 Ld MSOP M8.118
X9015UM8Z-2.7* (Note)DCF0 to +708 Ld MSOP (Pb-free)M8.118
X9015UM8I-2.7*ABE-40 to +858 Ld MSOP M8.118
X9015UM8IZ-2.7* (Note) DCE-40 to +858 Ld MSOP (Pb-free)M8.118
X9015US8-2.7*X9015U F0 to +708 Ld SOIC M8.15
X9015US8Z-2.7* (Note)X9015U ZF0 to +70 8 Ld SOIC (Pb-free)M8.15
X9015US8I-2.7*X9015U G-40 to +858 Ld SOIC M8.15
X9015US8IZ-2.7* (Note)X9015U ZG-40 to +858 Ld SOIC (Pb-free)M8.15
* Add “T1” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
TOTAL
(kΩ)
RANGE (°C)PACKAGE
Tape and Reel
Tape and Reel
PKG.
DWG. #
M8.15
M8.15
2
FN8157.5
August 31, 2006
X9015
www.BDTIC.com/Intersil
Pin Descriptions
RH/VH and RL/V
The high (RH/VH) and low (RL/VL) terminals of the X9015 are
equivalent to the fixed terminals of a mechanical
potentiometer. The minimum volt age is V
maximum is V
references the relative position of the terminal in relation to
wiper movement direction selected by the U/D
the voltage potential on the terminal.
RW/V
W
RW/Vw is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs.
The wiper terminal series resistance is typically 200Ω at
V
=5V. At power up the wiper position is at Tap #15.
CC
(V
=Tap #0).
L/RL
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the tap position is incremented or decremented.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the U/D
input.
Chip Select (CS)
The device is selected when the CS input is LOW. When CS
is returned HIGH while the INC
will be placed in the low power standby mode until the device
is selected once again.
L
and the
SS
. The terminology of RL/VL and RH/VH
CC
input, and not
input is also HIGH the X9015
Pin Names
SYMBOLDESCRIPTION
RH/V
RW/V
RL/V
V
SS
V
CC
U/D
INC
CS
H
W
L
High terminal
Wiper terminal
Low terminal
Ground
Supply voltage
Up/Down control input
Increment control input
Chip select control input
The wiper, when at either fixed terminal, act s li ke it s
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
connected to the wiper for t
R
significant amount if the wiper is moved several positi ons.
When the device is powered-down, the wiper position is lost.
When power is restored, the wiper is set to Tap #15.
value for the device can temporarily be reduced by a
TOTAL
(INC to VW change). The
IW
Instructions and Programming
The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS
selected and enabled to respond to the U/D
HIGH to LOW transitions on INC
(depending on the state of the U/D
The output of this counter is decoded to select one of thirty
two wiper positions along the resistive array.
The system may select the X9015, move the wiper and
deselect the device. The new wiper position will be maintained
until changed by the system or until a power-up/down cycle.
The state of U/D
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
may be changed while CS remains LOW.
set LOW the device is
and INC inputs.
will increment or decrement
input) a five bit counter.
Mode Selection
CSINCU/DMODE
LH
LL
HX
HXX
LLX
LHWiper Up (not recommended)
LL
Wiper up
Wiper down
Standby mode
Standby mode
Normal mode
Wiper Down (not recommended)
Principles Of Operation
There are two sections of the X9015: the input control,
counter and decode section; and the resistor array . The input
control section operates just like an up/down counter. The
output of this counter is decoded to turn on a sin gle electronic
switch connecting a point on the resistor array to the wiper
output. The resistor array is comprised of 31 individual
resistors connected in series.
3
FN8157.5
August 31, 2006
X9015
www.BDTIC.com/Intersil
Absolute Maximum RatingsOperating Conditions
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
)
Potentiometer Specifications Over recommended operating conditions unless otherwise stated
The are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins
provided that V
always in effect.
NOTES:
1. Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage = (V
2. Relative Linearity is a measure of the error in step size between
taps = V
3. 1 Ml = Minimum Increment = R
4. Typical values are for T
5. This parameter is periodically sampled and not 100% tested.
is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC ramp rate spec is
CC
W
(n+1)
– [V
+ Ml] = ±0.2 Ml.
w(n)
/31.
TOT
= +25°C and nominal supply voltage.
A
(actual)–V
w(n)
(expected)) = ±1 Ml Maximum.
w(n)
4
FN8157.5
August 31, 2006
X9015
www.BDTIC.com/Intersil
)
D.C. Operating Specifications Over recommended operating conditions unless otherwise specified
VCC active current (increment)CS = VIL, U/D = VIL or VIH and
= 0.4V @ max. t
VCC active current (Store) (EEPROM
Store)
INC
CS = VIH, U/D = VIL or VIH and
INC
=V
@ max. t
IH
CYC
WR
Standby supply currentCS = VCC – 0.3V, U/D and
=VSS or VCC – 0.3V
INC
CS, INC, U/D input leakage currentVIN = V
CS, INC, U/D input HIGH voltageV
SS
to V
CC
x 0.7VCC + 0.5V
CC
CS, INC, U/D input LOW voltage-0.5V
f= 1MHz
TEST CIRCUIT #1TEST CIRCUIT #2CIRCUIT #3 SPICE MACRO MODEL
(Note 4)MAX.UNITS
50µA
400µA
1µA
±10µA
x 0.1V
CC
10pF
VH/R
H
V
S
VL/R
Test Point
VW/R
L
Symbol Table
WAVEFORMINPUTSOUTPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/ACenter Line
W
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
is High
Impedance
VH/R
V
VL/R
L
H
L
VW/R
VW
Test Point
W
Force
Current
R
R
H
10pF
TOTAL
C
C
H
W
25pF
R
W
C
10pF
R
L
L
A.C. Conditions of Test
Input pulse levels0V to 3V
Input rise and fall times10ns
Input reference levels1.5V
5
FN8157.5
August 31, 2006
X9015
www.BDTIC.com/Intersil
A.C. Operating Specifications Over recommended operating conditions unless otherwise specified
SYMBOLPARAMETERMIN.TYP. (Note 6)MAX.UNIT
t
Cl
t
lD
t
DI
t
lL
t
lH
t
lC
t
CPH
t
CPH
t
IW
t
CYC
t
(Note 7) INC input rise and fall time500µs
R, tF
(Note 7)Power up to wiper stable5µs
t
PU
(Note 7) VCC power-up rate0.250V/ms
t
R VCC
t
WR
CS to INC setup100ns
INC HIGH to U/D change100ns
U/D to INC setup2.9µs
INC LOW period1µs
INC HIGH period1µs
INC inactive to CS inactive1µs
CS deselect time (NO STORE)100ns
CS deselect time (STORE)10ms
INC to Vw change15µs
INC cycle time4µs
Store cycle510ms
A.C. Timing
CS
t
CYC
t
IC
t
DI
(8)
MI
INC
U/D
V
t
CI
t
IW
W
t
IL
t
ID
t
IH
NOTES:
6. Typical values are for T
= +25°C and nominal supply voltage.
A
7. This parameter is periodically sampled and not 100% tested.
8. MI in the A.C. timing diagram refers to the minimum incremental change in the V
(store)
t
CPH
90%90%
10%
t
F
output due to a change in the wiper position.
W
t
R
6
FN8157.5
August 31, 2006
Performance Characteristics (Typical)
www.BDTIC.com/Intersil
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
NOISE (dB)
-100
-110
-120
-130
-140
-150
0 102030405060708090100
FIGURE 1. TYPICAL NOISE
10000
9800
9600
9400
9200
9000
RTOTAL
8800
8600
8400
8200
8000
-55
-45
-35 -25 -15 -55
X9015
FREQUENCY (kHz)
15 25
110 120 130 140 150 160 170 180 190 200
35 45
TEMPERATURE
55 65 75
85 95 105 11 5 125
C
FIGURE 2. TYPICAL RTOTAL VS. TEMPERATURE
0
-50
-100
-150
PPM
-200
-250
-300
-350
-55
-45 -35 -25 -15 -5515 25 35
TEMPERATURE
45 55 65 75 85 95 105 115 12 5 C
FIGURE 3. TYPICAL TOTAL RESISTANCE TEMPERATURE COEFFICIENT
7
FN8157.5
August 31, 2006
X9015
www.BDTIC.com/Intersil
Performance Characteristics (Typical) (Continued)
800
700
600
500
400
RW (Ω)
300
200
100
0
0
246810121416
FIGURE 4. TYPICAL WIPER RESISTANCE
40.0%
30.0%
20.0%
10.0%
0.0%
-10.0%
-20.0%
ABSOLUTE% ERROR
-30.0%
-40.0%
03691215
FIGURE 5. TYPICAL ABSOLUTE% ERROR PER TAP POSITION
1820222426283032 VCC = 2.7V
TAP
18212 42730
Tap
20.0%
15.0%
10.0%
5.0%
0.0%
-5.0%
-10.0%
RELATIVE% ERROR
-15.0%
-20.0%
03691215
1821242730
TAP
FIGURE 6. TYPICAL RELATIVE% ERROR PER TAP POSITION
8
FN8157.5
August 31, 2006
X9015
www.BDTIC.com/Intersil
Applications Information
Electronic digitally controlled potentiometers provide two powerful application advantages: (1) the variability and reliability of a
solid-state potentiometer, and (2) the flexibility of computer-based digital controls.
Basic Configurations of Electronic Potentiometers
V
R
I
VH/R
VL/R
V
R
H
L
VW/R
W
Basic Circuits
R
+V
IN
1
V
REF
VOLTAGE REGULATOR
317
I
adj
VO (REG) = 1.25V (1+R2/R1)+I
THREE-TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER
+5V
V
R
W/RW
V
2
+
–
OUT
R
1
adj R2
–5V
= V
OP-07
W
V
OUT
VO (REG)V
Cascading TechniquesBuffered Reference Voltage
+V+V
–
+
R
2
TL072
X
VW/R
W
+V
(a)(b)
OFFSET VOLTAGE ADJUSTMENT
R
V
S
10kΩ
1
100kΩ
10kΩ10kΩ
-12V+12V
TWO-TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
Noninverting Amplifier
+5V
VW/R
V
S
W
+
–
–5V
R
1
VO = (1+R2/R1)V
COMPARATOR WITH HYSTERESIS
LT311A
V
S
V
O
V
= {R1/(R1+R2)} VO(max)
UL
V
= {R1/(R1+R2)} VO(min)
LL
R
–
+
}
}
R
2
1
LM308A
R
2
S
V
O
V
O
9
(FOR ADDITIONAL CIRCUITS, SEE AN115.)
FN8157.5
August 31, 2006
Small Outline Plastic Packages (SOIC)
www.BDTIC.com/Intersil
X9015
N
INDEX
AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010)BMM
H
L
h x 45°
α
e
B
0.25(0.010)C AMBS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M
A1
C
0.10(0.004)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHESMILLIMETERS
SYMBOL
A0.05320.06881.351.75-
A10.00400.00980.100.25-
B0.0130.0200.330.519
C0.00750.00980.190.25-
D0.18900.19684.805.003
E0.14970.15743.804.004
e0.050 BSC1.27 BSC-
H0.22840.24405.806.20-
h0.00990.01960.250.505
L0.0160.0500.401.276
N887
α
0°8°0°8°-
NOTESMINMAXMINMAX
Rev. 1 6/05
10
FN8157.5
August 31, 2006
X9015
www.BDTIC.com/Intersil
Mini Small Outline Plastic Packages (MSOP)
N
EE1
INDEX
AREA
AA1A2
-H-
SIDE VIEW
12
TOP VIEW
b
e
D
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane.Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- H -
-A -
.
10. Datumsandto be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
-B-
0.20 (0.008) A
GAUGE
PLANE
SEATING
PLANE
0.10 (0.004) C
-A-
0.20 (0.008) C
- B -
0.25
(0.010)
-C-
SEATING
PLANE
a
0.20 (0.008) C
- H -
B
4X θ
C
D
4X θ
L1
C
C
L
E
1
END VIEW
R1
R
L
-B-
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHESMILLIMETERS
SYMBOL
A0.0370.0430.941.10-
A10.0020.0060.050.15-
A20.0300.0370.750.95-
b0.0100.0140.250.369
c0.0040.0080.090.20-
D0.1160.1202.953.053
E10.1160.1202.953.054
e0.026 BSC0.65 BSC-
E0.1870.1994.755.05-
L0.0160.0280.400.706
L10.037 REF0.95 REF-
N887
R0.003-0.07--
R10.003-0.07--
05
α
o
o
0
15
o
o
6
o
5
o
0
15
o
o
6
Rev. 2 01/03
NOTESMINMAXMINMAX
-
-
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN8157.5
August 31, 2006
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