查询X80010供应商
®
X80010, X80011, X80012, X80013
PRELIMINARY
Data Sheet January 13, 2005
Penta-Power Sequence Controller
with Hot swap and System Management
The X80010, X80011, X80012, X80013 contain three major
functions: a power sequencing controller, a hotswap
controller, and systems management support.
The power sequencer controller time sequences up to five
DC/DC modules. The device allows various DC/DC power
sequencing configurations, either parallel or relay modes.
The power good, enable, and voltage good signals provide
for flexible DC/DC timing configurations. Each voltage
enable signal has a built-in delay while additional delay can
be added with simple external passive components.
The hot swap controller allows a board to be safely inserted
and removed from a live backplane without turning off the
main power supply. The X80010 family of devices offers a
modular, power distribution approach by providing flexibility
to solve the hotswap and power sequencing issues for
insertion, operations, and extraction. Hardshort Detection
and Retry with Delay, Noise filtering, Insertion Overcurrent
Bypass, and Gate Current selection are some of the
integrated features of the device. During insertion, the gate
of an external power MOSFET is clamped low to suppress
contact bounce. The undervoltage/overvoltage circuits and
the power on reset circuitry suppress the gate turn on until
the mechanical bounce has ended. The X80010 turns on the
gate with a user set slew rate to limit the inrush current and
incorporates an electronic circuit breaker set by a sense
resistor. After the load is successfully charged, the PWRGD
signal is asserted; indicating that the device is ready to
power sequence the DC/DC power bricks.
FN8149.0
Features
• Integrates Three Major Functions
- Power Sequencing
- Hot Swap Controller
- System Management Functions
• Penta-Power Sequencing
- Sequence up to 5 DC/DC converters.
- Four independent voltage enable pins
- Four time delay circuits
- Soft Power Sequencing - MRC pin restarts sequence
without power cycling.
• Hot Swap Controller
- Programmable overvoltage and undervoltage protection
- Undervoltage lockout for battery/redundant supplies
- Electronic circuit breaker - Overcurrent Detection and
Gate Shut-off
- Overcurrent limit during Insertion
- Hardshort retry with retry failure flag
- Selectable gate current using IGQ pins (10, 70, 150µA)
- MRH pin controls board insertion/extraction.
- Typically operates from -30V to -80V. Tolerates
transients to -200V (limited by external components)
• System Management
- Reset output, with delay, holds off host until all supplies
are good
- Host control of reinsertion with MRH input
- Host control of resequencing using MRC input
• Available packages
- 32-lead Quad No-Lead Frame (QFN)
Systems management function provides a reset signal
indicating that the power good and all the voltage good
signals are active. The reset signal is asserted after a wait
state delay. This signal is used to coordinate the hotswap
and DC/DC module latencies during power up to avoid
"power hang up". In addition, the CPU host can initiate soft
insertion or DC voltage module re-sequencing.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Applications
• -48V Hot Swap Power Backplane/Distribution Central
Office, Ethernet for VOIP
• Card Insertion Detection
• Power Sequencing DC/DC/Power Bricks
• IP Phone Applications
• Databus Power Interfacing
• Custom Industrial Power Backplanes
• Distributed Power Systems
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
Pinout
QFN package
(Top view)
GQ0
I
MRH
I
32
V
RGO
NA1
V4GOOD
EN4
V3GOOD
EN3
V2GOOD
EN2 817
1
2
3
4
(7mm x 7mm)
5
6
7
91011121314
EE
DD
V
V
Ordering Information
X80010, X80011, X80012, X80013
GQ1
PWRGD
UV/OV
V
SENSE
EE
V
FAR
BA TT-ON
NC
262728293031
GATE
25
15
16
NA1
DRAIN
24
23
22
21
20
19
18
NA1
NC
MRC
NA1
RESET
V1GOOD
EN1
NA2
NA2
RETRY
DELAY
(ms)
I
GATE
(µA)
T
DELAY
(ms)
t
POR
(ms)
TEMP RANGE
(°C)
MARK
ORDER
NUMBER
OV
(V)
UV1
(V)
UV2
(V)
t
NF
(us)
V
OC
(mV)
V
OCI
(mV)
OVER
CURRENT
RETRY
X80010Q32I 74.9 42.4 33.2 5 50 150 Always 100 50 100 100 -40 to 85 80010I
X80011Q32I 68.0 42.4 33.2 5 50 150 Always 100 50 100 100 -40 to 85 80011I
X80012Q32I 74.9 42.4 33.2 5 50 150 5 retries 100 50 100 100 -40 to 85 80012I
X80013Q32I 68.0 42.4 33.2 5 50 150 5 retries 100 50 100 100 -40 to 85 80013I
Typical Application
BackPlane
-48V
RTN
-48V
R5
30k
1%
12V
R4
182k
1%
R6
10k
1%
4.7V
X80010, X80011,
X80012, X80013
OV=71V
V
UV/OV
UV=37V
V
DD
V
SENSE
EE
0.1uF
Rs
0.02Ω
5%
IRFR120
GATE
Q1
PWRGD
V1GOOD
V2GOOD
V3GOOD
DRAIN
100
EN1
EN2
EN3
4.7K
3.3n
100K
DC/DC
Module
1
ON/OFF
DC/DC
Module
2
ON/OFF
V1
DC/DC
Module
3
ON/OFF
V2
DC/DC
Module
4
ON/OFF
V3
PAR T
V4
2
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
Absolute Maximum Ratings Recommended Operating Conditions
Temperature under bias . . . . . . . . . . . . . . . . . . . . . –65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Voltage on given pin (Hot Side Functions):
V
ov/uv pin
SENSE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400mV + V
VEE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -80V
DRAIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48V + V
PWRGD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V + V
GATE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD + V
FAR pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V + V
MRH pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V + V
BATT_ON pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V + V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V + V
EE
EE
EE
EE
EE
EE
EE
EE
Voltage on given pin (Cold Side Functions):
ENi
pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V
ViGOOD
RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + V
MRC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V + V
IGQ1 and IGQ0 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V + V
VDD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V + V
D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V + V
EE
EE
EE
EE
EE
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . .300°C
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40°C to 85°C
Supply Voltage (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
DD
Electrical Specifications (Standard Settings)
Over the recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC CHARACTERISTICS
V
I
V
I
RGO
I
GATE
V
GATE
V
V
V
I
V
V
DD
RGO
PGA
IHB
ILB
I
LO
IL
IH
Supply Operating Range 10 12 14 V
DD
Supply Current 2.5 5 mA
Regulated 5V output I
V
current output 50 µA
RGO
Gate Pin Current Gate Drive On,
External Gate Drive (Slew Rate Control) I
Power Good Threshold
(PWRGD
High to Low)
= 10µA 4.5 6.0
RGO
46.2 52.5 58.8 µA
V
= VEE,
GATE
V
= V
SENSE
- VEE = 3V
V
GATE
V
SENSE-VEE
= 50µA VDD-1 V
GATE
Referenced to V
V
< V
UV1
(sourcing)
EE
= 0.1V (sinking)
EE
< V
UV/OV
9mA
0.9 1 1.1 V
OV
Voltage Input High (BATT_ON) VEE + 4 VEE + 5 V
Voltage Input Low (BATT_ON) VEE + 2 V
Input Leakage Current (MRH, MRC) VIL = GND to V
LI
Output Leakage Current
(V1GOOD
RESET
(3)
Input LOW Voltage (MRH, MRC, IGQ0, IGQ1) -0.5 + V
(3)
Input HIGH Voltage (MRH, MRC, IGQ0, IGQ1) (VEE + 5) x
, V2GOOD, V3GOOD, V4GOOD,
)
All ENi
= V
CC
for i = 1 to 4 10 µA
RGO
EE
0.7
DD
10 µA
(VEE + 5) x
0.3
(VEE + 5) +
0.5
V
V
V
3
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
Electrical Specifications (Standard Settings)
Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
Output LOW Voltage
OL
(RESET, RESET
V3GOOD
(1)
C
OUT
Output Capacitance
(RESET
, V1GOOD, V2GOOD, V3GOOD,
V4GOOD
(1)
C
IN
V
V
OCI
V
OVR
V
OVH
V
UV1H
V
UV1F
V
UV2H
V
UV2F
V
DRAINF
V
DRAINR
V
TRIP1
V
TRIP2
V
TRIP3
V
TRIP4
OC
Input Capacitance (MRH, MRC) VIN = 0V 6 pF
Over-current threshold VOC = V
Over-current threshold (Insertion) VOC = V
Overvoltage threshold (rising)
Overvoltage hysteresis Referenced to V
Undervoltage 1 hysteresis Referenced to V
Undervoltage 1 threshold (falling) 2.16 2.21 2.26 V
Undervoltage 2 hysteresis Referenced to V
Undervoltage 2 threshold (falling) 1.68 1.73 1.78 V
Drain sense voltage threshold
(falling)
Drain sense voltage threshold
(rising)
EN1 Trip Point Voltage Referenced to V
EN2 Trip Point Voltage Referenced to V
EN3 Trip Point Voltage Referenced to V
EN4 Trip Point Voltage Referenced to V
AC CHARACTERISTICS
t
FOC
t
FUV
t
FOV
t
VFR
t
BATT_ON
t
MRC
t
MRH
t
MRCE
t
MRCD
t
MRHE
t
MRHD
Sense High to Gate Low 1.5 2.5 3.5 µs
Under Voltage conditions to Gate Low 0.5 1.0 1.5 µs
Overvoltage Conditions to Gate Low 1.0 1.5 2 µs
Overvoltage/undervoltage failure recovery time
to Gate =1V.
Delay BATT_ON Valid 100 ns
Minimum time high for reset valid on the MRC
pin
Minimum time high for reset valid on the MRH
pin
Delay from MRC enable to PWRGD HIGH No Load 1.0 1.6 µs
Delay from MRC disable to PWRGD LOW Gate is On, No Load 200 400 µs
Delay from MRH enable to Gate Pin LOW I
Delay from MRH disable to GATE reaching 1V I
, V1GOOD, V2GOOD,
, V4GOOD, FAR, PWRGD)
, FAR)
X80010, X80012
X80011, X80013
I
= 4.0mA
OL
(V
+ 2.7 to VEE + 5.5V)
EE
I
= 2.0mA
OL
(V
+ 2.7 to VEE + 3.6V)
EE
V
= 0V 8 pF
OUT
SENSE
PWRGD = HIGH
SENSE
- V
- V
EE
EE
45 50 55 mV
135 150 165 mV
Initial Power Up condition
Referenced to V
BATT-ON = V
BATT-ON = V
Referenced to V
Referenced to V
EE
EE
EE
EE
EE
RGO
EE
EE
EE
EE
EE
EE
VDD does not drop below 3V, No
3.85
3.49
3.90
3.54
12 18 24 mV
12 18 24 mV
12 18 24 mV
0.9 1 1.1 V
1.2 1.3 1.4 V
2.25 2.5 2.75 V
2.25 2.5 2.75 V
2.25 2.5 2.75 V
2.25 2.5 2.75 V
1.2 1.6 2 µs
other failure conditions.
5 µs
5 µs
= 60µA, No Load 1.0 1.6 2.4 µs
GATE
= 60µA, No Load 1.8 2.6 µs
GATE
V
+ 0.4 V
EE
3.95
3.59
V
4
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
Electrical Specifications (Standard Settings)
Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
RESET_E
t
QC
t
SC_RETRY
t
NF
t
DPOR
t
SPOR
t
DELAY1
t
DELAY2
t
DELAY3
t
DELAY4
t
TO
t
PDHLPG
t
PDLHPG
t
PGHLPG
t
PGLHPG
NOTE:
1. This parameter is based on characterization data.
Delay from PWRGD or ViGOOD to RESET
1 µs
valid LOW
Delay from IGQ1 and IGQ0 to valid Gate pin
1 µs
current
Delay between Retries 85 100 115 ms
Noise Filter for Overcurrent 4.5 5 5.5 µs
Device Delay before Gate assertion 45 50 55 ms
Delay after PWRGD and all ViGOOD signals
are active before RESET
assertion
Power Sequencing Time Delay
85 100 115 ms
85 100 115 ms
TiD1 = 0; TiD0 = 0
ViGOOD turn off time 50 ns
(1)
Delay from Drain good to PWRGD LOW Gate = V
(1)
Delay from Drain fail to PWRGD HIGH Gate = V
(1)
Delay from Gate good to PWRGD LOW Drain = V
(1)
Delay from Gate fail to PWRGD HIGH Drain = V
DD
DD
EE
EE
1 µs
1 µs
1 µs
1 µs
Equivalent A.C. Output Load Circuit
5V
4.6kΩ
,
30pF
RESET
FAR
PWRGD
5V
4.6kΩ
30pF
V1GOOD,
V2GOOD,
V3GOOD
V4GOOD
A.C. Test Conditions
Input pulse levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing levels V
Output load Standard output load
CC
x 0.5
5
FN8149.0
January 13, 2005
V
UV/OV
VDD
X80010, X80011, X80012, X80013
V
TH
t
DPOR
V
OV
V
UV
t
FOV
t
VFR
t
FUV
t
VFR
MRH
SENSE
GATE
VDD
SENSE
GATE
V
OCI
V
OC
1V 1V
FIGURE 1. OVERVOLTAGE/UNDERVOLTAGE GATE TIMING
V
TH
t
DPOR
Always Retry
< V
V
UV
UV/OV < VOV
MRH = HIGH
V
OCI
V
OC
t
t
FOC
t
SC_RETRY
t
FOC
SC_RETRY
FIGURE 2. OVERCURRENT GATE TIMING
VDD
V
TRIPi
ENi
ViGOOD
Initial
Power-up
6
t
TO
t
DELAYi
Enable DC/DC supply
t
TO
i = 1, 2, 3, 4
FIGURE 3. ViGOOD TIMINGS
FN8149.0
January 13, 2005
MRH
t
MRH
X80010, X80011, X80012, X80013
MRC
t
MRC
GATE
t
MRHE
FIGURE 4. MANUAL RESET (HOT SIDE) MRH
V
DRAIN
V
GATE
PWRGD
ENi
V1GOOD
V2GOOD
1V
t
DHLPG
t
GLHPG
t
MRHD
t
DELAY1
t
DELAY2
PWRGD
t
MRCE
FIGURE 5. MANUAL RESET (COLD SIDE) MRC
t
DLHPG
t
GHLPG
t
MRCD
V3GOOD
V4GOOD
RESET
t
DELAY3
t
DELAY4
t
SPOR
FIGURE 6. RESET TIMINGS
PWRGD or
any ENi LOW to HIGH
(1st occurance)
t
RESET_E
7
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
Typical Performance Characteristics
52.000
51.000
50.000
49.000
48.000
47.000
INRUSH CURRENT LIMIT (mV)
46.000
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
FIGURE 7. OVER CURRENT THRESHOLD vs
TEMPERATURE
3.92
3.91
3.90
3.89
3.88
3.87
OV THRESHOLD (V)
3.86
3.85
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
Rising
Falling
FIGURE 9. OVERVOLTAGE THRESHOLD vs TEMPERATURE
1.780
1.770
1.760
1.750
1.740
1.730
1.720
1.710
1.700
1.690
UNDER VOLTAGE 2 THRESHOLD (V)
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
FIGURE 8. UNDERVOLTAGE 2 THRESHOLD vs
TEMPERATURE
2.515
2.510
2.505
2.500
2.495
2.490
2.485
ENi THRESHOLD (V)
2.480
2.475
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
FIGURE 10. ENi
THRESHOLD vs TEMPERATURE
Rising
Falling
2.250
2.240
2.230
2.220
2.210
2.200
UNDER VOLTAGE 1 THRESHOLD (V)
2.190
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
FIGURE 11. UNDERVOLTAGE 1 THRESHOLD vs
TEMPERATURE
8
Rising
Falling
200
160
120
80
GATE CURRENT (µA)
40
0
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
FIGURE 12. I
(SOURCE) vs TEMPERATURE
GATE
150µA
70µA
50µA
10µA
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
Typical Performance Characteristics (Continued)
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
GATE CURRENT - SINK (mA)
7.0
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
(µs)
UV
t
0.800
0.750
0.700
0.650
0.600
0.550
FIGURE 13. I
(SINK) vs TEMPERATURE
GATE
tUV2
tUV1
2.5
2.4
2.3
2.2
(µs)
2.1
OC
t
2.0
1.9
1.8
1.7
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
FIGURE 14. T
1.02
1.00
0.98
0.96
(NORMALIZED)
0.94
DELAY
t
0.92
vs TEMPERATURE
FOC
0.500
-55-40-25-105 203550658095110125
TEMPERATURE
FIGURE 15. t
1.4
1.4
1.3
1.3
(µs)
1.2
OV
t
1.2
1.1
1.1
1.0
-55-40-25-105 203550658095110125
FIGURE 17. t
vs TEMPERATURE
FUV
TEMPERATURE
vs TEMPERATURE
FOV
0.90
-55 -35 -15 5 25 45 65 85
TEMPERATURE
FIGURE 16. t
vs TEMPERATURE
DELAYi
9
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
Typical Performance Characteristics (Continued)
52.000
51.000
50.000
49.000
48.000
47.000
INRUSH CURRENT LIMIT (mV)
46.000
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
FIGURE 18. OVER CURRENT THRESHOLD vs TEMPERATURE
3.92
3.91
3.90
3.89
3.88
3.87
OV THRESHOLD (V)
3.86
3.85
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
Rising
Falling
1.780
1.770
1.760
1.750
1.740
1.730
1.720
1.710
1.700
UNDER VOLTAGE 2 THRESHOLD (V)
1.690
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
FIGURE 19. UNDERVOLTAGE 2 THRESHOLD vs
TEMPERATURE
2.515
2.510
2.505
2.500
2.495
2.490
2.485
ENi THRESHOLD (V)
2.480
2.475
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
Rising
Falling
FIGURE 20. OVERVOLTAGE THRESHOLD vs TEMPERATURE
2.250
2.240
2.230
2.220
2.210
2.200
UNDER VOLTAGE 1 THRESHOLD (V)
2.190
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
Rising
Falling
FIGURE 22. UNDERVOLTAGE 1 THRESHOLD vs
TEMPERATURE
10
FIGURE 21. ENi
200
160
120
80
GATE CURRENT (µA)
40
0
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
FIGURE 23. I
THRESHOLD vs TEMPERATURE
150µA
70µA
50µA
10µA
TEMPERATURE
(SOURCE) vs TEMPERATURE
GATE
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
Typical Performance Characteristics (Continued)
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
GATE CURRENT - SINK (mA)
7.0
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
(µs)
t
0.800
0.750
0.700
0.650
UV
0.600
0.550
FIGURE 24. I
(SINK) vs TEMPERATURE
GATE
tUV2
tUV1
2.5
2.4
2.3
2.2
(µs)
2.1
OC
t
2.0
1.9
1.8
1.7
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
FIGURE 25. t
1.02
1.00
0.98
0.96
(NORMALIZED)
0.94
DELAY
t
0.92
vs TEMPERATURE
FOC
0.500
-55-40-25-105 203550658095110125
TEMPERATURE
FIGURE 26. t
1.4
1.4
1.3
1.3
(µs)
1.2
OV
t
1.2
1.1
1.1
1.0
-55-40-25-105 203550658095110125
FIGURE 28. t
vs TEMPERATURE
FUV
TEMPERATURE
vs TEMPERATURE
FOV
0.90
-55 -35 -15 5 25 45 65 85
TEMPERATURE
FIGURE 27. t
vs TEMPERATURE
DELAYi
11
FN8149.0
January 13, 2005
V
UV/OV
BATT-ON
DRAIN
GATE
X80010, X80011, X80012, X80013
PWRGD
V
Ref
OV
V
Ref
UV1
V
Ref
UV2
V
V
EE
1V Ref
RGO
2:1
MUX
50µA
V
DD
Power Good
Logic
Over current
logic, Hard short
relay, Retry logic
status and delay
V
EE
FAR
V
EE
V
DD
IGQ1
IGQ0
SENSE
V
EE
MRH
MRC
EN1
EN2
EN3
EN4
Slew Rate
Selection
Gate
Control
POR
5V reg.
V
RGO
RESET
V
EE
3R
V
EE
VOC REF
V
RGO
38R
OSC
Divider
Reset
4
repeated 4 times
4
Select
0.1s
0.5s
1s
5s
delay1
delay2
delay3
delay4
Delay circuit
Reset Logic
and Delay
Sequence
and Timing
Control logic
V
EE
V
EE
V1GOOD
V2GOOD
V3GOOD
V4GOOD
12
FIGURE 29. BLOCK DIAGRAM
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
Pin Configuration
X80010, X80011, X80012, X80013
32-lead QFN Quad Package
EE
GQ0
GQ1
I
MRH
I
32
V
RGO
NA1
V4GOOD
EN4
V3GOOD
EN3 EN1
V2GOOD
EN2
1
2
3
4
(7mm x 7mm)
5
6
7
817
910111213 14
EE
DD
V
V
UV/OV
V
FAR
NC
GATE
V
262728293031
25
15
16
NA1
NA1
DRAIN
NC
24
MRC
23
NA1
22
RESET
21
20
V1GOOD
19
NA2
18
NA2
BATT-ON
PWRGD
SENSE
Pin Descriptions
PIN NAME DESCRIPTION
1V
RGO
2NA1Not Available. Do not connect to this pin.
3 V4GOOD
4EN4V4 Voltage Enable Input. Fourth voltage enable pin. If unused connect to V
5 V3GOOD
6EN3V3 Voltage Enable Input. Third voltage enable pin. If unused connect to V
7 V2GOOD
8EN2
9V
DD
10 V
11 V
UV/OV
12 SENSE Circuit Breaker Sense Input. This input pin detects the overcurrent condition.
13 GATE Gate Drive Output. Gate drive output for the external N-channel MOSFET.
14 DRAIN Drain. Drain sense input of the external N-channel MOSFET.
15 NA1 Not Available. Do not connect to this pin.
16 NA1 Not Available. Do not connect to this pin.
17 NA2 Not Available. Connect to V
18 NA2 Not Available. Connect to V
19 EN1
20 V1GOOD
Regulated 5V output. Used to pull-up
user programmable inputs IGQ0, IGQ1, BATT-ON (if needed).
V4 Voltage Good Output. This open drain output goes LOW when EN4 is less than V
greater than V
. There is a user selectable delay circuitry on this pin.
TRIP4
V3 Voltage Good Output (Active Low). This open drain output goes LOW when EN3 is less than V
when EN3
is greater than V
. There is a user selectable delay circuitry on this pin.
TRIP3
V2 Voltage Good Output (Active Low). This open drain output goes LOW when EN2 is less than V
when EN2
is greater than V
. There is a user selectable delay circuitry on this pin.
TRIP2
V2 Voltage Enable Input. Second voltage enable pin. If unused connect to V
Positive Supply Voltage Input.
Negative Supply Voltage Input.
EE
Analog Undervoltage and Overvoltage Input. Turns off the external N-channel MOSFET when there is an undervoltage or
overvoltage condition.
.
RGO
.
RGO
V1 Voltage Enable Input. First voltage enable pin. If unused connect to V
V1 Voltage Good Output (Active Low).This open drain output goes LOW when EN1 is less than V
when EN1
is greater than V
. There is a user selectable delay circuitry on this pin.
TRIP1
RGO
RGO
RGO
.
RGO
.
and goes HIGH when EN4 is
TRIP4
.
and goes HIGH
TRIP3
and goes HIGH
TRIP2
.
and goes HIGH
TRIP1
13
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
Pin Descriptions (Continued)
PIN NAME DESCRIPTION
21 RESET RESET Output. This open drain pin is an active LOW output. This pin will be active until PWRGD goes active and the power
22 NA1 Not Available. Do not connect to this pin.
23 MRC Manual Reset Input Cold-side. Pulling the MRC pin HIGH initiates a system side RESET. The MRC signal must be held HIGH
24 NC No Connect. No internal connections.
25 V
26 NC No Connect. No internal connections.
27 FAR
28 BATT-ON Battery On Input. This input signals that the battery backup (or secondary supply) is supplying power to the backplane. It has
29 PWRGD
30 IGQ1 Gate Current Quick Select Bit 1 Input. This pin is used to change the gate current drive and is intended to allow for current
31 IGQ0 Gate Current Quick Select Bit 0 Input. This pin is used to change the gate current drive and is intended to allow for current
32 MRH
sequencing is complete. This pin will be released after a programmable delay.
for 5µs. It has an internal pulldown resistor. (>10mΩ typical)
Negative Supply Voltage Input.
EE
Failure After Re-try (FAR) output signal. Failure After Re-try (FAR) is asserted after a number of retries. Used for Overcurrent
and hardshort detection.
an internal pulldown resistor. (>10mΩ typical)
Power Good Output. This output pin enables a power module.
ramp rate control of the gate pin of an external FET. It has an internal pulldown resistor. (>10mΩ typical)
ramp rate control of the gate pin of an external FET. It has an internal pulldown resistor. (>10mΩ typical)
Manual Reset Input Hot-side. Pulling the MRH pin LOW initiates a GATE pin reset (GATE pin pulled LOW). The MRH signal
must be held LOW for 5µs (minimum).
Functional Description
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
bypass capacitors at the input of the board’s power module
or DC/DC converter can draw huge transient currents as
they charge up (See Figure 30). This transient current can
cause permanent damage to the board’s components and
cause transients on the system power supply.
-48V
Return
R4
182K
1%
R5
30k
-48V
1%
R6
10K
1%
V
UV/OV
V
DD
V
EE
0.02Ω
I
inrush
UV=37V
OV=71V
SENSE
Rs
5%
0.1µF
Q1
X80010
X80011
X80012
X80013
GATE
100
IRFR120
4.7k
3.3n
DRAIN
100K
FIGURE 30. TYPICAL -48V HOTSWAP APPLICATION CIRCUIT
The X80010 is designed to turn on a board’s supply voltage
in a controlled manner (see Figure 31), allowing the board to
be safely inserted or removed from a live backplane. The
device also provides undervoltage, overvoltage and
overcurrent protection while keeping the power module
DC/DC
Converter
DC/DC
Converter
-48V
(DC/DC converter) off until the backplane input voltage is
stable and within tolerance.
FIGURE 31. TYPICAL INRUSH WITH GATE SLEW RATE
CONTROL
Overvoltage and Undervoltage Shutdown
The X80010 provides overvoltage and undervoltage
protection circuits. When an overvoltage (V
undervoltage (V
UV1
and V
) condition is detected, the
UV2
GATE pin immediately pulls low. The undervoltage threshold
V
applies to the normal operation with a mains supply.
UV1
The undervoltage threshold V
assumes the system is
UV2
powered by a battery. When using a battery backup, the
OV
) or
14
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
BATT-ON pin is pulled to V
. The default thresholds have
RGO
been set so the external resistance values in Figure 30
provide an overvoltage threshold of 74.9V (X80010/X80012)
or 68V (X80011/X80013), a main undervoltage threshold of
43V and a battery undervoltage threshold of 33.8V.
As shown in Figure 34, this circuit block contains
comparators and voltage references to monitor for a single
overvoltage and dual undervoltage trip points. The
overvoltage and undervoltage trip points as shown in Table 1.
TABLE 1. OVERVOLTAGE/UNDERVOLTAGE DEFAULT
SYMBOL DESCRIPTION FALLING RISING
V
OV
V
OV
V
UV1
V
UV2
Notes: 1: Max/Min Voltage is the maximum and minimum operat-
THRESHOLDS
THRESHOLD
Overvoltage
MAX/MIN
VO LTAGE
3.87V 3.9V 74.3 74.9
LOCKOUT
1
VOLTAGE
(X80010/12)
Overvoltage
3.51V 3.54V 67.4 68
(X80011/13)
Undervoltage 1 2.21V 2.24V 43.0 42.4
Undervoltage 2 1.73V 1.76V 33.8 33.2
ing voltage assuming the recommended V
tor divider.
UV/OV
resis-
2: Lockout voltage is the voltage where the X8001x turns
off the FET.
A resistor divider connected between the plus and minus
input voltages and the V
pin (see Figure 32)
UV/OV
determines the overvoltage and undervoltage shutdown
voltages and the operating voltage range. Using the
thresholds in Table and the equations of Figure 32 the
desired operating voltage can be determined. Figure 33
shows the resistance values for various operating voltages
(X80010 and X80012).
100
90
80
V
OV
70
60
50
40
30
20
10
OPERATING VOLTAGE (V)
0
150
V
V
UV1
UV2
158
BATT-ON = V
166
175
R1 in kΩ (for R2=10K)
182
EE
190
Operating
Voltage
BATT-ON = V
198
206
214
RGO
222
FIGURE 33. OPERATING VOLTAGe vs RESISTOR RATIO
2
Battery Back Up Operations
An external signal, BATT_ON is provided to switch the
undervoltage trip point. The BATT_ON signal is a LOGIC
HIGH if V
+ 2V. The time from a BATT_ON input change to a valid new
undervoltage threshold is 100ns. See Electrical
Specifications for more details.
Note: The V
5.5V in worst case conditions. Values for R1 and R2 must be
chosen such that this condition is met. Intersil recommends
R1 = 182kΩ and R2 = 10kΩ to conform to factory settings.
TABLE 2. SELECTING BETWEEN UNDERVOLTAGE TRIP
PIN DESCRIPTION TRIP POINT SELECTION
BATT_ON Undervoltage Trip
V
UV1
> VEE + 4V and is a LOGIC LOW if V
IHB
pin must be limited to less than VEE +
UV/OV
POINTS
If BATT_ON = 0,
V
UV1
If BATT_ON = 1,
V
UV2
and V
Point
Selection Pin
are undervoltage thresholds.
UV2
ILB
trip point is selected;
trip point is selected.
< V
EE
V
P
R1
R2
V
UV/OV
V
S
V
N
Voltage divider:
UV OV⁄
=
V
or:
V
=
SVUV OV⁄
R2
----------------------
V
S
R1 R2+
R1 R2+
----------------------
R2
FIGURE 32. OVERVOLTAGE UNDERVOLTAGE DIVIDER
15
R1
182K
V
UV/OV
R2
10K
-48V
BATT_ON
+
V
OV
Voltage
Reference
+
V
UV1
Voltage
Reference
+
V
UV2
Voltage
Reference
2:1
Mux
To Gate
Control
To Gate
Control
FIGURE 34. OVERVOLTAGE UNDERVOLTAGE FOR PRIMARY
AND BATTERY BACKUP
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
Overcurrent Protection (Circuit Breaker Function)
The X80010 over-current circuit provides the following
functions:
- Over-current shut-down of the power FET and external
power good indicators.
- Noise filtering of the current monitor input.
- Relaxed over-current limits for initial board insertion.
- Over-current recovery retry operation.
A sense resistor, placed in the supply path between VEE and
SENSE (see Figure 30) generates a voltage internal to the
X80010. When this voltage exceeds 50mV an over current
condition exists and an internal “circuit breaker” trips, turning
off the gate drive to the external FET. The actual overcurrent level is dependent on the value of the current sense
resistor. For example a 20mΩ sense resistor sets the overcurrent level to 2.5A.
Intersil’s X80010 provides a safety mechanism during
insertion of the board into the back plane. During insertion of
the board into the backplane large currents may be induced.
In order to prevent premature shut down, the overcurrent
detect circuit of the X80010 allows up to 3 times the standard
overcurrent setting during insertion.
After the PWRGD
signal is asserted, the X80010 switches
back to the normal overcurrent setting. The over-current
threshold voltage during insertion is 150mV.
After the Power FET turns off due to an over-current
condition, a retry circuit turns the FET back on after a delay
of 100ms. If the over-current condition remains, the FET
again turns off. For the X80010 and X80012, this sequence
repeats indefinitely until the over-current condition is
released. For the X80011 and X80013, the X80010 retries
five times, then, sets an output signal, FAR
, to indicate a
failure after retry.
Over-current shut-down
As shown in Figure 35, this circuit block contains a resistor
divider, a comparator, a noise filter and a voltage reference
to monitor for over-current conditions.
Voltage
Reference
38R
–
3R
-48V
FIGURE 35. OVERCURRENT DETECTION/SHORT CIRCUIT
R
Overcurrent Event
PROTECTION
Sense
+
noise
filtering
5µs
The overcurrent voltage threshold (V
Gate
Control
ock
Bl
Overcurrent/
Short-Circuit
Retry Logic
RETRY
Delay
) is 50mV. This can
OC
be factory set, by special order, to any setting between
30mV and 100mV. V
and V
pins and across the R
EE
is the voltage between the SENSE
OC
SENSE
resistor. If the
selected sense resistor is 20mW, then 50mV corresponds to
an overcurrent of 2.5A.
If an over-current condition is detected, the GATE is turned
off and all power good indicators go inactive.
Overcurrent Noise Filter
The X80010 has a noise (low pass) filter built into the overcurrent comparator. The comparator will thus require the
current spikes to exceed the overcurrent limit for more than
5µs.
Overcurrent During Insertion
Insertion is defined as the first plug-in of the board to the
backplane. In this case, the X80010 is initially fully powered
off prior to the hot plug connection to the mains supply. This
condition is different from a situation where the mains supply
has temporarily failed resulting in a partial recycle of the
power. This second condition will be referred to as a power
cycle.
16
During insertion, the board can experience high levels of
current for short periods of time as power supply capacitors
charge up on the power bus. To prevent the over-current
sensor from turning off the FET inadvertently, the X80010
has the ability to allow more current to flow through the
powerFET and the sense resistor for a short period of time
until the FET turns on and the PWRGD
signal goes active. In
the X80010, 150mV is allowed across sense resistor the
during insertion (10A assuming a 20mΩ resistor). This
provides a mechanism to reduce insertion issues associated
with huge current surges.
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
Hardshort Protection - FET Turn-on Retry
In the event on an over-current or hard short condition, the
X80010 includes a retry circuit. This circuit waits for 100ms,
then attempts to again turn on the FET. If the fault condition
still exists, the FET turns off and the sequence repeats. For
the X80010 and X80012, this process continues indefinitely
until the overcurrent condition does not exist. For the X80011
and X80013, this process repeats five times, only then will
keep the FET off and set the FAR
pin active. After FAR is
asserted, it can be cleared using the master reset pin, MRH
(upon MRH
the power on V
assertion the FAR output is cleared) or cycling
.
DD
If an overcurrent condition does not occur on any retry, the
gate pin proceeds to open at the user defined slew rate.
Gate Drive Output Slew Rate (Inrush Current)
Control
The gate output drives an external N-Channel FET. The
GATE pin goes high when no overcurrent, undervoltage or
overvoltage conditions exist.
The X80010 provides an I
on-chip slew rate control to minimize inrush current. This
I
current limits the inrush current and provides the best
GATE
charge time for a given load, while avoiding overcurrent
conditions.
For applications that require different ramp rates during
insertion and start-up and operations modes, the X80010
provides two external pins, IGQ1 and IGQ0, that allow the
user to switch to different GATE currents on-the-fly by
selecting one of four pre-selected I
IGQ0 and IGQ1 are left unconnected, the gate current is
50µA. The other three settings are 10µA, 70µA and 150µA
(See Figure 36). Typically, the delay from IGQ1 and IGQ0
selection to a change in the GATE pin current is less than
1µs.
I
=
150µA
GATE
70µA
50µA
10µA
Inrush Current
current of 50µA to provide
GATE
currents. When
GATE
overcurrent
I
GATE
For applications that require different ramp rates during
insertion and operation or for applications where a different
gate current is desired, the X80010 provides two external
pins, IGQ1 and IGQ0, that allow the system to switch to a
different GATE current with pre-selected options.
The IGQ1 and IGQ0 pins can be used to select from one of
four set values.
IGQ1
IGQ0
PIN
PIN CONTENTS
0 0 Defaults to gate current 50µA
0 1 Gate Current is 10µA
1 0 Gate Current is 70µA
1 1 Gate Current is 150µA
Typically, the delay from IGQ1 and IGQ0 selection to a
change in the GATE pin current is less than 1µs.
Gate Current
I
INRUSH
Quick Select
Logic
Control
Registers
C2
3.3nF
100K
V
=12V
DD
Slew
100*
Selection
Logic
DRAIN
R2
22K
Rate
10µA
50µA
70µA
150µA
SENSEV
EE
-48V
R
SENSE
FIGURE 37. SLEW RATE (INRUSH CURRENT) CONTROL
GATE
100nF*
* Optional Components
See Section “Gate Capacitor, Filtering and Feedback”
IGQ1
IGQ0
LOAD
Gate Capacitor, Filtering and Feedback
In Figure 37, the FET control circuit includes an FET
feedback capacitor C
FET during turn on. The capacitor value depends on the
load, the FET gate current, and the maximum desired inrush
current.
, which provides compensation for the
2
T1
FIGURE 36. SELECTING I
CONTROL ON THE GATE PIN
T2 T3
Time, ms
CURRENT FOR SLEW RATE
GATE
T4
T5
Slew Rate (Gate) Control
As shown in Figure 37, this circuit block contains a current
source (I
pin. This current provides a controlled slew rate for the FET.
) that drives the 50µA current into the GATE
GATE
17
The value of C2 can be selected with the following formula.
C2
I
-------------------------------------------=
GATE
I
C×
LOAD
INRUSH
Where:
I
= FET Gate current
GATE
I
INRUSH
C
= Maximum desired inrush current
= DC/DC bulk capacitance
LOAD
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
With the X80010, there is some control of the gate current
with the IGQ pins, so one selection of C2 can cover a wide
range of possible loading conditions. Typical values for C2
range from 2.2 to 4.7nF.
When power is applied to the system, the FET tries to turn
on due to its internal gate to drain capacitance (Cgd) and the
feedback capacitor C2 (see Figure 37.) The X80010 device,
when powered, pulls the gate output low to prevent the gate
voltage from rising and keep the FET from turning on.
However, unless V
powers up very quickly, there will be a
DD
brief period of time during initial application of power when
the X80010 circuits cannot hold the gate low. The use of an
external capacitor (C1) prevents this. Capacitors C1 and C2
form a voltage divider to prevent the gate voltage from rising
above the FET turn on threshold before the X80010 can hold
the gate low. Use the following formula for choosing C1.
V1 V2–
C1
--------------------- C 2=
V2
Where:
V1 = Maximum input voltage,
V2 = FET threshold voltage,
C1 = Gate capacitor,
C2 = Feedback capacitor.
In a system where V
rises very fast, a smaller value of C1
DD
may suffice as the X80010 will control voltage at the gate
before the voltage can rise to the FET turn on threshold. The
circuit of Figure 37 assumes that the input voltage can rise to
80V before the X80010 sees operational voltage on V
DD
. If
C1 is used then the series resistor R1 will be required to
prevent high frequency oscillations.
Drain Sense and Power Good Indicator
The X80010 provides a drain sense and power good
indicator circuit. The PWRGD
there is no overvoltage, no undervoltage, and no overcurrent
condition, the Gate voltage exceeds VDD-1V, and the
voltage at the DRAIN pin is less V
As shown in Figure 38, this circuit block contains a drain
sense voltage trip point (∆V
point (∆V
), two comparators, and internal voltage
GATE
references. These provide both a drain sense and a gate
sense circuit to determine the whether the FET has turned
on as requested. If so, the power good indicator (PWRGD
goes active.
signal asserts LOW when
EE+VDRAIN
) and a gate voltage trip
DRAIN
.
)
The PWRGD
signal asserts (Logic LOW) only when all of the
below conditions are true:
- there is no overvoltage or no undervoltage condition,
(i.e. undervoltage < V
- There is no overcurrent condition (i.e. V
< overvoltage.)
EE
EE
- V
SENSE
<
VOC.)
- The FET is turned on (i.e. V
V
> VDD - 1V).
GATE
∆V
DRAIN
–
+
1V
(Factory
Programmable)
∆V
GATE
–
+
VDD-1V
SENSEV
EE
-48V
R
SENSE
FIGURE 38. DRAIN SENSE AND POWER GOOD INDICATOR
GATE
DRAIN
100K
< VEE + 1V and
DRAIN
Power
Good
Logic
Control/Status
Registers
LOAD
PWRGD
V
EE
Power On/System Reset and Delay
Application of power to the X80010 activates a Power On
Reset circuit that pulls the RESET
used, provides several benefits.
- It prevents the system microprocessor from starting to
operate with insufficient voltage.
- It prevents the processor from operating prior to
stabilization of the oscillator.
- It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
The POR/RESET circuit is activated when all voltages are
within specified ranges and the following time-out conditions
are met: PWRGD
V4GOOD
. The POR/RESET circuit will then wait 100ms and
assert the RESET
and V1GOOD, V2GOOD, V3GOOD, and
pin.
pin active. This signal, if
The drain sense circuit checks the DRAIN pin. If the voltage
on this pin is greater that 1V above V
, then a fault
EE
condition exists.
The gate sense circuit checks the GATE pin. If the voltage
on this pin is less than V
- 1V, then a fault condition exists.
EE
18
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
Drain Sense
& Power
Good Logic
Enable
Logic
ViGOOD
i = 1 to 4
PWRGD
SPOR
V
DD
RESET
µP
RESET Logic
t
Delay
SPOR
Control
Registers
V
EE
MRC
FIGURE 39. POWER ON/SYSTEM RESET AND DELAY
Quad Voltage Monitoring
X80010 monitors 4 voltage enable inputs. When the ENi
(i=1-4) input is detected to be below the input threshold, the
output ViGOOD
signal is asserted after a delay of 100ms. The ViGOOD
signal remains active until ENi
(i = 1 to 4) goes active LOW. The ViGOOD
rises above threshold.
Once the PWRGD
of the DC/DC modules can commence. RESET
100ms after all ViGOOD
signal is asserted, the power sequencing
goes active
(i=1 to 4) outputs are asserted (See
Figure 39).
As shown in Figure 40, this circuit block contains four
separate voltage enable pins, a time delay circuit, and an
output driver.
EN1
EN2
EN3
EN4
V
RGO
OSC
Divider
Reset
4
repeated 4 times
4
Select
0.1s
0.5s
1s
5s
delay1
delay2
delay3
delay4
Delay circuit
Control Register
V
EE
FIGURE 40. VOLTAGE MONITORS AND VGOOD OUTPUTS
V1GOOD
V2GOOD
V3GOOD
V4GOOD
19
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
Manual Reset (Hot Side and Cold Side)
The manual reset option allows a hardware reset of either
the Gate control or the PWRGD
used to recover the system in the event of an abnormal
operating condition.The X80010 has two manual reset pins:
MRH
(manual reset hot side) and MRC (manual reset cold
side). The MRH
signal is used as a manual reset for the
GATE pin. This pin is used to initiate Soft Reinsert. When
MRH
is pulled LOW the GATE pin will be pulled LOW. It also
clears the FAR
signal. When the MRH pin goes HIGH, it
removes the override signal and the gate will turn on based
on the selected gate control mechanism.
TABLE 3. MANUAL RESET OF THE HOT SIDE (GATE SIGNAL)
MRH GATE PIN REQUIREMENTS
1 Operational When MRH
(Hot) function is disabled
0OFFMRH
indicator. These can be
is HIGH the Manual Reset
must be held LOW minimum of 5µs
The MRC signal is used as a manual reset for the PWRGD
signal. This pin is used to initiate a Soft Restart. When the
MRC is pulled HIGH, the PWRGD
When MRC pin goes LOW, the PWRGD
signal is pulled HIGH.
pin goes
operational. It will go LOW if all constraints on the GATE are
within limits.
TABLE 4. MANUAL RESET OF THE COLD SIDE (PWRGD
SIGNAL)
MRC PWRGD REQUIREMENTS
1 HIGH MRC must be held HIGH minimum of 5µs
0 Operational When MRC is LOW the MRC
function is disabled
Flexible Power Sequencing of Multiple Power
Supplies
The X80010 provides several circuits such as multiple
voltage enable pins, programmable delays, and a power
good signals can be used to set up flexible power
sequencing schemes for downstream DC/DC supplies.
Below are examples of parallel and relay sequencing.
1. Power Up of DC/DC Supplies In Parallel Sequencing
Using Programmable Delays on Power Good (See Figure
41 and Figure 42).
Several DC/DC power supplies and their respective
power up start times can be controlled using the X80010
such that each of the DC/DC power supplies will start up
following the issue of the PWRGD
signal is fed into the ENi
PWRGD
ViGOOD
control the ON
is valid, the internal voltage enable circuits issue
signals after a time delay. The ViGOOD signals
/OFF pins of the DC/DC supplies. Each
inputs to the X80010. When
signal. The PWRGD
DC/DC converter is instructed to turn on 100ms after the
PWRGD goes active. However, each ViGOOD delay can
be increased with the use of external R-C circuits.
20
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
-48V
Return
GND
GND
R5
30k
1%
-48V
R4
182k
1%
R6
10k
1%
V
UV/OV
OV=71V
V
DD
V
EE
0.02
C3
0.1µF
100V
C6
0.1µF
100V
MRH
UV=37V
Rs
Ω
5%
+
+
SENSE
0.1µF
Q1
IRFR120
C4
100µF
100V
C7
100µF
100V
X80010, X80011,
X80013, X80014
100
1
4
1
4
GATE
4.7K
V
V
V
V
3.3n
IN+
IN-
IN+
IN-
ON/OFF
V
SENSE+
SENSE-
ON/OFF
V
SENSE+
SENSE-
DRAIN
OUT
TRIM
V
OUT
TRIM
V
OUT
OUT
MRC
100K
+
+
RESET
9
8
7
6
5
9
8
7
6
5
V4GOOD
V3GOOD
V2GOOD
V1GOOD
PWRGD
OPTO
COUPLER
RESET ‘
C5
+
100µF
16V
C8
+
100µF
16V
EN4
EN3
EN2
EN1
OPTO
COUPLER
3.3V
2.5V
PWRGD
RESET
V
CC1
V
CC2
µC
V
CC1
V
CC2
FPGA
GND
GND
C9
0.1µF
100V
C12
0.1µF
100V
ON/OFF
1
V
IN+
V
V
V
SENSE+
IN-
ON/OFF
IN+
IN-
C10
+
100µF
100V
4
1
C13
+
100µF
100V
4
V
OUT
TRIM
SENSE-
V
OUT
V
OUT
SENSE+
TRIM
SENSE-
V
OUT
9
+
8
7
6
+
C11
100µF
16V
5
9
+
8
7
6
+
C14
100µF
16V
5
1.8V
1.2V
FIGURE 41. TYPICAL APPLICATION OF HOTSWAP AND DC/DC PARALLEL POWER SEQUENCING
21
V
CC1
V
CC2
ASIC
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
EN1
(from PWRGD)
t
V1GDO
Power Supply
#1 OUTPUT
(3.3V)
EN2
(from PWRGD)
t
DELAY2
V2GDO
Power Supply
#2 OUTPUT
(2.5V)
EN3
(from PWRGD
t
DELAY3
V3GDO
Power Supply
#3 OUTPUT
(1.8V)
Main FET
turns ON
DELAY1
)
100ms
100ms
100ms
Power Supply
#1 turns ON
Power Supply
#2 turns ON
Power Supply
#3 turns ON
the X80010 EN1
input to sequence the next supply. An
opto-coupler is recommended in this connection for
isolation. This configuration ensures that each
subsequent DC/DC supply will power up after the
preceding DC/DC supply voltage output is valid.
EN4
(from PWRGD
V4GDO
Power Supply
#4 OUTPUT
(1.2V)
RESET
t
DELAY4
t
SPOR
)
100ms
Power Supply
#4 turns ON
100ms
All ViGOOD=LOW
FIGURE 42. PARALLEL SEQUENCING OF DC/DC SUPPLIES.
(TIMING)
1. Power Up of DC/DC Supplies Via Relay Sequencing
Using Power Good and Voltage Monitors (see Figure 43
and Figure 44).
Several DC/DC power supplies and their respective
power up start times can be controlled using the X80010
such that each of the DC/DC power supplies will start in
a relay sequencing fashion. The 1st DC/DC supply will
power up when PWRGD
is LOW after a 100ms delay.
Subsequent DC/DC supplies will power up after the prior
supply has reached its operating voltage. One way to do
this is by using an external CPU Supervisor (for example
the Intersil X40430) to monitor the DC/DC output. When
the DC/DC voltage is good, the supervisor output signals
22
FN8149.0
January 13, 2005
X80010, X80011, X80012, X80013
-48V
Return
R5
30k
1%
-48V
GND
GND
R4
182k
1%
R6
10k
1%
V
UV/OV
V
DD
V
0.02Ω
0.1µF
100V
0.1µF
100V
UV=37V
OV=71V
EE
Rs
5%
C3
C6
MRH
SENSE
+
+
X80010, X80011,
X80012, X80013
0.1µF
100
Q1
IRFR120
1
C4
100µF
100V
4
1
C7
100µF
100V
4
GATE
4.7K
V
IN+
V
V
IN+
V
3.3n
ON/OFF
IN-
ON/OFF
IN-
DRAIN
100K
V
OUT
SENSE+
TRIM
SENSE-
V
OUT
V
OUT
SENSE+
TRIM
SENSE-
V
OUT
MRC
+
+
RESET
OPTO
COUPLER
9
8
7
6
5
9
8
7
6
5
V4GOOD
V3GOOD
V2GOOD
V1GOOD
PWRGD
C5
+
100µF
16V
C8
+
100µF
16V
EN4
EN3
EN2
EN1
OPTO
COUPLER
3.3V
2.5V
OPTO
COUPLER
VFAIL<1:3>
X40430
VMON<1:3>
PWRGD
RESET
RESET
V
CC1
V
CC2
µC
V
CC1
V
CC2
FPGA
GND
GND
C9
0.1µF
100V
C12
0.1µF
100V
ON/OFF
1
V
IN+
V
V
V
SENSE+
IN-
ON/OFF
IN+
IN-
C10
+
100µF
100V
4
1
C13
+
100µF
100V
4
V
OUT
TRIM
SENSE-
V
OUT
V
OUT
SENSE+
TRIM
SENSE-
V
OUT
9
+
8
7
6
+
C11
100µF
16V
5
9
+
8
7
6
+
C14
100µF
16V
5
1.8V
1.2V
FIGURE 43. TYPICAL APPLICATION OF HOTSWAP AND DC/DC RELAY SEQUENCING
23
V
CC1
V
CC2
ASIC
FN8149.0
January 13, 2005
EN2 In
(from PWRGD)
t
V1GDO
Power Supply
#1 OUTPUT
(3.3V)
EN2
V2GDO
Power Supply
#2 OUTPUT
(2.5V)
EN3
FET
turns ON
DELAY1
100ms
t
DELAY2
X80010, X80011, X80012, X80013
Power Supply
#1 turns ON
V2MON
threshold
100ms
Power Supply
#2 turns ON
V3MON
threshold
V3GDO
Power Supply
#3 OUTPUT
(1.8V)
EN4
V4GDO
Power Supply
#4 OUTPUT
(1.2V)
RESET
t
DELAY3
100ms
t
DELAY4
Power Supply
#3 turns ON
V4MON
threshold
100ms
t
RESET
FIGURE 44. RELAY SEQUENCING OF DC/DC SUPPLIES. (TIMING)
Power Supply
#4 turns ON
100ms
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
24
FN8149.0
January 13, 2005
Packaging Information
0.007 (0.19)
0.009 (0.25)
0.000 (0.00)
0.002 (0.05)
X80010, X80011, X80012, X80013
32-Lead Very Very Thin Quad Flat No Lead Package
7mm x 7mm Body with 0.65mm Lead Pitch
0.009 (0.23)
0.015 (0.38)
0.185
(4.70)
0.271 (6.90)
0.279 (7.10)
0.027 (0.70)
0.031 (0.80)
0.000 (0.00)
0.030 (0.76)
0.271 (6.90)
0.279 (7.10)
PIN 1 INDENT
0.185
(4.70)
(4.70)
0.014 (0.35)
0.029 (0.75)
25
0.271 (6.90)
0.279 (7.10)
FN8149.0
January 13, 2005
Loading...