intersil X80000, X80001 DATA SHEET

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®

X80000, X80001

Data Sheet March 18, 2005

Smart Power Plug™ Penta-Power
Sequence Controller with Hot Swap

The X80000 contains three major functions: a power
communications controller, a power sequencing controller,
and a hotswap controller.

The power communications controller allows smart power
supply control via the backplane using the SMBus protocol.
The system can check for voltage, current, and
manufacturing ID compliance before board insertion. The
power distribution network can monitor the status of the
negative voltage supply, DC voltage supplies, and hardshort
events by accessing the Fault Detection Register and
General Purpose EEPROM of the device. Each device has a
unique slave address for identification.

The power sequencer controller time sequences up to five
DC-DC modules. The X80000 allows for various hardwired
configurations, either parallel or relay sequencing modes.
The power good, enable and voltage good signals provide
for flexible DC-DC timing configurations. Each voltage
enable signal has a programmable delay. In addition, the
voltage good signals can be monitored remotely via the fault
detection register (thru the SMBus).

The hot swap controller allows a board to be safely inserted
and removed from a live backplane without turning off the
main power supply. The X80000 family of devices offers a
modular, power distribution approach by providing flexibility
to solve the hotswap and power sequencing issues for
insertion, operations, and extraction. Hardshort Detection
and Retry with Delay, Noise filtering, Insertion Overcurrent
Bypass, and Gate Current selection are some of the
programmable features of the device.

During insertion, the gate of an external power MOSFET is
clamped low to suppress contact bounce. The
undervoltage/overvoltage circuits and the power on reset
circuitry suppress the gate turn on until the mechanical
bounce has ended. The X80000 turns on the gate with a
user set slew rate to limit the inrush current and incorporates
an electronic circuit breaker set by a sense resistor. After the
load is successfully charged, the PWRGD signal is asserted;
indicating that the device is ready to power sequence the
DC-DC power bricks.

FN8148.0

Features

• Integrates Three Major Functions

- Smart Power Plug communications

- Programmable power sequencing

- Programmable Hot Swap controller

• Smart Power Plug™

- Intelligent board insertion allows verification of board
and power supply resources prior to system insertion.

- Fault detection register records the cause of the faults

- Soft extraction

- Soft re-insertion

- Remote gate shutdown/turn on

- Power ID/manufacturing ID memory (2kb of EEPROM)

• Programmable Power Sequencing

- Sequence up to 5 DC/DC converters.

- Four independent voltage enable pins

- Four programmable time delay circuits

- Soft Power Sequencing - restart sequence without
power cycling.

• Hot Swap Controller

- Programmable overvoltage and undervoltage protection

- Undervoltage lockout for battery/redundant supplies

- Programmable slew rate for external FET gate control

- Electronic circuit breaker - overcurrent detection and
gate shut-off

- Programmable overcurrent limit during Insertion

- Programmable hardshort retry with retry failure flag

- Typically operates from -30V to -80V. Tolerates
transients to -200V (limited by external components)

• Available Packages

- 32-lead Quad No-Lead Frame (QFN)

Applications

• -48V Hot Swap Power Backplane/Distribution Central
Office, Ethernet for VOIP

• Card Insertion Detection

• Power Sequencing DC-DC/Power Bricks

• IP Phone Applications

• Databus Power Interfacing

• Custom Industrial Power Backplanes

• Distributed Power Systems

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2005. All Rights Reserved

Pinout

V4GOOD

V3GOOD

V2GOOD

V

RGO

A0

EN4

EN3

EN2

X80000, X80001

X80000, X80001

(7X7 QFN)

TOP VIEW

GQ0

GQ1

PWRGD

I

MRH

32

1

BATT-ON

I

2
3
4

(7mm x 7mm)

5
6

7
817

910111213 14

EE

FAR

NC

V

262728293031

25

NC

24

MRC

23

WP

22

RESET

21
20

V1GOOD
EN1

19

SCL

18

SDA

15

16

Ordering Information

PAR T

NUMBER OV UV1 UV2

X80000Q32I 74.9 42.4 33.2 I 32 Ld

X80001Q32I 68.0 42.4 33.2 I 32 Ld

TEMP

RANGE PKG

QFN

QFN

PART

MARK

80000I

80001I

EE

DD

V

V

Typical Application

Back­Plane

SCL

SDA

Insert

Control

-48V
RTN

-48V

Opto-

Isolation

R5
30K

1%

12V

R4

182K

1%

R6

10K

1%

4.7V

V

UV/OV

V
V

SCL

SDA
MRH

UV/OV
DD

V

EE

0.02Ω

SENSE

Rs

5%

GATE

OV=71V
UV=37V

SENSE

NC

DRAIN

X80000
X80001

GATE

0.1µF

IRFR120

Q1

A1

PWRGD
V1GOOD
V2GOOD
V3GOOD

DRAIN

100

EN1
EN2
EN3

4.7K

3.3n

100K

DC-DC

Module

1

ON/OFF

DC-DC

Module

2

ON/OFF

V1

DC-DC

Module

3

ON/OFF

V2

DC-DC

Module

4

ON/OFF

V3

V4

2

FN8148.0

March 18, 2005

X80000, X80001

Absolute Maximum Ratings Recommended Operating Conditions

Temperature under bias . . . . . . . . . . . . . . . . . . . . . –65°C to +135°C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Voltage on given pin (Hot Side Functions):

V

ov/uv pin

SENSE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400mV + V

VEE pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -80V

DRAIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48V + V

PWRGD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V + V

GATE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD + V

FAR pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V + V

MRH pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V + V

BATT_ON pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V + V

EE
EE

EE
EE
EE
EE
EE
EE

Voltage on given pin (Cold Side Functions):

ENi

pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V

ViGOOD

RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + V

SDA, SCL, WP, A0, A1 pins . . . . . . . . . . . . . . . . . . . . . 5.5V + V

MRC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V + V

IGQ1 and IGQ0 pins . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + V

VDD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V + V

D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . .5.5V + V

EE
EE
EE
EE
EE
EE

Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . .300°C

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40°C to 85°C

Supply Voltage (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V

DD

Electrical Specifications Standard Settings

Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DC CHARACTERISTICS

V

I

DD

V

RGO

I

RGO

I

GATE

V

GATE

V

PGA

V

V

I

I

LO

V

V

DD

IHB

ILB

Supply Operating Range 10 12 14 V

Supply Current 2.5 5 mA

Regulated 5V output I

V

current output 50 µA

RGO

Gate Pin Current Gate Drive On,

External Gate Drive (Slew Rate Control) I

Power Good Threshold (PWRGD High to Low) Referenced to V

= 10µA 4.5 5.5

RGO

46.2 52.5 58.8 µA

V

= VEE,

GATE

V

= V

SENSE

- VEE = 3V

V

GATE

V

SENSE-VEE

= 50µA VDD-0.01 V

GATE

V

< V

UV1

(sourcing)

EE

= 0.1V (sinking)

EE

< V

UV/OV

0.9 1 1.1 V

OV

9mA

Voltage Input High (BATT_ON) VEE + 4 VEE + 5 V

Voltage Input Low (BATT_ON) VEE + 2 V

Input Leakage Current (MRH, MRC) VIL = GND to V

LI

Output Leakage Current
(V1GOOD
RESET

Input LOW Voltage (MRH, MRC, IGQ0, IGQ1) -0.5 +

IL

Input HIGH Voltage (MRH, MRC, IGQ0, IGQ1) (VEE + 5)

IH

, V2GOOD, V3GOOD, V4GOOD,

)

All ENi

= V

CC

for i = 1 to 4 10 µA

RGO

V

EE

x 0.7

DD

10 µA

(VEE + 5)

x 0.3

+ 5)

(V

EE

+ 0.5

V

V

V

3

FN8148.0

March 18, 2005

X80000, X80001

Electrical Specifications Standard Settings

Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

C

OUT

(Note 1)

(Note 1) Input Capacitance (MRH, MRC) VIN = 0V 6 pF

C

IN

V

OC

V

OCI

V

OVR

Output LOW Voltage

OL

(RESET

, V1GOOD, V2GOOD, V3GOOD,

V4GOOD, FAR

, PWRGD)

Output Capacitance
(RESET, V1GOOD, V2GOOD, V3GOOD,
V4GOOD

, FAR)

Overcurrent threshold VOC = V

Overcurrent threshold (Insertion) VOC = V

Overvoltage threshold (rising)

X80000 Referenced to V

X80001 3.49 3.54 3.59 V

V

OVF

Overvoltage threshold (falling)

X80000 Referenced to V

X80001 3.46 3.51 3.56 V

V

UV1R

V

UV1F

V

UV2R

V

UV2F

V

DRAINF

V

DRAINR

V

TRIP1

(Note 1)

V

TRIP2

(Note 1)

V

TRIP3

Undervoltage 1 threshold (rising) Referenced to V

Undervoltage 1 threshold (falling) 2.16 2.21 2.26 V

Undervoltage 2 threshold (rising) Referenced to V

Undervoltage 2 threshold (falling) 1.68 1.73 1.78 V

Drain sense voltage threshold (falling) Referenced to V

Drain sense voltage threshold (rising) Referenced to V

Trip Point Voltage Referenced to V

EN1

Trip Point Voltage Referenced to V

EN2

Trip Point Voltage Referenced to V

EN3

(Note 1)

V

TRIP4

(Note 1)

Trip Point Voltage Referenced to V

EN4

AC CHARACTERISTICS

t

FOC

t

FUV

t

FOV

t

VFR

t

BATT_ON

t

MRC

t

MRH

t

MRCE

t

MRCD

t

MRHE

Sense High to Gate Low 1.5 2.5 3.5 µs

Under Voltage conditions to Gate Low 0.5 1 1.5 µs

Overvoltage Conditions to Gate Low 1.0 1.5 2 µs

Overvoltage/undervoltage failure recovery time to
Gate =1V.

Delay BATT_ON Valid 100 ns

Minimum time high for reset valid on the MRC pin 5 µs

Minimum time high for reset valid on the MRH pin 5 µs

Delay from MRC enable to PWRGD HIGH No Load 1.0 1.6 µs

Delay from MRC disable to PWRGD LOW Gate is On, No Load 200 400 ns

Delay from MRH enable to Gate Pin LOW I

I

= 4.0mA VEE + 0.4 V

OL

V

= 0V 8 pF

OUT

SENSE

SENSE

- V

- V

EE

EE

45 50 55 mV

135 150 165 mV
PWRGD = HIGH
Initial Power Up condition

EE

EE

BATT-ON = V

BATT-ON = V

EE

EE

EE

RGO

EE

EE

EE

EE

EE

EE

VDD does not drop below 3V, No

3.85 3.90 3.95 V

3.82 3.87 3.92 V

2.19 2.24 2.29 V

1.71 1.76 1.81 V

0.9 1 1.1 V

1.2 1.3 1.4 V

V

÷ 2 V

RGO

1.2 1.6 2 µs

other failure conditions.

= 60µA, No Load 1.0 1.6 2.4 µs

GATE

V

V

V

4

FN8148.0

March 18, 2005

X80000, X80001

Electrical Specifications Standard Settings

Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

MRHD

t

RESET_E

t

QC

t

SC_RETRY

t

NF

t

DPOR

t

SPOR

t

TO

t

PDHLPG

(Note 1)

t

PDLHPG

(Note 1)

t

PGHLPG

(Note 1)

t

PGLHPG

(Note 1)

NOTE:

1. This parameter is based on characterization data.

Delay from MRH disable to GATE reaching 1V I

Delay from PWRGD or ViGOOD to RESET valid

= 60µA, No Load 1.8 2.6 µs

GATE

1 µs

LOW

Delay from IGQ1 and IGQ0 to valid Gate pin

1 µs

current

Delay between retries TSC1 = 0; TSC0 = 0 90 100 110 ms

Noise Filter for Overcurrent TF1 = 0; TF0 = 1 4.5 5 5.5 µs

Device Delay before Gate assertion 45 50 55 ms

Delay after PWRGD and all ViGOOD signals are
active before RESET

assertion

TPOR1 = 0; TPOR0 = 0 90 100 110 ms

ViGOOD turn off time 50 ns

Delay from Drain good to PWRGD

Delay from Drain fail to PWRGD

Delay from Gate good to PWRGD

Delay from Gate fail to PWRGD

HIGH Drain = V

LOW Gate = V

HIGH Gate = V

LOW Drain = V

DD

DD

EE

EE

1 µs

1 µs

1 µs

1 µs

Equivalent A.C. Output Load Circuit

5V

,

,

SDA

5V

4.6kΩ

30pF

RESET
FAR
PWRGD

5V

4.6kΩ

30pF

V1GOOD,
V2GOOD,
V3GOOD
V4GOOD

A.C. Test Conditions

Input pulse levels VCC x 0.1 to VCC x 0.9

Input rise and fall times 10ns

Input and output timing levels V

Output load Standard output load

CC

x 0.5

4.6kΩ

30pF

5

FN8148.0

March 18, 2005

V

UV/OV

VDD

X80000, X80001

V

TH

t

DPOR

V

OV

V

UV

t

FOV

t

VFR

t

FUV

t

VFR

MRH

SENSE

GATE

VDD

SENSE

GATE

V

OCI

V

OC

1V 1V

FIGURE 1. OVERVOLTAGE/UNDERVOLTAGE GATE TIMING

V

TH

t

DPOR

V

OCI

V

OC

t

FOC

t

SC_RETRY

Always Retry
V

< V

UV

MRH = HIGH

t

FOC

UV/OV

< V

OV

t

SC_RETRY

VDD

V

TRIPi

ENi

ViGOOD

Initial

Power-up

6

FIGURE 2. OVERCURRENT GATE TIMING

t

TO

t

DELAYi

Enable DC/DC supply

FIGURE 3. ViGOOD TIMINGS

t

TO

i = 1, 2, 3, 4

FN8148.0

March 18, 2005

MRH

t

MRH

X80000, X80001

MRC

t

MRC

GATE

t

MRHE

FIGURE 4. MANUAL RESET (HOT SIDE) MRH

V

DRAIN

V

GATE

PWRGD

ENi

V1GOOD

V2GOOD

t

DHLPG

t

GLHPG

1V

t

MRHD

t

DELAY1

t

DELAY2

PWRGD

t

MRCE

FIGURE 5. MANUAL RESET (COLD SIDE) MRC

t

DLHPG

t

GHLPG

t

MRCD

V3GOOD

V4GOOD

RESET

t

DELAY3

t

DELAY4

t

SPOR

PWRGD or

any ENi

(1st occurance)

FIGURE 6. PWRGD AND RESET TIMINGS

LOW to HIGH

t

RESET_E

7

FN8148.0

March 18, 2005

X80000, X80001

Electrical Specifications Programmable Parameters

Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT

DC CHARACTERISTICS

VCB Over Current Trip Voltage Range Factory Setting is 50mV (see VOCI). 30 100 mV

I

GATE

V

PGA

V

OCI

AC CHARACTERISTICS

t

SC_RETRY

(VCB = V

Gate Pin Pull-Up Current. (error)
(current)

- VEE) For other options, contact Intersil. -12 12 %

SENSE

Gate Drive On; V

= VEE, IGQ1=0;

GATE

IGQ0=0

IG3 = 0; IG2= 0; IG1 = 0; IG0 = 0 Factory Default 9.2 10.5 11.8 µA

IG3 = 0; IG2= 0; IG1 = 0; IG0 = 1 21.0 µA

IG3 = 0; IG2= 0; IG1 = 1; IG0 = 0 31.5 µA

IG3 = 0; IG2= 0; IG1 = 1; IG0 = 1 42.0 µA

IG3 = 0; IG2= 1; IG1 = 0; IG0 = 0 46.2 52.5 58.5 µA

IG3 = 0; IG2= 1; IG1 = 0; IG0 = 1 63.0 µA

IG3 = 0; IG2= 1; IG1 = 1; IG0 = 0 64.7 73.5 82.3 µA

IG3 = 0; IG2= 1; IG1 = 1; IG0 = 1 84.0 µA

IG3 = 1; IG2= 0; IG1 = 0; IG0 = 0 94.5 µA

IG3 = 1; IG2= 0; IG1 = 0; IG0 = 1 105.0 µA

IG3 = 1; IG2= 0; IG1 = 1; IG0 = 0 115.5 µA

IG3 = 1; IG2= 0; IG1 = 1; IG0 = 1 126.0 µA

IG3 = 1; IG2= 1; IG1 = 0; IG0 = 0 136.5 µA

IG3 = 1; IG2= 1; IG1 = 0; IG0 = 1 147.0 µA

IG3 = 1; IG2= 1; IG1 = 1; IG0 = 0 138.6 157.5 176.4 µA

IG3 = 1; IG2= 1; IG1 = 1; IG0 = 1 168.0 µA

IG3-IG0 = Don’t Care IGQ1=0; IGQ0=1 9.2 10.57 11.8 µA

IG3-IG0 = Don’t Care IGQ1=1; IGQ0=0 64.7 73.5 82.3 µA

IG3-IG0 = Don’t Care IGQ1=1; IGQ0=1 138.6 157.5 176.4 µA

Power Good Threshold Accuracy V

- VEE, High to Low Transition.

DRAIN

Default Factory Setting is 47V.

±400 mV

Over current threshold (Insertion) Referenced to VEE

VS1 = 0 VS0 = 0 PWRGD = HIGH 45 50 55 mV

VS1 = 0 VS0 = 1 Factory Default 90 100 110 mV

VS1 = 1 VS0 = 0 135 150 165 mV

VS1 = 1 VS0 = 1 180 200 220 mV

Delay between Retries Factory Default

TSC1 = 0 TSC0 = 0 90 100 110 ms

TSC1 = 0 TSC0 = 1 450 500 550 ms

TSC1 = 1 TSC0 = 0 0.9 1 1.1 s

TSC1 = 1 TSC0 = 1 4.5 5 5.5 s

8

FN8148.0

March 18, 2005

X80000, X80001

Electrical Specifications Programmable Parameters

Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT

t

NF

t

SPOR

t

DELAYi

Noise Filter for Overcurrents Factory Default

F1 = 0 F0 = 0 0µs

F1 = 0 F0 = 1 4.5 5 5.5 µs

F1 = 1 F0 = 0 9 10 11 µs

F1 = 1 F0 = 1 18 20 22 µs

Delay before RESET assertion Factory Default

TPOR1 = 0 TPOR0 = 0 90 100 110 ms

TPOR1 = 0 TPOR0 = 1 450 500 550 ms

TPOR1 = 1 TPOR0 = 0 0.9 1 1.1 s

TPOR1 = 1 TPOR0 = 1 4.5 5 5.5 s

Time Delay used in Power

Factory Default

Sequencing (i = 1 to 4)

TiD1 = 0 TiD0 = 0 90 100 110 ms

TiD1 = 0 TiD0 = 1 450 500 550 ms

TiD1 = 1 TiD0 = 0 0.9 1 1.1 s

TiD1 = 1 TiD0 = 1 4.5 5 5.5 s

Serial Interface

Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DC CHARACTERISTICS

I

CC1

(Note 1)

I

CC2

(Note 1)

I

LI

I

LO

V

(Note 3) Input LOW Voltage (SDA, SCL, WP, A0, A1) -0.5 + VEE (VEE + 5) x

IL

V

(Note 3) Input HIGH Voltage (SDA, SCL, WP, A0, A1) (VEE + 5) x

IH

V

HYS

Active Supply Current (VDD) Read to
Memory or CRs

Active Supply Current (VDD)
Write to Memory or CRs

Input Leakage Current (SCL, WP, A0, A1) VIL = GND to V

Output Leakage Current (SDA) V

Schmitt Trigger Input Hysteresis

Fixed input level V

V

related level .05 x

CC

V

OL

Output LOW Voltage (SDA) IOL = 4.0mA (2.7-5.5V)

VIL = VCC x 0.1
V

= VCC x 0.9,

IH

f

= 400kHz

SCL

CC

= GND to V

SDA

Device is in Standby (Note 2)

I

= 2.0mA (2.4-3.6V)

OL

CC

0.7

+ 0.2 V

EE

(V

+ 5)

EE

AC CHARACTERISTICS

f

SCL

t

t

AA

IN

SCL Clock Frequency 400 kHz

Pulse width Suppression Time at inputs 50 ns

SCL LOW to SDA Data Out Valid 0.1 1.5 µs

2.5 mA

3.0 mA

10 µA

10 µA

0.3

(VEE + 5) +

0.5

+ 0.4 V

V

EE

V

V

V

9

FN8148.0

March 18, 2005

X80000, X80001

Serial Interface (Continued)

Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

BUF

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

t

DH

t

R

t

F

t

SU:WP

t

HD:WP

Cb Capacitive load for each bus line 400 pF

t

(Note 2) EEPROM Write Cycle Time 5 10 ms

WC

NOTE:

2. t

WC

minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

Time the bus is free before start of new

1.3 µs

transmission

Clock LOW Time 1.3 µs

Clock HIGH Time 0.6 µs

Start Condition Setup Time 0.6 µs

Start Condition Hold Time 0.6 µs

Data In Setup Time 100 ns

Data In Hold Time 0 µs

Stop Condition Setup Time 0.6 µs

Data Output Hold Time 50 ns

SDA and SCL Rise Time 20 +.1Cb

300 ns

(Note 1)

SDA and SCL Fall Time 20 +.1Cb

300 ns

(Note 1)

WP Setup Time 0.6 µs

WP Hold Time 0 µs

is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the

Timing Diagrams

t

BUF

SCL

t

SU:STA

SDA IN

SDA OUT

t

F

t

HD:STA

t

SU:DAT

t

HIGH

t

LOW

t

HD:DAT

FIGURE 7. BUS TIMING

t

R

t

SU:STO

t

t

DH

AA

t

BUF

t

HD:STO

t

HD:DAT

10

FN8148.0

March 18, 2005

START

X80000, X80001

SCL

SDA

Symbol Table

SCL

SDA IN

WP

t

8th Bit of Last Byte

SU:WP

Clk 1 Clk 9

Slave Address Byte

FIGURE 8. WP PIN TIMING

ACK

Stop

Condition

FIGURE 9. WRITE CYCLE TIMING

t

HD:WP

t

WC

Start

Condition

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from LOW
to HIGH

May change
from HIGH
to LOW

Don’t Care:
Changes
Allowed

Will be
steady

Will change
from LOW
to HIGH

Will change
from HIGH
to LOW

Changing:
State Not
Known

11

FN8148.0

March 18, 2005

Typical Performance Characteristics

X80000, X80001

52.000

51.000

50.000

49.000

48.000

47.000

INRUSH CURRENT LIMIT (mV)

46.000

-55 -40 -25 -10 5 20 35 50 65 80 95 110 12
TEMPERATURE

1.780

1.770

1.760

1.750

1.740

1.730

1.720

1.710

1.700

UNDERVOLTAGE 2 THRESHOLD (V)

1.690

-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE

FIGURE 10. OVERCURRENT THRESHOLD vs TEMPERATURE FIGURE 11. UNDERVOLTAGE 1 THRESHOLD vs

TEMPERATURE

3.92

3.91

3.90

3.89

3.88

3.87

OV THRESHOLD (V)

3.86

3.85

-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE

RISING

FALLING

FIGURE 12. OVERVOLTAGE THRESHOLD vs TEMPERATURE FIGURE 13. ENi

2.515

2.510

2.505

2.500

2.495

2.490

2.485

ENi THRESHOLD (V)

2.480

2.475

-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE

THRESHOLD vs TEMPERATURE

RISING

FALLING

2.250

2.240

2.230

2.220

2.210

2.200

UNDERVOLTAGE 1 THRESHOLD (V)

2.190

-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE

FIGURE 14. UNDERVOLTAGE 1 THRESHOLD vs

TEMPERATURE

12

RISING

FALLING

200

160

120

80

GATE CURRENT (µA)

40

0

-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE

FIGURE 15. I

(SOURCE) vs TEMPERATURE

GATE

150µA

70µA
50µA

10µA

FN8148.0

March 18, 2005

X80000, X80001

Typical Performance Characteristics (Continued)

11.0

10.5

10.0

9.5

9.0

8.5

8.0

7.5

GATE CURRENT - SINK (mA)

7.0

-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE

(µs)
t

0.800

0.750

0.700

0.650

UV

0.600

0.550

FIGURE 16. I

(SINK) vs TEMPERATURE FIGURE 17. t

GATE

tUV2

tUV1

2.5

2.4

2.3

2.2

(µs)

2.1

OC

t

2.0

1.9

1.8

1.7

-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE

vs TEMPERATURE

FOC

1.02

1.00

0.98

0.96

(NORMALIZED)

0.94

DELAY

t

0.92

0.500

-55-40-25-105 203550658095110125
TEMPERATURE

FIGURE 18. t

vs TEMPERATURE FIGURE 19. t

FUV

1.4

1.4

1.3

1.3

(µs)

1.2

OV

t

1.2

1.1

1.1

1.0

-55 -40 -25 -10 5 20 35 50 65 80 95 110 125

FIGURE 20. t

TEMPERATURE

vs TEMPERATURE

FOV

0.90

-55 -35 -15 5 25 45 65 85
TEMPERATURE

vs TEMPERATURE

DELAYi

13

FN8148.0

March 18, 2005

V

UV/OV

BATT-ON

DRAIN

GATE

X80000, X80001

PWRGD

V

Ref

OV

V

Ref

UV1

V

Ref

UV2

V

V

EE

RGO

2:1

MUX

1V Ref

10-160µA

V

DD

Power Good

Logic

Over current
logic, Hard short
relay , Ret ry logic
status and delay

V

EE

FAR

V

EE

V

DD

IGQ1
IGQ0

V

SENSE

MRC
MRH

EN1

EN2

EN3

EN4

V

EE

RRRR

EE

V

EE

Slew Rate

x2 x3

x1

Selection

Programmable

REF

V

OC

x4

V

RGO

36R

Gate

Control

current

OSC

Over

Divider

Reset

4

Select

0.1s

0.5s
1s
5s

delay1
delay2

delay3
delay4

Delay circuit

repeated 4 times

4

POR

Reset Logic

and Delay

Control and

Fault

Registers

EEPROM

2kbits

V

EE

5V

V

RGO

RESET

V

EE

SDA
SCL
WP

Bus Interface

A2
A1

V

EE

V1GOOD

V2GOOD

V3GOOD

V4GOOD

14

FIGURE 21. BLOCK DIAGRAM

FN8148.0

March 18, 2005

Pin Configuration

X80000/X80001

32-lead QFN Quad Package

X80000, X80001

FAR

262728293031

15

DRAIN

NC

NA

EE

V

25

16

A1

NC

24

MRC

23

WP

22

RESET

21
20

V1GOOD
EN1

19

SCL

18

SDA

V

RGO

V4GOOD

EN4

V3GOOD

EN3

V2GOOD

EN2

GQ0

GQ1

I

MRH

32

1

A0

2
3
4

(7mm x 7mm)

5
6

7
817

910111213 14

EE

DD

V

V

BATT -ON

I

PWRGD

GATE

UV/OV

SENSE

V

Pin Descriptions

PIN NAME DESCRIPTION

1V

RGO

2A0Address Select Input. It has an internal pulldown resistor. (>10MΩ typical)

3 V4GOOD

4EN4V4 Voltage Enable Input. Fourth voltage enable pin. If unused connect to V

5 V3GOOD V3 Voltage Good Output (Active Low). This open drain output goes LOW when EN3 is less than V

6EN3V3 Voltage Enable Input. Third voltage enable pin. If unused connect to V

7 V2GOOD V2 Voltage Good Output (Active Low). This open drain output goes LOW when EN2 is less than V

8EN2

9V

10 V

11 V

DD

EE

UV/OV

12 SENSE Circuit Breaker Sense Input. This input pin detects the overcurrent condition.

13 GATE Gate Drive Output. Gate drive output for the external N-channel MOSFET.

14 DRAIN Drain. Drain sense input of the external N-channel MOSFET.

15 NA Not Available. Do not connect to this pin.

16 A1 Address Select Input. It has an internal pulldown resistor. (>10MΩ typical)

17 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output

18 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output.

19 EN1

Regulated 5V output. Used to pull-up user programmable inputs IGQ0, IGQ1, BATT-ON, A1, A0, and WP (if
needed).

The A0 and A1 bits allow for up to 4 X80000 devices to be used on the same SMBus serial interface.

V4 Voltage Good Output. This open drain output goes LOW when EN4 is less than V
EN4

is greater than V

goes HIGH when EN3

goes HIGH when EN2

V2 Voltage Enable Input. Second voltage enable pin. If unused connect to V

. There is a user selectable delay circuitry on this pin.

TRIP4

is greater than V

is greater than V

. There is a user selectable delay circuitry on this pin.

TRIP3

. There is a user selectable delay circuitry on this pin.

TRIP2

RGO

RGO

.

RGO

.

.

and goes HIGH when

TRIP4

Positive Supply Voltage Input.

Negative Supply Voltage Input.

Analog Undervoltage and Overvoltage Input. Turns off the external N-channel MOSFET when there is an

undervoltage or overvoltage condition.

The A0 and A1 bits allow for up to 4 X80000 devices to be used on the same SMBus serial interface.

and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the
input buffer is always active (not gated).

V1 Voltage Enable Input. First voltage enable pin. If unused connect to V

RGO

.

TRIP3

TRIP2

and

and

15

FN8148.0

March 18, 2005

X80000, X80001

Pin Descriptions (Continued)

PIN NAME DESCRIPTION

20 V1GOOD V1 Voltage Good Output (Active Low).This open drain output goes LOW when EN1 is less than V

21 RESET

HIGH when EN1

RESET Output. This open drain pin is an active LOW output. This pin will be active until PWRGD goes active and

is greater than V

. There is a user selectable delay circuitry on this pin.

TRIP1

the power sequencing is complete. This pin will be released after a programmable delay.

22 WP Write Protect. Input Pin. WP HIGH (in conjunction with WPEN bit=1) prevents writes to any memory

location in the device. It has an internal pulldown resistor. (>10MΩ typical)

23 MRC Manual Reset Input Cold-side. Pulling the MRC pin HIGH initiates a system side RESET. The MRC signal must

be held HIGH for 5µsecs. It has an internal pulldown resistor. (>10MΩ typical)

24 NC No Connect. No internal connections.

25 V

EE

Negative Supply Voltage Input.

26 NC No Connect. No internal connections.

27 FAR

Failure After Re-try (FAR) output signal. Failure After Re-try (FAR) is asserted after a number of retries. Used for
Overcurrent and hardshort detection.

28 BATT-ON Battery On Input. This input signals that the battery backup (or secondary supply) is supplying power to the

backplane. It has an internal pulldown resistor. (>10MΩ typical)

29 PWRGD

Power Good Output. This output pin enables a power module.

30 IGQ1 Gate Current Quick Select Bit 1 Input. This pin is used to change the gate current drive and is intended to allow

for current ramp rate control of the gate pin of an external FET. It has an internal pulldown resistor. (>10MΩ typical)

31 IGQ0 Gate Current Quick Select Bit 0 Input. This pin is used to change the gate current drive and is intended to allow

for current ramp rate control of the gate pin of an external FET. It has an internal pulldown resistor. (>10MΩ typical)

32 MRH

Manual Reset Input Hot-side. Pulling the MRH pin LOW initiates a GATE pin reset (GATE pin pulled LOW). The
MRH

signal must be held LOW for 5µsecs (minimum).

TRIP1

and goes

Functional Description

Hot Circuit Insertion

When circuit boards are inserted into a live backplane, the
bypass capacitors at the input of the board’s power module
or DC/DC converter can draw huge transient currents as
they charge up (See Figure 22). This transient current can
cause permanent damage to the board’s components and
cause transients on the system power supply.

-48V
Return

R4

182K

1%

R5
30k

-48V

1%

R6

10K

1%

V

UV/OV

V

DD

V

I

EE

0.02Ω

inrush

UV=37V

OV=71V

SENSE

Rs

5%

0.1µF

Q1

X80000
X80001

GATE

100

IRFR120

4.7K

3.3n

DRAIN

100K

FIGURE 22. TYPICAL -48V HOTSWAP APPLICATION CIRCUIT

DC/DC

Converter

DC/DC

Converter

-48V

The X80000 is designed to turn on a board’s supply voltage
in a controlled manner (see Figure 23), allowing the board to
be safely inserted or removed from a live backplane. The
device also provides undervoltage, overvoltage and
overcurrent protection while keeping the power module (DC­DC converter) off until the backplane input voltage is stable
and within tolerance.

I

INRUSH

V

GATE

V

FET_DRAIN

PWRGD

FIGURE 23. TYPICAL INRUSH WITH GATE SLEW RATE

CONTROL

16

FN8148.0

March 18, 2005

X80000, X80001

Overvoltage and Undervoltage Shutdown

The X80000 provides overvoltage and undervoltage
protection circuits.

When an overvoltage (V
V

) condition is detected, the GATE pin will be

UV2

immediately pulled low. The undervoltage threshold V
applies to the normal operation with a main supply. The
undervoltage threshold V
powered by a battery. When using a battery backup, the
BATT-ON pin is pulled to V
been set so the external resistance values determine the
overvoltage threshold, a main undervoltage threshold and a
battery undervoltage threshold.

) or undervoltage (V

OV

assumes the system is

UV2

. The default thresholds have

RGO

UV1

and

UV1

V

P

R1

V

S

V

N

R2

V

UV/OV

Voltage divider:

V

UV OV⁄

=

or:

=

V

SVUV OV⁄

R2



----------------------

V

S



R1 R2+

R1 R2+



----------------------



R2

FIGURE 24. OVERVOLTAGE UNDERVOLTAGE DIVIDER

As shown in Figure 26, this circuit block contains
comparators and programmable voltage references to
monitor the single overvoltage and dual undervoltage trip
points. During manufacturing, Intersil programmed the
overvoltage and undervoltage trip points as shown in Table 1
below. Custom values are possible.

A resistor divider connected between the plus and minus
input voltages and the V

pin (see Figure 24)

UV/OV

determines the overvoltage and undervoltage shutdown
voltages and the operating voltage range. Using the
thresholds in Table 1 and the equations of Figure 24 the
desired operating voltage can be determined. Figure 25
shows the resistance values for various operating voltages.

TABLE 1. OVERVOLTAGE/UNDERVOLTAGE DEFAULT

THRESHOLDS

THRESHOLD

MAX/MIN

VO LTAG E

SYMBOL DESCRIPTION FALLING RISING

V

OV

Overvoltage

3.87V 3.9V 74.3 74.9

(Note 1)

(X80000)

V

V

V

Overvoltage

OV

UV1

UV2

(X80001)

Undervoltage 12.21V 2.24V 43.0 42.4

Undervoltage 21.73V 1.76V 33.8 33.2

3.51V 3.54V 67.4 68

NOTES:

1. Max/Min Voltage is the maximum and minimum operating voltage
assuming the recommended V

resistor divider.

UV/OV

2. Lockout voltage is the voltage where the X80000/1 turns off the
FET.

LOCKOUT

VO LTAG E

(Note 2)

100

90
80

V

OV

70
60
50

V

UV1

40
30

V

UV2

20
10

OPERATING VOLTAGE (V)

0

150

158

BATT-ON = V

166

175

R1 in kΩ (for R2=10K)

182

EE

190

Operating

Voltage

BATT-ON = V

198

206

214

RGO

222

FIGURE 25. OPERATING VOLTAGE vs RESISTOR RATIO

Battery Back Up Operations

An external signal, BATT-ON, is provided to switch the
undervoltage trip point. The BATT-ON signal is a LOGIC
HIGH if V

> VEE + 4V and is a LOGIC LOW if V

IHB

ILB

< V

EE

+ 2V. The time from a BATT-ON input change to a valid new
undervoltage threshold is 100ns. See Electrical
Specifications for more details.

Note: The V

pin must be limited to less than VEE +

UV/OV

5.5V in worst case conditions. Values for R1 and R2 must be
chosen such that this condition is met. Intersil recommends
R1 = 182kΩ and R2 = 10kΩ to conform to factory settings.

TABLE 2. SELECTING BETWEEN UNDERVOLTAGE TRIP

PIN DESCRIPTION TRIP POINT SELECTION

BATT-ON Undervoltage Trip

V

UV1

POINTS

Point Selection Pin

and V

UV2

If BATT-ON = 0,
V

trip point is selected;

UV1

If BATT-ON = 1,
V

trip point is selected.

UV2

are undervoltage thresholds.

17

Overvoltage/Undervoltage Fault Condition Flags

On any overvoltage or undervoltage violation, the X80000
cuts-off the GATE. This condition also sets the fault­overvoltage (FOV) or fault-undervoltage1/2 (FUV1/2) bits
low. These bits are readable through the SMBus. To clear
the fault bits, the fault condition must first be rectified (by the

FN8148.0

March 18, 2005

X80000, X80001

system) then cleared by a write to Fault Detection Register.
Please refer to FDR section. See Table 2.

TABLE 3. OVERVOLTAGE/UNDERVOLTAGE FLAG BITS

SYMBOL VIOLATION (ON) NORMAL (OFF)

FOV FOV = 0, when

V

> V

UV/OV

(Overvoltage)

FUV1/2 FUV1/2 = 0, when

V

UV/OV

(Undervoltage)

R1=182K R2=10K

-

+

V

OV

-

+

V

UV1

-

+

V

UV2

Programmable

FIGURE 26. PROGRAMMABLE UNDERVOLTAGE AND

OV

< V

UV1/2

V

UV/OV

Overvoltage Flag

Programmable

VREF

UV flag_1

Programmable

VREF

UV flag_2

VREF

OVERVOLTAGE FOR PRIMARY AND BATTERY
BACKUP

FOV = 1, when
V

< V

UV/OV

and reset by a write operation

FUV1/2 = 1, when
V

UV/OV

and reset by a write operation

-48V

2:1

Mux

BATT_ON

OV

> V

UV1/2

UV Flag

Control

& Status

Registers

+ 0.2V

To Gate
Control

To Gate
Control

SMBus

- 0.2V

Fault Bits
FOV
FUV1/2

SDA
SCL

Overcurrent Protection (Circuit Breaker Function)

The X80000 overcurrent circuit provides the following
functions:

• Overcurrent shut-down of the power FET and external
power good indicators.

• Noise filtering of the current monitor input.

• Relaxed overcurrent limits for initial board insertion.

• Overcurrent recovery retry operation.

• Flag of overcurrent fault condition.

• Flag of overcurrent retry failure.

A sense resistor, placed in the supply path between V
SENSE (see Figure 22) generates a voltage internal to the
X80000. When this voltage exceeds 50mV, an over current
condition exists and an internal “circuit breaker” trips, turning
off the gate drive to the external FET. The actual overcurrent
level is dependent on the value of the current sense resistor.

EE

and

For example a 20mΩ sense resistor sets the overcurrent
level to 2.5A.

Intersil’s X80000 provides a safety mechanism during
insertion of the board into the back plane. During insertion of
the board into the backplane large currents may be induced.
In order to prevent premature shut down of the external FET,
the X80000 allows for a choice of up to 4 times the
overcurrent setting during insertion.

After the PWRGD

signal is asserted, the X80000 switches
back to the normal overcurrent setting. The overcurrent
threshold voltage during insertion can be changed from
50mV to 100mV, 150mV, or 200mV, by setting bits in Control
Register CR4.

After the Power FET turns off due to an overcurrent
condition, a retry circuit turns the FET back on after a delay
of t

SC_RETRY

. If the overcurrent condition remains, the FET
again turns off. This sequence repeats until the overcurrent
condition is released. There are various other options that
program the retry circuit to change the number of retries or
to not retry. An optional output signal, FAR

, indicates a

failure after retry.

Overcurrent Shut-down

As shown in Figure 27, this circuit block contains a resistor
ladder, a comparator, a noise filter and a programmable
voltage reference to monitor for overcurrent conditions.

The overcurrent voltage threshold (V

) is 50mV. This can

OC

be factory set, by special order, to any setting between
30mV and 100mV. V
and V

pins and across the R

EE

is the voltage between the SENSE

OC

SENSE

resistor. If the

selected sense resistor is 20mΩ, then 50mV corresponds to
an overcurrent of 2.5A.

If an overcurrent condition is detected, the GATE is turned
off, all power good indicators go inactive and an overcurrent
failure bit (FOC) is set.

Overcurrent Noise Filter

The X80000 has a noise (low pass) filter built into the
overcurrent comparator. The comparator will thus ignore
current spikes shorter than 5µs. Other filter options are
provided by setting control bits in register CR4. The control
bits set the comparator to ignore current spikes shorter that
5µs, 10µs or 20µs and allow the filter to be turned off.

TABLE 4. NOISE FILTER FOR OVER CURRENTS

t

F1 F0

00 0µs

01 5µs

10 10µs

11 20µs

(maximum noise input pulse width)

NF

18

FN8148.0

March 18, 2005

X80000, X80001

Programmable

Voltage Reference

Overcurrent

36R

R

4x

R

R

R

-48V

FIGURE 27. OVERCURRENT DETECTION/SHORT CIRCUIT PROTECTION WITH PROGRAMMBLE RETRY AND FLAG MONITORS

3x

2x

1x

R

Sense

Overcurrent Event

2 bit
noise
filtering

–

+

0µs

5µs
10µs
20µs

Overcurrent During Insertion

Insertion is defined as the first plug-in of the board to the
backplane. In this case, the X80000 is initially fully powered
off prior to the hot plug connection to the mains supply. This
condition is different from a situation where the mains supply
has temporarily failed resulting in a partial recycle of the
power. This second condition will be referred to as a power
cycle.

During insertion, the board can experience high levels of
current for short periods of time as power supply capacitors
charge up on the power bus. To prevent the overcurrent
sensor from turning off the FET inadvertently, the X80000
has the ability to allow more current to flow through the
powerFET and the sense resistor for a short period of time
until the FET turns on and the PWRGD

signal goes active. In

the standard setting, 200mV is allowed across sense resistor

Logic and Gate

Control Block

Fault Bit
FAR_STAT

still exists, the FET turns off and a retry counter
(SC_Counter) increments. After the selected number of
failed trys, the X80000 sets a Failed After Retry Status
(FAR_STAT) fault bit, sets the FAR
an idle state. In this state the GATE pin will not go active until
the device is cleared.

The retry circuit can be programmed to handle the retry
operation in one of eight ways (See Table 6). The options
allow retries from zero to unlimited and specifies when to
assert the FAR
Retry” case there is no idle state, so when the overcurrent
condition clears, the GATE goes active and the FET turns
on.

There are four optional retry delay periods. These are
100ms, 500ms, 1s, and 5s. These are programmed by bits
located in the CR2 register.

Short-Circuit

Retry Logic

and System

Monitors

Retry Delay

Retry Counter

N

retry

Control

Registers

SMBus

(Failure After Re-Try) signal. In the “Always

Failure After

Re-Try

V

EE

pin LOW and goes into

the during insertion (10A assuming a 20mW resistor). Two
bits in register CR4 select the insertion current limit of 1X,
2X, 3X or 4X the base setting of 50mV. This provides a
mechanism to reduce insertion issues associated with huge
current surges.

TABLE 5. INSERTION OVERCURRENT THRESHOLD OPTIONS

VS1 VS0 V

0 0 50mV (1X)

0 1 100mV (2X)

1 0 150mV (3X)

1 1 200mV (4X)

OCI

After FAR
hardshort protection:

1. Master Reset Hot Side. The master reset pin, MRH

2. Power cycle the part, turning VDD OFF, then ON.

If an overcurrent condition does not occur on any retry, the
gate pin will proceed to open at the user defined slew rate.

Overcurrent Fault Condition Flags

On any overcurrent violation, the X80000 will cut-off the
GATE, turning off the voltage to the load, and setting all

is asserted, there are two ways to clear the

be asserted by pulling it LOW. Upon MRH assertion, all
default values are restored and the retry is cleared.

power good pins to their disabled state. In this condition, the

Hardshort Protection - Programmable Retry

In the event on an overcurrent or hard short condition, the
X80000 includes a retry circuit. This circuit waits for 100ms,
then attempts to again turn on the FET. If the fault condition

fault-overcurrent bit (FOC) goes LOW. To clear FOC,
remove the over current condition, then write to the control
register. Refer to instructions on writing to the FDR (See
Table 8).

FAR

SCL

SDA

, can

19

FN8148.0

March 18, 2005

X80000, X80001

When exceeding the overcurrent retry limit, the status bit
“FAR_STAT” is set to ‘1’ and the FAR

pin is asserted. To
clear FAR_STAT, write to the control register. Refer to
instructions on writing to the FDR (See Table 9).

TABLE 6. RETRY AND EVENT SEQUENCE OPTIONS

N

NR2 NR1 NR0

0 0 0 Always Retry, Do Not assert FAR

001N

N

010N

011N

100N

101N

1 1 0 Always Retry, assert FAR

111N

TSC1 TSC0

0 0 100 miliseconds

0 1 500 miliseconds

1 0 1 second

1 1 5 seconds

STATUS

BIT VIOLATION (ON) NORMAL (OFF)

FOC FOC = 0, when

TABLE 9. RETRY COUNT FAILURE STATUS BIT

STATUS BIT CONDITION

FAR_S TAT if FA R_S TAT = 1, FAR

N

N

N

N

FAR
pin.

GATE pin.

TABLE 7. RETRY EVENT DELAY OPTIONS

TABLE 8. OVERCURRENT FLAG BIT

V

RSENSE

if FAR _STAT = 0 , FAR

AND RETRY SEQUENCE OF EVENTS

RETRY

RETRY
RETRY,

RETRY
RETRY,

RETRY
RETRY,

RETRY
RETRY,

RETRY
RETRY,

when FOC cleared, do not shutoff GATE

RETRY

> V

OC

(FAILURE MODE)

pin (Default)

= 1 (one retry), assert FAR pin after

STOP retry, and shutoff GATE pin

= 2 (two retries), assert FAR pin after

STOP retry, and shutoff GATE pin

= 3 (three retries), assert FAR pin after

STOP retry, and shutoff GATE pin

= 4 (four retries), assert FAR pin after

STOP retry, and shutoff GATE pin

= 5 (five retries), assert FAR pin after

STOP retry, and shutoff GATE pin

pin after 1st retry; clear

= 0 (no retry), asset FAR, and shutoff

t

DELAY BETWEEN RETRIES

SC_RETRY

FOC = 1, when:
V

RSENSE

and reset by a write operation
or hardshort retry is initiated.

is asserted.
is deasserted

< V

OC

,

- 0.2V

The X80000 provides an I

current of 50µA to provide

GATE

on-chip slew rate control to minimize inrush current. This
current is programmable from 10µA to 160uA (in 10µA
steps) to allow the X80000 to support various load conditions
(See Figure 23 and Figure 28). I

is chosen to limit the

GATE

inrush current and to provide the best charge time for a
given load, while avoiding overcurrent conditions. The user
programs the I

I

GATE

INRUSH CURRENT

FIGURE 28. SELECTING I

current using four I

GATE

=

160µA

100µA

75µA

25µA

10µA

T1

CONTROL ON THE GATE PIN

GATE

Overcurrent

T2 T3

TIME (ms)

CURRENT FOR SLEW RATE

control bits.

GATE

T4

T5

I

GATE

For applications that require different ramp rates during
insertion and start-up and operations modes, the X80000
provides two external pins, IGQ1 and IGQ0, that allow the
user to switch to different GATE currents on-the-fly by
selecting one of four pre-selected I

currents. When

GATE

IGQ0 and IGQ1 are left unconnected, the gate current is
determined by the gate control bits. The other three settings
are 10µA, 70µA and 150µA. Typically, the delay from IGQ1
and IGQ0 selection to a change in the GATE pin current is
less than 1 µsecond.

Programmable Slew Rate (Gate) Control

As shown in Figure 29, this circuit block contains a
selectable current source (I
current into the GATE pin. This current provides a controlled
slew rate for the FET.

X80000 allows the user to change the gate current to one of
sixteen possible I

values. The options allow currents of

GATE

between 10µA to 160µA in 10µA increments.

Once the overcurrent condition and the amount of load is
known, an appropriate slew rate can be determined and
selected for the external FET. This will ensure proper

) that drives the 50µA

GATE

Gate Drive Output Slew Rate (Inrush Current)
Control

The gate output drives an external N-Channel FET. The
GATE pin goes high when no overcurrent, undervoltage or
overvoltage conditions exist.

20

FN8148.0

March 18, 2005

”

X80000, X80001

operation to control Inrush currents during hot insertion
modes.

Gate Current

I

INRUSH

Quick Select

Logic

Control

Registers

SMBus

C2

3.3nF

100K

V

=12V

DD

Slew

100*

Rate

Selection

Logic

DRAIN

R2

22K

10µA

to

160µA

SENSEV

EE

-48V
R

SENSE

FIGURE 29. PROGRAMMBLE SLEW RATE (INRUSH

GATE

100nF*

* Optional Components

See Section “Gate Capacitor, Filtering and Feedback

CURRENT) CONTROL

IGQ1
IGQ0

SCL

SDA

LOAD

Software Slew Rate Control

Users can adjust the slew rate control by using an SMBus
write command to change the slew rate control bits. This
allows adaptation in the case of changing load conditions,
creates a modular design for downstream DC-DC supplies,
and provides control of the load on the hot voltage when
slew rates vs. loads vary.

Gate Capacitor, Filtering and Feedback

In Figure 29, the FET control circuit includes an FET
feedback capacitor C

, which provides compensation for the

2

FET during turn on. The capacitor value depends on the
load, the FET gate current, and the maximum desired inrush
current.

The value of C2 can be selected with the following formula:

C2

I

-------------------------------------------=

GATE

I

C×

LOAD

INRUSH

Where:

I

= FET Gate current

GATE

I

INRUSH

C

= Maximum desired inrush current

= DC/DC bulk capacitance

LOAD

With the X80000, there is some control of the gate current
with the IGQ pins and IGx bits, so one selection of C2 can
cover a wide range of possible loading conditions. Typical
values for C2 range from 2.2 to 4.7nF.

voltage from rising and keep the FET from turning on.
However, unless V

powers up very quickly, there will be a

DD

brief period of time during initial application of power when
the X80000 circuits cannot hold the gate low. The use of an
external capacitor (C1) prevents this. Capacitors C1 and C2
form a voltage divider to prevent the gate voltage from rising
above the FET turn on threshold before the X80000 can hold
the gate low. Use the following formula for choosing C1.

V1 V2–

C1

--------------------- C 2=
V2

Where:

V1 = Maximum input voltage,
V2 = FET threshold Voltage,
C1 = Gate capacitor,
C2 = Feedback capacitor.

In a system where V

rises very fast, a smaller value of C1

DD

may suffice as the X80000 will control voltage at the gate
before the voltage can rise to the FET turn on threshold. The
circuit of Figure 29 assumes that the input voltage can rise to
80V before the X80000 sees operational voltage on V

DD

. If
C1 is used then the series resistor R1 will be required to
prevent high frequency oscillations.

TABLE 10. I

IG3 IG2 IG1 IG0 I

0000 10

0001 20

0010 30

0011 40

0 1 0 0 50 Default

0101 60

0110 70

0111 80

1000 90

1001 100

1010 110

1011 120

1100 130

1101 140

1110 150

1111 160

OUTPUT CURRENT OPTIONS

GATE

GATE

(µA)

When power is applied to the system, the FET tries to turn
on due to its internal gate to drain capacitance (Cgd) and the
feedback capacitor C2 (see Figure 29). The X80000 device,
when powered, pulls the gate output low to prevent the gate

21

GATE Current Quick Selection

For applications that require different ramp rates during
insertion and start-up and operations modes or those where
the serial interface is not available, the X80000 provides two

FN8148.0

March 18, 2005

X80000, X80001

external pins, IGQ1 and IGQ0, that allow the system to
switch to different GATE current on-the-fly with pre-selected
I

currents.

GATE

The IGQ1 and IGQ0 pins can be used to select from one of
four set values.

IGQ1

PIN

0 0 Defaults to gate current set by IG3:IG0 bits

0 1 Gate Current is 10µA

1 0 Gate Current is 70µA

1 1 Gate Current is 150µA

IGQ0

PIN CONTENTS

EE

–
+

Programmable)

∆V

GATE

–
+

VDD-1V

SENSEV

∆V

DRAIN

1V

(Factory

GATE

DRAIN

Power

Good
Logic

Control/Status

Registers

V

SMBus

PWRGD

EE

SCL

SDA

Typically, the delay from IGQ1 and IGQ0 selection to a
change in the GATE pin current is less than 1 µsecond.

Drain Sense and Power Good Indicator

The X80000 provides a drain sense and power good
indicator circuit. The PWRGD
there is no overvoltage, no undervoltage, and no overcurrent
condition, the Gate voltage exceeds VDD-1V, and the
voltage at the DRAIN pin is less V

As shown in Figure 30, this circuit block contains a drain
sense voltage trip point (∆V
point (∆V

), two comparators, and internal voltage

GATE

references. These provide both a drain sense and a gate
sense circuit to determine the whether the FET has turned
on as requested. If so, the power good indicator (PWRGD
goes active.

The drain sense circuit checks the DRAIN pin. If the voltage
on this pin is greater that 1V above V
condition exists.

The gate sense circuit checks the GATE pin. If the voltage
on this pin is less than V

The PWRGD signal asserts (Logic LOW) only when all of the
below conditions are true:

• there is no overvoltage or no undervoltage condition, (i.e.
undervoltage < V

EE

• There is no overcurrent condition (i.e. V
V

.)

OC

• The FET is turned on (i.e. V

- 1V).

> V

DD

signal asserts LOW when

EE+VDRAIN

) and a gate voltage trip

DRAIN

EE

- 1V, then a fault condition exists.

EE

.

, then a fault

< overvoltage.)

- V

EE

SENSE

< VEE + 1V and V

DRAIN

)

<

GATE

100K

-48V
R

SENSE

FIGURE 30. DRAIN SENSE AND POWER GOOD INDICATOR

LOAD

Power On Reset and System Reset With Delay

Application of power to the X80000 activates a Power On
Reset circuit that pulls the RESET
used, provides several benefits.

• It prevents the system microprocessor from starting to
operate with insufficient voltage.

• It prevents the processor from operating prior to
stabilization of the oscillator.

• It allows time for an FPGA to download its configuration
prior to initialization of the circuit.

• It prevents communication to the EEPROM during
unstable power conditions, greatly reducing the likelihood
of data corruption on power up.

The SPOR/RESET circuit is activated when all voltages are
within specified ranges and the following time-out conditions
are met: PWRGD
V4GOOD

. The SPOR/RESET circuit will then wait 100ms

and assert the RESET

and V1GOOD, V2GOOD, V3GOOD, and

pin. The SPOR delay may be
changed by setting the TPOR bits in register CR2. The delay
can be set to 100 ms, 500 ms, 1 second, or 5 seconds.

TPOR1 TPOR0

TABLE 11. SPOR RESET DELAY OPTIONS

t

SPOR

0 0 100 miliseconds (default)

0 1 500 miliseconds

1 0 1 second

1 1 5 seconds

pin active. This signal, if

DELAY BEFORE RESET

ASSERTION

22

FN8148.0

March 18, 2005

X80000, X80001

EN1

EN2

EN3

EN4

Drain Sense

Good Logic

Enable

Logic

ViGOOD
i = 1 to 4

& Power

RESET Logic

t

SPOR

Control

Remote

& Fault

Registers

EEPROM

2Kbits

Delay

V

RGO

PWRGD

SPOR

Fault Detection Register

OSC

Divider

Reset

4

4

Select

0.1s

0.5s
1s
5s

delay1
delay2

delay3
delay4

Delay circuit

repeated 4 times

Control Register

V

EE

FIGURE 32. VOLTAGE ENABLE CONTROL AND VGOOD OUTPUTS

delay time can be changed by setting bits in register CR2
(See Figure 32).

As shown in Figure 32, this circuit block contains four
separate voltage enable inputs, a time delay circuit, and an
output driver.

TABLE 12. ViGOOD OUTPUT TIME DELAY OPTIONS

V

DD

TiD1 TiD0 t

0 0 100ms

RESET

µP

0 1 500ms

1 0 1 secs

V

EE

MRC

SDA

11 5 secs

where i is the ith voltage enable (i = 1 to 4).

Manual Reset and Remote Shutdown

Bus Interface

SCL

The manual reset option allows a hardware reset of either
the Gate control or the PWRGD
used to recover the system in the event of an abnormal
operating condition.

SMBus Interface

V1GOOD

V2GOOD

V3GOOD

V4GOOD

DELAYi

indicator. These can be

FIGURE 31. POWER ON/SYSTEM RESET AND DELAY

(BLOCK DIAGRAM)

Quad Voltage Monitoring

X80000 monitors 4 voltage enable inputs. When the ENi
(i=1-4) input is detected to be below the input threshold, the
output ViGOOD
is asserted after a delay of 100ms. This delay can be
changed on each ViGOOD
register CR3. The delay can be 100ms, 500ms, 1s and 5s.
The ViGOOD
threshold.

Once the PWRGD
of the DC-DC modules can commence. RESET
100ms after all ViGOOD

(i = 1 to 4) goes active. The ViGOOD signal

output individually with bits in

signal remains active low until ENi rises above

signal is asserted, the power sequencing

will go active

(i=1 to 4) outputs are asserted. This

23

The remote shutdown feature of the X80000 allows smart
power control remotely through the SMBus. The host system
can either override the control of the FET, thus turning it off,
or it can remove the override. Removing the override restarts
the power up sequence.

The X80000 has two manual reset pins: MRH
hot side) and MRC (manual reset cold side). The MRH

(manual reset

signal is used as a manual reset for the GATE pin. This pin is
used to initiate Soft Reinsert. When MRH

is pulled LOW the
GATE pin will be pulled LOW. It also clears the Remote
Shutdown Register (RSR) and the FAR
MRH

pin goes HIGH, it removes the override signal and the

signal. When the

FN8148.0

March 18, 2005

X80000, X80001

gate will turn on based on the selected gate control
mechanism.

TABLE 13. MANUAL RESET OF THE HOT SIDE (GATE SIGNAL)

MRH GATE PIN REQUIREMENTS

1 Operational When MRH

function is disabled and the
device operates normally

0OFFMRH

to turn of the GATE

is HIGH the Manual Reset (Hot)

must be held LOW minimum of 5µsecs

The MRC signal is used as a manual reset for the PWRGD
signal. This pin is used to initiate a Soft Restart. When the
MRC is pulled HIGH, the PWRGD
When MRC pin goes LOW, the PWRGD

signal is pulled HIGH.

pin goes low using
the MRC pin has no affect on the FET gate control, so the
FET remains on.

TABLE 14. MANUAL RESET OF THE COLD SIDE (PWRGD

SIGNAL)

MRC PWRGD Requirements

1 HIGH MRC must be held HIGH minimum of 5µsecs

to set PWRGD

0 Operational When MRC is LOW the MRC function is

disabled and the device operates normally

HIGH

Fault Detection

The X80000 contains a Fault Detection Register (FDR) that
provides the user the status of the causes for a RESET

pin

active (See Table 17).

At power-up, the FDR is defaulted to all “0”. The system
needs to initialize the register to all “1” before the actual
monitoring can take place. In the event that any one of the
monitored sources fail, the corresponding bit in the register
changes from a “1” to a “0” to indicate the failure (ViGOOD
sources set the bit LOW when the ViGOOD goes LOW
indicating a “good” status). When a RESET is detected by
the main controller, the controller should read of the FDR
and note the cause of the fault. After reading the register, the
controller can reset the register bit back to all “1” in
preparation for future monitored conditions.

Remote Shutdown

The gate of the external MOSFET can be remotely shutdown
by using a software command sequence. A byte write of
‘10101010’ (AAh) data to the Remote Shutdown Register
(RSR) will shutdown the gate and the gate will be pulled low.

Flexible Power Sequencing of Multiple Power
Supplies

The X80000 provides several circuits such as multiple
voltage enable pins, programmable delays, and a power
good signals that can be used to set up flexible power
sequencing schemes for downstream DC-DC supplies.
Below are two examples:

1. Power Up of DC-DC Supplies In Parallel Sequencing
Using Programmable Delays on Power Good (See Figure
33 and Figure 34).

Several DC-DC power supplies and their respective
power up start times can be controlled using the X80000
such that each of the DC-DC power supplies will start up
following the issue of the PWRGD
signal is fed into the ENi

inputs to the X80000. When

signal. The PWRGD

PWRGD is valid, the internal voltage enable inputs issue
ViGOOD signals after a time delay. The ViGOOD signals
control the ON

/OFF pins of the DC-DC supplies. In the
factory default condition, each DC/DC converter is
instructed to turn on 100ms after the PWRGD goes
active. However, each ViGOOD

delay is individually
selectable as 100ms, 500ms, 1s and 5s. The delay times
are changed via the SMBus during calibration of the
system.

2. Power Up of DC-DC Supplies Via Relay Sequencing
Using Power Good and Voltage Enables (see Figure 35
and Figure 36).

Several DC-DC power supplies and their respective
power up start times can be controlled using the X80000
such that each of the DC-DC power supplies will start in
a relay sequencing fashion. The 1st DC-DC supply will
power up when PWRGD

is LOW after a 100ms delay.
Subsequent DC-DC supplies will power up after the prior
supply has reached its operating voltage. One way to do
this is by using an external CPU Supervisor (for example
the Intersil X40430) to monitor the DC-DC output. When
the DC/DC voltage is good, the supervisor output signals
the X80000 EN1

input to sequence the next supply. An
opto-coupler is recommended in this connection for
isolation. This configuration ensures that each
subsequent DC-DC supply will power up after the
preceding DC-DC supplys voltage output is valid. Again,
the X80000 offers programmable delays for each voltage
enable input that is selectable via the SMBus during
calibration of the system.

Activating the MRH

pin or a writing 00h into the RSR will turn
off the override signal and the gate will turn on based on the
gate control mechanism.

The RSR powers up with ‘0’s in the register and its contents
are volatile.

24

FN8148.0

March 18, 2005

X80000, X80001

-48V

Return

-48V

Return

-48V

Return

R5

30K

1%

-48V

R4

182K

1%

R6

10K

1%

V

UV/OV

V

DD

V

EE

0.02Ω

C3

0.1µF
100V

C6

0.1µF
100V

MRH

UV=37V

OV=71V

Rs

5%

+

+

SENSE

0.1µF

IRFR120

100µF

100V

100µF

100V

Q1

C4

C7

1

4

1

4

X80000

X80001

GATE

4.7K

100

V

V

V

V

3.3n

ON/OFF

IN+

IN-

ON/OFF

IN+

IN-

DRAIN

100K

V

OUT

SENSE+

TRIM

SENSE-

V

OUT

V

OUT

SENSE+

TRIM

SENSE-

V

OUT

MRC

+

+

9
8
7

6
5

9
8
7

6
5

RESET

V4GOOD

V3GOOD

V2GOOD

V1GOOD

PWRGD

OPTO
COUPLER

RESET

C5

+

100µF

16V

C8

+

100µF

16V

EN4

EN3

EN2

EN1

3.3V

2.5V

OPTO
COUPLER

V

V

V

V

PWRGD

RESET

CC1

CC2

µC

CC1

CC2

FPGA

-48V

Return

-48V

Return

C9

0.1µF
100V

C12

0.1µF
100V

ON/OFF

1

V

IN+

V

IN-

V

IN+

V

SENSE+

ON/OFF

SENSE+

IN-

C10

+

100µF

100V

4

1

C13

+

100µF

100V

4

V

OUT

TRIM

SENSE-

V

OUT

V

OUT

TRIM

SENSE-

V

OUT

9

+

8
7

6

+

C11

100µF

16V

5

9

+

8
7

6

+

C14

100µF

16V

5

1.8V

1.2V

FIGURE 33. TYPICAL APPLICATION OF HOTSWAP AND DC-DC PARALLEL POWER SEQUENCING

25

V

CC1

V

CC2

ASIC

FN8148.0

March 18, 2005

X80000, X80001

EN2 In

(from PWRGD)

t

V1GDO

Power Supply

#1 OUTPUT

(3.3V)

EN2

t

DELAY2

V2GDO

Power Supply

#2 OUTPUT

(2.5V)

EN3

t

DELAY3

V3GDO

Power Supply

#3 OUTPUT

(1.8V)

EN4

FET

turns ON

DELAY1

Programmable

Delay

Programmable

100ms
500ms
1sec
5sec

Power Supply

#1 turns ON

Delay

Programmable

Delay

100ms
500ms
1sec
5sec

Power Supply

#2 turns ON

DELAYx

and t

Select t

via the 2-wire interface.

100ms
500ms
1sec
5sec

Power Supply

#3 turns ON

RESET

100ms
500ms
1sec
5sec

t

DELAY4

V4GDO

Power Supply

#4 OUTPUT

(1.2V)

RESET

Programmable

Delay

t

RESET

FIGURE 34. PARALLEL SEQUENCING OF DC-DC SUPPLIES (TIMING)

Power Supply

#4 turns ON

Programmable

Delay

100ms
500ms
1sec
5sec

26

FN8148.0

March 18, 2005

X80000, X80001

-48V

Return

R5

30k

1%

-48V

-48V

Return

-48V

Return

R4

182k

1%

R6

10k

1%

V

UV/OV

V

DD

V

EE

0.02Ω

C3

0.1µF
100V

C6

0.1µF
100V

MRH

UV=37V

OV=71V

Rs

5%

SENSE

0.1µF

+

+

Q1

IRFR120

C4

100µF

100V

C7

100µF

100V

1

4

1

4

X80000
X80001

GATE

4.7K

100

V

V

V

V

3.3n

IN+

IN-

IN+

IN-

100K

ON/OFF

V

OUT

SENSE+

TRIM

SENSE-

ON/OFF

V

OUT

SENSE+

TRIM

SENSE-

MRC

DRAIN

+

V

OUT

+

V

OUT

RESET

OPTO
COUPLER

9
8
7

6
5

9
8
7

6
5

V4GOOD

V3GOOD

V2GOOD

V1GOOD

PWRGD

C5

+

100µF

16V

C8

+

100µF

16V

EN4

EN3

EN2

EN1

OPTO
COUPLER

3.3V

2.5V

OPTO

COUPLER

VFAIL<1:3>

(Optional)

X40430

VMON<1:3>

PWRGD

RESET

RESET

V

CC1

V

CC2

µC

V

CC1

V

CC2

FPGA

-48V

Return

-48V

Return

C9

0.1µF
100V

C12

0.1µF
100V

ON/OFF

1

V

IN+

V

IN-

V

V

ON/OFF

IN+

IN-

SENSE+

SENSE+

C10

+

100µF

100V

4

1

C13

+

100µF

100V

4

V

OUT

TRIM

SENSE-

V

OUT

V

OUT

TRIM

SENSE-

V

OUT

9

+

8
7

6

+

C11

100µF

16V

5

9

+

8
7

6

+

C14

100µF

16V

5

1.8V

1.2V

FIGURE 35. TYPICAL APPLICATION OF HOTSWAP AND DC-DC RELAY SEQUENCING

27

V

CC1

V

CC2

ASIC

FN8148.0

March 18, 2005

X80000, X80001

EN2 In

(from PWRGD)

t

V1GDO

Power Supply

#1 OUTPUT

(3.3V)

EN2

V2GDO

Power Supply

#2 OUTPUT

(2.5V)

EN3

V3GDO

Power Supply

#3 OUTPUT

(1.8V)

EN4

FET

turns ON

DELAY1

Programmable

Delay

t

DELAY2

100ms
500ms
1sec
5sec

Power Supply

#1 turns ON

V2MON
threshold

Programmable

Delay

t

DELAY3

100ms
500ms
1sec
5sec

Power Supply

#2 turns ON

V3MON
threshold

Programmable

Delay

DELAYx

and t

Select t

via the 2-wire interface.

100ms
500ms
1sec
5sec

Power Supply

#3 turns ON

V4MON

threshold

RESET

100ms
500ms
1sec
5sec

V4GDO

Power Supply

#4 OUTPUT

(1.2V)

RESET

FIGURE 36. RELAY SEQUENCING OF DC-DC SUPPLIES (TIMING)

Control Registers and Memory

The user addressable internal control, status and memory
components of the X80000 can be split up into four parts:

• Control Register (CR)

• Fault Detection Register (FDR)

• Remote Shutdown Register (RSR)

• EEPROM array

t

DELAY4

Programmable

Delay

t

RESET

Power Supply

#4 turns ON

Programmable

Delay

100ms
500ms
1sec
5sec

Registers

The Control Registers, Remote Shutdown Register and
Fault Detection Register are summarized in Table 15.
Changing bits in these registers change the operation of the
device or clear fault conditions. Reading bits from these
registers provides information about device configuration or
fault conditions. Reads and writes are done through the
SMBus serial port. It is important to remember that, in most
cases, the SMBus serial port must be isolated between the
X80000, which is referenced to -48V, and the system
controller, which is referenced to ground.

28

FN8148.0

March 18, 2005

X80000, X80001

All of the Control Register bits are nonvolatile (except for the
WEL bit), so they do not change when power is removed.

The values of the Register Block can be read at any time by
performing a random read (see Serial Interface) at the
specific byte address location. Only one byte is read by each
register read operation.

TABLE 15. REGISTER ADDRESS MAP

BYTE

ADDR.

(1) This register is write only

REGISTER

NAME DESCRIPTION

00H CR0 Control

Register 0

01H CR1 Control

Register 1

02H CR2 Control

03H CR3 Control

04H CR4 Control

05H RSR

FF FDR Fault Detection

(Note 1)

Register 2

Register 3

Register 4

Remote Shutdown

Register

Register

WEL0000000Volatile

WPEN 0 0 BP1 BP0 NR2 NR1 NR0 EEPROM

IG3 IG2 IG1 IG0 TPOR1 TPOR0 TSC1 TSC0 EEPROM

T4D1 T4D0 T3D1 T3D0 T2D1 T2D0 T1D1 T1D0 EEPROM

VS1 VS0 F1 F0 0 0 0 0 EEPROM

AAh: Override FET control and shutdown the FET
00h: Turn off override
(All other data combinations to RSR are reserved.)

FOV FUV1/2 FOC FAR_

Bits in the registers can be modified by performing a single
byte write operation directly to the address of the register
and only one data byte can change for each register write
operation.

BIT

V40S V30S V20S V10S Volatile

STAT

MEMORY

TYPE 76543210

Volatile

TABLE 16. FAULT DETECTION BITS SUMMARY

LOCATION(S)

SYMBOL

FAR_STAT FDR 4 Retry Violation FAR_STAT = 0 : Failure After retry detected (must be preset to 1).

FOC FDR 5 Overcurrent Violation FOC = 0 : Over current detected (must be preset to 1).

FOV FDR 7 Overvoltage Violation FOV = 0 : Over voltage detected (must be preset to 1).

FUV1/2 FDR 6 Undervoltage Violation FUV1/2 = 0 : Under voltage detected (must be preset to 1).

V1OS FDR 0 1st Voltage Good V1OS = 0 : V1GOOD

V2OS FDR 1 2nd Voltage Good V2OS = 0 : V2GOOD

V3OS FDR 2 3rd Voltage Good V3OS = 0 : V3GOOD pin has been asserted (must be preset to 1).

V4OS FDR 3 4th Voltage Good V4OS = 0 : V4GOOD

REGISTER BITS

CONTROL FUNCTION/

STATUS INDICATION DESCRIPTION

pin has been asserted (must be preset to 1).

pin has been asserted (must be preset to 1).

pin has been asserted (must be preset to 1).

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TABLE 17. HARDWARE/SOFTWARE CONTROL AND FAULT DETECTION BITS SUMMARY

LOCATION(S)

SYMBOL

REGISTER BITS

SOFTWARE CONTROL BITS

F0

CR4 5:4 Insertion Current Filter F1=0, F0=0 ; t

F1

IG0

CR2 7:4 Gate Current Select See Table 10.
IG1
IG2
IG3

NR0

CR1 2:0 Retry Sequence Options See Table 6.

NR1
NR2

T1D0

CR3 1:0 V1GOOD

T1D1

T2D0

CR3 3:2 V2GOOD

T2D1

T3D0

CR3 5:4 V3GOOD

T3D1

T4D0

CR3 7:6 V4GOOD

T4D1

TPOR0

CR2 3:2 RESET

TPOR1

TSC0

CR2 1:0 Overcurrent Retry Delay

TSC1

VS0

CR4 7:6 Insertion Overcurrent Limit VS1=0, VS0=0 ; Insertion Overcurrent Limit = 1X

VS1

WEL CR0 7 Write Enable WEL = 1 enables write operations to the control registers and EEPROM.

WPEN CR1 7 Write Protect WPEN = 1 (and WP pin HIGH) prevents writes to the control registers and the

BP1

CR1 4:3 EEPROM Block Protect BP1=0, BP0=0 : No EEPROM memory protected.

BP0

HARDWARE SELECT BITS

IGQ0

Input pins Gate Current Select IGQ1=0, IGQ0=0 : I

IGQ1

BATTON Input pin Main or Battery BATTON = 0 ; Undervoltage Threshold = V

CONTROL FUNCTION/

STATUS INDICATION DESCRIPTION

= 0
F1=0, F0=1 ; t
F1=1, F0=0 ; t
F1=1, F0=1 ; t

NF
NF
NF
NF

= 5µs

= 10µs

= 20µs

Time Delay TiD1=0, TiD0=0 : ViGOOD delay = 100ms

Time Delay

TiD1=0, TiD0=1 : ViGOOD
TiD1=1, TiD0=0 : ViGOOD
TiD1=1, TiD0=1 : ViGOOD

delay = 500ms
delay = 1s
delay = 5s

Time Delay

Time Delay

delay time TPOR1=0, TPOR0=0 : RESET delay = 100ms

Time

TPOR1=0, TPOR0=1 : RESET
TPOR1=1, TPOR0=0 : RESET
TPOR1=1, TPOR0=1 : RESET

TSC1=0, TSC0=0 ; t
TSC1=0, TSC0=1 ; t
TSC1=1, TSC0=0 ; t
TSC1=1, TSC0=1 ; t

SC_RETRY
SC_RETRY
SC_RETRY
SC_RETRY

delay = 500ms
delay = 1s
delay = 5s

= 100ms
= 500ms
= 1s
= 5s

VS1=0, VS0=1 ; Insertion Overcurrent Limit = 2X
VS1=1, VS0=0 ; Insertion Overcurrent Limit = 3X
VS1=1, VS0=1 ; Insertion Overcurrent Limit = 4X

WEL = 0 prevents write operations.

EEPROM.

BP1=0, BP0=1 : Upper 1/4 of EEPROM memory protected
BP1=1, BP0=0 : Upper 1/2 of EEPROM memory protected.
BP1=1, BP0=1 : All of EEPROM memory protected.

= set by IG0-IG3
IGQ1=0, IGQ0=1 : I
IGQ1=1, IGQ0=0 : I
IGQ1=1, IGQ0=1 : I

GATE
GATE
GATE
GATE

= 10µA

= 70µA

= 150µA

BATTON = 1 ; Undervoltage Threshold = V

UV1
UV2

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X80000, X80001

Memory

The X80000 contains a 2kbit EEPROM memory array. This
array can contain information about manufacturing location
and dates, board configuration, fault conditions, service
history, etc. Access to this memory is through the SMBus
serial port. Read and write operations are similar to those of
the control registers, but a single command can write up to
16 bytes at one time. A single read command can return the
entire contents of the EEPROM memory.

Register and Memory Protection

In order to reduce the possibility of inadvertent changes to
either a control register of the contents of memory, several
protection mechanisms are built into the X80000. These are
a Write Enable Latch, Block Protect bits, a Write Protect
Enable bit and a Write Protect pin.

WEL: Write Enable Latch

A write enable latch (WEL) bit controls write accesses to the
nonvolatile registers and the EEPROM memory array in the
X80000. This bit is a volatile latch that powers up in the LOW
(disabled) state. While the WEL bit is LOW, writes to any
address (registers or memory) will be ignored. The WEL bit
is set by writing a “1” to the WEL bit and zeroes to the other
bits of the control register 0 (CR0). It is important to write
only 00h or 80h to the CR0 register.

Once set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits of the
control register) or until the part powers up again.

Note, a write to FDR or RSR does not require that WEL=1.

BP1 and BP0: Block Protect Bits

The Block Protect Bits, BP1 and BP0, determines which
blocks of the memory array are write protected. A write to a
protected block of memory is ignored. The block protect bits
will prevent write operations to one of four segments of the
array.

PROTECTED ADDRESSES

BP1

BP0

0 0 None (Default) None (Default)

0 1 C0h - FFh (64 bytes) Upper 1/4

1 0 80h - FFh (128 bytes) Upper 1/2

1 1 00h - FFh (256 bytes) All

(SIZE) ARRAY LOCK

WPEN: Write Protect Enable

The Write Protect pin and Write Protect Enable bit in the
CR1 register control the Programmable Hardware Write
Protect feature. Hardware Protection is enabled when the
WP pin is HIGH and WPEN bit is HIGH and disabled when
WP pin is LOW or the WPEN bit is LOW. When the chip is
Hardware Write Protected, non-volatile writes to all control
registers (CR1, CR2, CR3, and CR4) are disabled including
BP bits, the WPEN bit itself, and the blocked sections in the
memory Array. Only the section of the memory array that are
not block protected can be written.

TABLE 18. WRITE PROTECT CONDITIONS

MEMORY ARRAY

NOT BLOCK

WEL WP WPEN

LOW X X Writes Blocked Writes Blocked Writes Blocked Hardware

HIGH LOW X Writes Enabled Writes Blocked Writes Enabled Software

HIGH HIGH LOW Writes Enabled Writes Blocked Writes Enabled Software

HIGH HIGH HIGH Writes Enabled Writes Blocked Writes Blocked Hardware

PROTECTED

MEMORY ARRAY

BLOCK PROTECTED

WRITES TO

CR1, CR2, CR3, CR4 PROTECTION

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Bus Interface Information

Interface Conventions

The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. Therefore,
the devices in this family operate as slaves in all
applications.

It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a stop condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a stop condition.

Serial Clock and Data

Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions (See Figure 37).

Serial Start Condition

All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met.

condition is generated by the master, the device will continue
to transmit data. The device will terminate further data
transmissions if an acknowledge is not detected. The master
must then issue a stop condition to return the device to
Standby mode and place the device into a known state.

SCL

SDA

Start Stop

FIGURE 37. VALID START AND STOP CONDITIONS

SCL from

Master

Data Output from

Transmitter

Data Output from

Receiver

Start Acknowledge

FIGURE 38. ACKNOWLEDGE RESPONSE FROM RECEIVER

81 9

Serial Stop Condition

All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH, followed by a HIGH to LOW transition of SCL. The
stop condition is also used to place the device into the
Standby power mode after a read sequence.

Serial Acknowledge

Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to acknowledge that it received the eight bits
of data (See Figure 38).

The device will respond with an acknowledge after
recognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave Address
Byte. If a write operation is selected, the device will respond
with an acknowledge after the receipt of each subsequent
eight bit word. The device will acknowledge all incoming data
and address bytes, except for the Slave Address Byte when
the Device Identifier and/or Select bits are incorrect.

In the read mode, the device will transmit eight bits of data,
release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop

Device Addressing

Addressing Protocol Overview

Depending upon the operation to be performed on each of
these individual parts, a 1, 2 or 3 Byte protocol is used. All
operations however must begin with the Slave Address Byte
being clocked into the SMBus port on the SCL and SDA
pins. The Slave address selects the part of the device to be
addressed, and specifies if a Read or Write operation is to
be performed.

Slave Address Byte

Following a START condition, the master must output a
Slave Address Byte. This byte consists of three parts:

• The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4). The

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Device Type Identifier MUST be set to 1010 in order to
select the device.

• The next two bits (SA3 - SA2) are slave address bits. The
bits received via the SMBus are compared to A0 and A1
pins and must match or the communication is aborted.

• The next bit, SA1, selects the device memory sector.
There are two addressable sectors: the memory array and
the control, fault detection and remote shutdown registers.

• The Least Significant Bit of the Slave Address (SA0) Byte
is the R/W bit. This bit defines the operation to be
performed. When the R/W bit is “1”, then a READ
operation is selected. A “0” selects a WRITE operation
(Refer to Figure 39).

DEVICE TYPE

IDENTIFIER

SA6SA7

SA5

101

INTERNAL

ADDRESS (SA1)

0EEPROM Array

1 Control Register,

BIT SA0 OPERATION

0WRITE

1 READ

FIGURE 39. SLAVE ADDRESS FORMAT

EXTERNAL

DEVICE

ADDRESS

SA3 SA2

SA4

A1 A0 MS

0

INTERNALLY ADDRESSED

Fault Detection Register,

Remote Shutdown Register

DEVICE

Memory
Select

SA1

READ /
WRITE

SA0

R/W

Serial Write Operations

In order to perform a write operation to either a Control
Register or the EEPROM array, the Write Enable Latch
(WEL) bit must first be set.

Writes to the WEL bit do not cause a high voltage write
cycle, so the device is ready for the next operation
immediately after the stop condition.

Byte Write

For a write operation, the device requires the Slave Address
Byte and a Word Address Byte. This gives the master
access to any one of the words in the array. After receipt of
the Word Address Byte, the device responds with an
acknowledge, and awaits the next eight bits of data. After
receiving the 8 bits of the Data Byte, the device again
responds with an acknowledge. The master then terminates
the transfer by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile

memory. During this internal write cycle, the device inputs
are disabled, so the device will not respond to any requests
from the master. The SDA output is at high impedance.

A write to a protected block of memory will suppress the
acknowledge bit.

Page Write

The device is capable of a page write operation (See Figure

40). It is initiated in the same manner as the byte write
operation; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit an
unlimited number of 8-bit bytes. After the receipt of each
byte, the device will respond with an acknowledge, and the
address is internally incremented by one. The page address
remains constant. When the counter reaches the end of the
page, it “rolls over” and goes back to ‘0’ on the same page
(See Figure 41).

This means that the master can write 16 bytes to the page
starting at any location on that page. If the master begins
writing at location 10, and loads 12 bytes, then the first 6
bytes are written to locations 10 through 15, and the last 6
bytes are written to locations 0 through 5. Afterwards, the
address counter would point to location 6 of the page that
was just written. If the master supplies more than 16 bytes of
data, then new data overwrites the previous data, one byte
at a time.

The master terminates the Data Byte loading by issuing a
stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation, all
inputs are disabled until completion of the internal write
cycle.

Stop and Write Modes

Stop conditions that terminate write operations must be sent
by the master after sending at least 1 full data byte plus the
subsequent ACK signal. If a stop is issued in the middle of a
data byte, or before 1 full data byte plus its associated ACK
is sent, then the device will reset itself without performing the
write. The contents of the array will not be effected.

Acknowledge Polling

The disabling of the inputs during high voltage cycles can be
used to take advantage of the typical 5ms write cycle time.
Once the stop condition is issued to indicate the end of the
master’s byte load operation, the device initiates the internal
high voltage cycle. Acknowledge polling can be initiated
immediately. To do this, the master issues a start condition
followed by the Slave Address Byte for a write or read
operation. If the device is still busy with the high voltage
cycle then no ACK will be returned. If the device has
completed the write operation, an ACK will be returned and
the host can then proceed with the read or write operation
(See Figure 44).

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S

Signals from

the Master

SDA Bus

Signals from

the Slave

t

a

r
t

1010

Slave

Address

Byte

Address

0

A
C
K

Data

(1)

A
C
K

FIGURE 40. PAGE WRITE OPERATION

7 Bytes

address

= 6

address pointer
ends here

Addr = 7

address

10

FIGURE 41. WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 10

Signals from

the Master

SDA Bus

Signals from

the Slave

S

t

Slave

a

Address

r

t

1010 1010

0

A
C
K

Byte

Address

S

Slave

t

Address

a

r
t

A
C
K

(1 to n to 16)

A
C
K

5 Bytes

1

A
C
K

Data

(n)

address

n-1

Data

S

t
o
p

A
C
K

S

t
o
p

FIGURE 42. RANDOM ADDRESS READ SEQUENCE

S

Signals from

the Master

SDA Bus

Signals from

the Slave

t

Slave Address

a
r
t

1010

1

A
C
K

Data

FIGURE 43. CURRENT ADDRESS READ SEQUENCE

34

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o
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Byte Load Completed by

Issuing STOP.

Enter ACK Polling

Issue START

X80000, X80001

Current Address Read

Internally the device contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n+1. On
power up, the address of the address counter is undefined,
requiring a read or write operation for initialization.

Issue Slave Address
Byte (Read or Write)

ACK

Returned?

YES

High Voltage Cycle

Complete. Continue

Command Sequence?

YES

Continue Normal Read

or Write Command

Sequence

PROCEED

FIGURE 44. ACKNOWLEDGE POLLING SEQUENCE

Issue STOP

NO

Issue STOP

NO

Serial Read Operations

Read operations are initiated in the same manner as write
operations with the exception that the R/W
Address Byte is set to one. There are three basic read
operations: Current Address Reads, Random Reads, and
Sequential Reads.

bit of the Slave

Upon receipt of the Slave Address Byte with the R/W

bit set
to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond with
an acknowledge during the ninth clock and then issues a
stop condition. See Figure 43 or the address, acknowledge,
and data transfer sequence.

Operational Notes

The device powers-up in the following state:

• The device is in the low power standby state.

• The WEL bit is set to ‘0’. In this state, it is not possible to

write to the device.

• SDA pin is the input mode.

Data Protection

The following circuitry has been included to prevent
inadvertent writes:

• The WEL bit must be set to allow write operations.

• The proper clock count and bit sequence is required prior

to the stop bit in order to start a nonvolatile write cycle.

Random Read

Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W

bit set to one, the master must
first perform a “dummy” write operation. The master issues
the start condition and the Slave Address Byte, receives an
acknowledge, then issues the Word Address Bytes. After
acknowledging receipts of the Word Address Bytes, the
master immediately issues another start condition and the
Slave Address Byte with the R/W

bit set to one. This is
followed by an acknowledge from the device and then by the
eight bit word. The master terminates the read operation by
not responding with an acknowledge and then issuing a stop
condition. See Figure 42 for the address, acknowledge, and
data transfer sequence.

35

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Packaging Information

0.007 (0.19)

0.009 (0.25)

0.000 (0.00)

0.002 (0.05)

X80000, X80001

32-Lead Very Very Thin Quad Flat No Lead Package

7mm x 7mm Body with 0.65mm Lead Pitch

0.185

(4.70)

0.009 (0.23)

0.015 (0.38)

0.025 (0.65) BSC

0.027 (0.70)

0.031 (0.80)

0.000 (0.00)

0.030 (0.76)

0.271 (6.90)

0.279 (7.10)

PIN 1 INDENT

0.185
(4.70)

(4.70)

0.014 (0.35)

0.029 (0.75)

36

0.271 (6.90)

0.279 (7.10)

FN8148.0

March 18, 2005

X80000, X80001

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

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