intersil X55060 DATA SHEET

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X55060

64K

PRELIMINARY

Data Sheet March 28, 2005

Dual Voltage Monitor with Integrated
System Battery Switch and EEPROM

FEATURES

• Dual voltage monitoring

• Active high and active low reset outputs

• Four standard reset threshold voltages
(4.6/2.9, 4.6/2.6, 2.9/1.6, 2.6/1.6)
—User programmable thresholds

• Lowline Output — Zero delayed POR

• Reset signal valid to V

• System battery switch-over circuitry

• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<30µA max standby current, watchdog off

• Selectable watchdog timer
—(0.15s, 0.4s, 0.8s, off)

• 64Kbits of EEPROM

• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect none(0), or all of EEPROM array with

programmable Block Lock

CC

= 1V

™

protection

FN8133.0

—In circuit programmable ROM mode

• Minimize EEPROM programming time
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)

• 10MHz SPI interface modes (0,0 & 1,1)

• 2.7V to 5.5V power supply operation

• Available packages — 20-lead TSSOP

DESCRIPTION

This device combines power-on reset control, battery
switch circuit, watchdog timer, supply voltage supervi­sion, secondary voltage supervision, block lock

protect
and serial EEPROM in one package. This combination
lowers system cost, reduces board space require­ments, and increases reliability.

Applying power to the device activates the power-on
reset circuit which holds RESET

/RESET active for a
period of time. This allows the power supply and oscilla­tor to stabilize before the processor can execute code.

BLOCK DIAGRAM

V2MON

WP

SO

SI

SCK

CS

V

OUT

V

BATT

V

CC

(V1MON)

Watchdog Transition

Detector

Data

Register

Command

Decode, Test

& Control

Logic

System

Battery
Switch

V2 Monitor

X-Decoder

VCC Monitor

Logic

Logic

+

V

TRIP2

-

Protect Logic

Status

Register

EEPROM Array

512 X 128

V

+

V

TRIP1

-

OUT

V

OUT

Watchdog

Timer Reset

Reset &

Watchdog

Timebase

Power-on,

Low Voltage

Reset

Generation

V2FAIL

WDO

RESET

BATT-ON

RESET/MR

LOWLINE

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2005. All Rights Reserved

X55060

A system battery switch circuit compares VCC (V1MON)
with V

input and connects V

BATT

to whichever is

OUT

higher. This provides voltage to external SRAM or other
circuits in the event of main power failure. The X55060
can drive 50mA from V
device switches to V
low V

voltage threshold and V

CC

and 250µA from V

CC

when VCC drops below the

BATT

BATT

> VCC.

BATT

. The

The Watchdog Timer provides an independent protec­tion mechanism for microcontrollers. When the micro­controller fails to restart a timer within a selectable
time out interval, the device activates the WDO

signal.
The user selects the interval from th ree preset v alues.
Once selected, the interval does not change, even
after cycling the power.

The device’s low V

detection circuitry protects the

CC

user’s system from low voltage conditions, resetting the
system when V
V

trip point (V

CC

V

returns to proper operating level and stabilizes. A

CC

(V1MON) falls below the minimum

CC

). RESET/RESET is asserted until

TRIP1

second voltage monitor circuit tracks the unregulated

PIN CONFIGURATION

20-Pin TSSOP

supply or monitors a second power supply voltage to
provide a power fail warning. Intersil’s unique circuits
allow the threshold for either voltage monitor to be
reprogrammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.

ORDERING INFORMATION

X55060

Suffix Vtrip1 Vtrip2 Temp Range

V20-4.5A

V20I-4.5A -40°C to 85°C

V20-4.5

V20I-4.5 -40°C to 85°C

V20-2.7A

V20I-2.7A -40°C to 85°C

V20-2.7

V20I-2.7 -40°C to 85°C

4.6 2.6

4.6 2.9

2.9 1.65

2.6 1.65

0°C to 70°C

0°C to 70°C

0°C to 70°C

0°C to 70°C

CS/WDI

NC
SO

RESET

LOWLINE

V2FAIL

V2MON

WP

NC

VSS

1
2

3
4

5
6

7
8

9
10

20
19

18
17

16
15

14
13

12
11

V

(V1MON)

CC

WDO

/MR

RESET
BATT-ON
V

OUT

V

BATT

SCK
NC
NC
SI

2

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X55060

PIN DESCRIPTION

Pin Name Function

1CS

2 NC No internal connections
3SOSerial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The

4 RESET Reset Output.

5LOWLINE

6V2FAIL

7V2MONV2 Voltage Monitor Input. When the V2MON input is less than the V

8WP

9 NC No internal connections
10 V
11 SI Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on

12 NC No internal connections
13 NC No internal connections
14 SCK Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising

15 V

/WDI

SS

BATT

Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance

state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.

LOW enables the device, placing it in the active power mode. Prior to the start of any opera-

CS
tion after power-up, a HIGH to LOW transition on CS

is required.

Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in RESET
going active.

falling edge of the serial clock (SCK) clocks the data out.

RESET is an active HIGH, open drain output which is the inverse of the RESET

output.

Low V

immediately goes HIGH when V

Detect. This open drain output signal goes LOW when VCC < V

CC

CC

> V

. This pin goes LOW 250ns before RESET pin.

TRIP1

TRIP1

and

V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V
and goes HIGH when V2MON exceeds V

. There is no power-up reset delay circuitry on this

TRIP2

pin.

voltage, V2FAIL goes

TRIP2

LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V

SS

when not used.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting

of the Watchdog Timer control and the memory write protect bits.

Ground

this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.

edge of SCK latches in the opcode, address, or data bits present on t he SI pin. The falling e dge of
SCK changes the data output on the SO pin.

Battery Supply Voltage. This input provides a backup supply in the event of a failure of the pri­mary V

voltage. The V

CC

voltage typically provides the supply voltage necessary to maintain

BATT

the contents of SRAM and also powers the internal logic to “stay awake.” If unused connect
V

to ground.

BATT

/RESET

TRIP2

or VCC

3

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PIN DESCRIPTION (CONTINUED)

Pin Name Function

16 V

OUT

17 BATT-ON Battery On. This open drain output goes HIGH when the V

18 RESET

/MR

19 WDO

20 V

CC

(V1MON)

Output Voltage. V

< V

IF V

CC

TRIP1

= VCC if VCC > V

V

OUT

V

OUT

= V

BATT

if VCC < V

Note: There is hysteresis around V

= VCC if VCC > V

OUT

, then,

BATT

BATT

+0.03

-0.03

.

TRIP1

± 0.03V point to avoid oscillation at or near the

BATT

switchover voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability.

when V

switches to VCC. It is used to drive an external PNP pass transistor when VCC = V

OUT

and current requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when

the V
the V

supply is fully functional. In the event of a VCC failure, the battery voltage is applied to

CC

pin and the external transistor is turned off. In this “backup condition,” the battery only

OUT

needs to supply enough voltage and current to keep SRAM devices from losing their data-there
is no communication at this time.

Output/Manual Reset Input. This is an Input/Output pin.
RESET

below the minimum V
rupted. RESET
RESET

Output. This is an active LOW, open drain output which goes active whenever VCC falls

sense level. When RESET is active communication to the device is inter-

CC

remains active until VCC rises above the minimum VCC sense level for 150ms.

also goes active on power-up and remains active for 150ms after the power supply

stabilizes.

Input. This is an active LOW debounced input. When MR is active, the RESET/RESET pins

MR

are asserted. When MR

is released, the RESET/RESET remains asserted for t

leased.
Watchdog Output. WDO is an active low, open drain output which goes active whenever the

watchdog timer goes active. WDO

remains active for 150ms, then returns to the inactive state.

Supply Voltage/V1 Voltage Monitor Input. When the V1MON input is less than the VTRIP1
voltage, RESET and RESET go ACTIVE.

switches to V

OUT

and goes LOW

BATT

, and then re-

PURST

OUT

PRINCIPLES OF OPERATION

Power-On Reset

Application of power to the X55060 activates a Power­on Reset Circuit. This circuit goes active at about 1V
and pulls the RESET

/RESET pin active. This signal
prevents the system microprocessor from starting to
operate with insufficient voltage or prior to stabilization
of the oscillator. When V

exceeds the device V

CC

TRIP1

value for 150ms (nominal) the circuit releases
RESET

/RESET, allowing the processor to begin exe-

cuting code.

Low V

During operation, the X55060 monitors the V
and asserts RESET
below a preset minimum V

(V1MON) Voltage Monitoring

CC

/RESET if supply voltage falls

. During this time the

TRIP1

CC

level

communication to the device is interrupted. The

RESET

/RESET signal also prevents the microproces­sor from operating in a power fail or brownout condi­tion. The RESET

signal remains active until the
voltage drops below 1V. These also remain active until
V

returns and exceeds V

CC

TRIP1

for t

PURST

.

Low V2MON Voltage Monitoring

The X55060 also monitors a second voltage level and
asserts V2FAIL
mum V
RESET

TRIP2

to prevent the microprocessor from operating

if the voltage falls below a preset mini-

. The V2FAIL signal is either ORed with

in a power fail or brownout condition or used to inter­rupt the microprocessor with notification of an impend­ing power failure. V2FAIL
returns and exceeds V

The V2MON voltage sensor is powered by V
V

CC

and V

go away (i.e. V

BATT

remains active until V2MON

.

TRIP2

goes away), then

OUT

OUT

. If

V2MON cannot be monitored.

4

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Figure 1. Two Uses of Dual Voltage Monitoring

V

OUT

Unregulated

Supply

R1

R2

V2

5V

Reg

X55060

V

CC

RESET

V2MON

V2FAIL

X55060

System
Reset

System
Interrupt

Unregulated

Supply

5V

Reg

3.3V
Reg

X55060

V

CC

V2MON

RESET

V2FAIL

V

OUT

System
Reset

R1 and R2 selected so V2 = V2MON threshold when
Unregulated supply reaches 6V.

Watchdog Timer

The Watchdog Timer circuit monitors the microproces­sor activity by monitoring the CS/
processor must toggle the CS /

WDI pin. The micro-

WDI pin HIGH to LOW
periodically prior to the expiration of the watchdog time
out period to prevent the WDO

signal going active.
The state of two nonvolatile control bits in the Status
Register determines the watchdog timer period. The
microprocessor can change these watchdog bits by
writing to the status register. The factory default set­ting disables the watchdog timer.

The Watchdog Timer oscillator stops when in battery
backup mode. It re-starts when V

returns.

CC

System Battery Switch

As long as V
old V

TRIP1

(typical) switch. When the V
then V

CC

greater than V
than V

BATT

through an 80Ω (typical) switch. V

exceeds the low voltage detect thresh-

CC

, V

is applied to V

is connected to VCC through a 5Ω

OUT

+ 0.03V. When VCC drops to less

BATT

- 0.03V, then V

has fallen below V

CC

if VCC is equal to or

OUT

is connected to V

OUT

typically sup-

OUT

TRIP

BATT

plies the system static RAM voltage, so the switchover
circuit operates to protect the contents of the static
RAM during a power failure. Typically, when V

CC

has
failed, the SRAMs go into a lower power state and
draw much less current than in their active mode.
When V
V

CC

returns, V

CC

exceeds V

switches back to VCC when

OUT

+ 0.03V. There is a 60mV hyster-

BATT

esis around this battery switch threshold to prevent
oscillations between supplies.

Notice: No external components required to monitor
two voltages.

While V

is connected to V

CC

the BATT-ON pin is

OUT

pulled LOW. The signal can drive an external PNP
transistor to provide additional current to the external
circuits during normal operation.

Operation

The device is in normal operation with V
V

> V

CC

when V

. It switches to the battery backup mode

TRIP1

goes away.

CC

as long as

CC

Condition Mode of Operation

VCC > V
V

> V

CC

= 0

V

BATT

0 ≤ V

CC VTRIP1

and V

CC

TRIP1
TRIP1

< V

&

BATT

Normal Operation.
Normal Operation without battery

back up capability.
Battery Backup Mode; RESET

signal is asserted. No communica­tion to the device is allowed.

,

5

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X55060

Manual Reset

By connecting a push-button from MR

to ground or
driven by logic, the designer adds manual system reset
capability. The RESET/RESET
the push-button is closed and remain asserted for t

pins are asserted when

PURST

after the push-button is released. This pin is debounced
so a push-button connected directly to the device will
have both clean falling and rising edges on MR

V

(V1MON), V2MON Threshold Programming

CC

.

Procedure

The X55060 is shipped with standard V
and V2MON threshold (V

TRIP1

, V

CC

TRIP2

(V1MON)

) voltages.
These values will not change over normal operating
and storage conditions. However, in applications where
the standard thresholds are not exactly right, or if higher
precision is needed in the threshold value, the X55060
trip points may be adjusted. The procedure is described
below, and uses the application of a high voltage con­trol signal.

Setting the V

This procedure is used to set the V

TRIP

Voltage

TRIP1

or V

TRIP2

to a
lower or higher voltage value. It is necessary to reset
the trip point before setting the new value to a lower
level.

To set the new voltage, apply the desired V
threshold voltage to the VCC pin or the V
to the V2MON pin (when setting V

TRIP2

, VCC should

TRIP2

be same voltage as V2MON). Next, tie the WP

TRIP1

voltage

pin to

the programming voltage V

. Then, send the WREN

P

command and write to address 01h or to add ress 0Bh
to program V
data byte 00h). The CS

TRIP1

or V

, respectively (followed by

TRIP2

going high after a valid write
operation initiates the programming sequence. Bring
WP

LOW to complete the operation.

To check if the V
higher than V

TRIPX

has been set, apply a voltage

TRIPX

to the VXMON (x = 1, 2) pin. Dec­rement VXMON in small steps and observe where the
output switches. The voltage at which this occurs is
the V

C

ASE A

If the V
(desired), then add the difference between V
(desired) and V
(desired). This is your new V

TRIPX

(actual).

(actual) is lower than the V

TRIPX

(actual) to the original V

TRIPX

voltage that should

TRIPX

TRIPX
TRIPX
TRIPX

be applied to VXMON and the whole sequence
repeated again (see Fig 6).

C

ASE B

If the V

(actual) is higher than the V

TRIPX

TRIPX

(desired), perform the reset sequence as described in
the next section. The new V
to VXMON will now be: V
(desired) - V

TRIPX

(actual)).

voltage to be applied

TRIPX

(desired) - (V

TRIPX

TRIPX

Note: This operation will not alter the contents of the
EEPROM.

Figure 2. Example System Connection

Unregulated

Supply

5V

Reg

+

V

CC

V

BATT

V2MON

V

SS

BATT-ON

V

OUT

V2FAIL

RESET

CS, SCK

SI, SO

PNP transistor
or P-channel FET

V

OUT

Address

Decode

Enable

SRAM

Addr

NMI

RESET
SPI

µC

V

CC

6

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March 28, 2005

X55060

Resetting the V

To reset V

TRIP1

(V1MON). To reset V
both V

and V2MON. Next, tie the WP pin to the

CC

programming voltage V

Voltage

TRIP

, apply greater than 3V to V

, apply greater than 3V to

TRIP2

. Then send the WREN

P

CC

command and write to address 03h or 0Dh to reset th e
V

or V

TRIP1

Figure 3. Set V

WP

CS

SCK

SI

respectively (followed by data byte

TRIP2

Level Sequence

TRIPX

01234567 0123456

06h

WREN

WRITE

VP = 10-15V

02h

00h). The CS

going LOW to HIGH after a valid write
operation initiates the programming sequence. Bring
WP

LOW to complete the operation.

Note: This operation does not change the contents of
the EEPROM array.

78910 202122 23

16 Bits

0001h/000Bh

ADDRESS
Addr 01h: Set V
Addr 0Bh: Set V

TRIP1

TRIP2

00h

DATA

Figure 4. Reset V

WP

CS

01234567 0123456

SCK

SI

Level Sequence

TRIPX

06h

WREN

VP = 10-15V

02h

WRITE

78910 202122 23

16 Bits

0003h/000Dh

ADDRESS
Addr 03h: Reset V
Addr 0Dh: Reset V

00h

DATA

TRIP1

TRIP2

7

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