intersil X5168, X5169 DATA SHEET

查询X5165V14Z供应商

X5168, X5169

(Replaces X25268, X25169)

Data Sheet September 16, 2005

CPU Supervisor with 16Kbit SPI EEPROM

These devices combine three popular functions, Power-on Reset Control, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability.

Applying power to the device activates the power-on reset circuit which holds RESET time. This allows the power supply and oscillator to stabilize before the processor can execute code.

The device’s low V

system from low voltage conditions by holding RESET

/RESET active when VCC falls below a minimum VCC

trip point. RESET

/RESET remains asserted until VCC returns to proper operating level and stabilizes. Five industry standard V

thresholds are available, however, Intersil’s

TRIP

unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold in applications requiring higher precision.

/RESET active for a period of

detection circuitry protects the user’s

FN8130.1

Features

•Low VCC Detection and Reset Assertion

- Five standard reset threshold voltages

- Re-program low V special programming sequence

- Reset signal valid to V

• Long Battery Life with Low Power Consumption

- <50µA max standby current, watchdog on

- <1µA max standby current, watchdog off

- <400µA max active current during read

• 16Kbits of EEPROM

• Built-in Inadvertent Write Protection

- Power-up/power-down protection circuitry

- Protect 0, 1/4, 1/2 or all of EEPROM array with Block

™

protection

Lock

- In circuit programmable ROM mode

• 2MHz SPI Interface Modes (0,0 & 1,1)

• Minimize EEPROM Programming Time

- 32-byte page write mode

- Self-timed write cycle

- 5ms write cycle time (typical)

• 2.7V to 5.5V and 4.5V to 5.5V Power Supply Operation

• Available Packages

- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP

• Pb-Free Plus Anneal Available (RoHS Compliant)

reset threshold voltage using

= 1V

Block Diagram

SCK

Data

Command

Decode &

Control

Logic

TRIP

Protect Logic

Status

4Kbits 4Kbits

8Kbits

Reset

Timebase

Power-on and

Low Voltage

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Reset

Generation

EEPROM Array

RESET/RESET

X5168 = RESET X5169 = RESET

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X5168, X5169

Ordering Information

PAR T N UM BE R

RESET

(ACTIVE LOW)

X5168P-4.5A X5168P AL X5169P-4.5A X5169P AL 4.5-5.5 4.5.4.75 0 to 70 8 Ld PDIP

- - X5169PZ-4.5A 8 Ld PDIP

X5168PI-4.5A X5169PI-4.5A -40 to 85 8 Ld PDIP

- - X5169PIZ-4.5A X5169P Z AM 8 Ld PDIP

X5168S8-4.5A X5168 AL X5169S8-4.5A X5169 AL 0 to 70 8 Ld SOIC

X5168S8Z-4.5A X5168 Z AL X5169S8Z-4.5A X5169 Z AL 8 Ld SOIC

X5168S8I-4.5A* X5168 AM X5169S8I-4.5A X5169 AM -40 to 85 8 Ld SOIC

X5168S8IZ-4.5A* X5168 Z AM X5169S8IZ-4.5A X5169 Z AM 8 Ld SOIC

X5168V14-4.5A X5169V14-4.5A 0 to 70 14 Ld TSSOP

X5168V14I-4.5A X5169V14I-4.5A -40 to 85 14 Ld TSSOP

X5168P X5168P X5169P X5169P 4.5-5.5 4.25.4.5 0 to 70 8 Ld PDIP

- - X5169PZ X5169P Z 8 Ld PDIP

X5168PI X5168P I X5169PI X5169P I -40 to 85 8 Ld PDIP

- - X5169PIZ X5169P Z I 8 Ld PDIP

X5168S8* X5168 X5169S8* X5169 0 to 70 8 Ld SOIC

X5168S8Z* X5168 Z X5169S8Z* X5169 Z 8 Ld SOIC

X5168S8I* X5168 I X5169S8I* X5169 I -40 to 85 8 Ld SOIC

X5168S8IZ* X5168 Z I X5169S8IZ* X5169 Z I 8 Ld SOIC

X5168V14* X5168V X5169V14* X5169V 0 to 70 14 Ld TSSOP

X5168V14I* X5169V14I* -40 to 85 14 Ld TSSOP

X5168P-2.7A X5169P-2.7A 2.7-5.5 2.85-3.0 0 to 70 8 Ld PDIP

- - X5169PZ-2.7A X5169P Z AN 8 Ld PDIP

X5168PI-2.7A X5169PI-2.7A -40 to 85 8 Ld PDIP

- - X5169PIZ-2.7A X5169P Z AP 8 Ld PDIP

X5168S8-2.7A* X5168 AN X5169S8-2.7A X5169 AN 0 to 70 8 Ld SOIC

X5168S8Z-2.7A* (Note) X5168 Z AN X5169S8Z-2.7A X5169 Z AN 8 Ld SOIC

X5168S8I-2.7A X5169S8I-2.7A -40 to 85 8 Ld SOIC

X5168S8IZ-2.7A X5168 Z AP X5169S8IZ-2.7A X5169 Z AP 8 Ld SOIC

X5168V14-2.7A X5169V14-2.7A 0 to 70 14 Ld TSSOP

X5168V14I-2.7A* X5169VI14-2.7A -40 to 85 14 Ld TSSOP

X5168P-2.7 X5169P-2.7 2.7-5.5 2.55-2.7 0 to 70 8 Ld PDIP

- - X5169PZ-2.7 X5169P Z F 8 Ld PDIP

X5168PI-2.7 X5169PI-2.7 -40 to 85 8 Ld PDIP

- - X5169PIZ-2.7 X5169P Z G 8 Ld PDIP

X5168S8-2.7* X5168 F X5169S8-2.7* X5169 F 0 to 70 8 Ld SOIC

X5168S8Z-2.7* X5168 Z F X5169S8Z-2.7* X5169 Z F 8 Ld SOIC

X5168S8I-2.7* X5168 G X5169S8I-2.7* X5169 G -40 to 85 8 Ld SOIC

X5168S8IZ-2.7* X5168 Z G X5169S8IZ-2.7* X5169 Z G 8 Ld SOIC

X5168V14-2.7* X5169V14-2.7* 0 to 70 14 Ld TSSOP

X5168V14I-2.7 X5169V14I-2.7* -40 to 85 14 Ld TSSOP

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

*Add "-T1" suffix for tape and reel.

PAR T

MARKING

PART NUMBER

RESET

(ACTIVE HIGH)

PART

MARKING

RANGE

(V)

TRIP

RANGE (V)

TEMP RANGE

(°C) PACKAGE

Tape and Reel (Pb-free)

FN8130.1

September 16, 2005

X5168, X5169

Pin Configuration

14 LD TSSOP

CS SO

8 LD SOIC/PDIP

X5168/69

2 3

SO NC

NC NC WP

7 6

RESET/RESET

SCK SI

1 2

3 4

5 6 7

X5168/69

Pin Description

(SOIC/PDIP) PIN TSSOP NAME FUNCTION

11CSChip Select Input.

pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS to the start of any operation after power-up, a HIGH to LOW transition on CS

22SOSerial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The

falling edge of the serial clock (SCK) clocks the data out.

58SISerial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this

pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first.

69SCKSerial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge

of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin.

36WPWrite Protect. The WP

of the watchdog timer control and the memory write protect bits.

47V

814V

7 13 RESET

RESET

Ground

Supply Voltage

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever V the minimum V enabled and CS period. A falling edge of CS up at about 1V and remains active for 200ms after the power supply stabilizes.

3-5,10-12 NC No internal connections

CS HIGH, deselects the device and the SO output

LOW enables the device, placing it in the active power mode. Prior

pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting

falls below the minimum VCC sense level. It will remain active until VCC rises above

sense level for 200ms. RESET/RESET goes active if the watchdog timer is

remains either HIGH or LOW longer than the selectable watchdog time out

will reset the watchdog timer. RESET/RESET goes active on power-

14 13 12 11

/RESET

RESET NC NC

NC SCK

is required.

FN8130.1

September 16, 2005

X5168, X5169

Principles of Operation

Power-on Reset

Application of power to the X5168, X5169 activates a poweron reset circuit. This circuit goes active at about 1V and pulls the RESET system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When V (nominal) the circuit releases RESET processor to begin executing code.

Low Voltage Monitoring

During operation, the X5168, X5169 monitors the VCC level and asserts RESET preset minimum V the microprocessor from operating in a power fail or brownout condition. The RESET active until the voltage drops below 1V. It also remains active until V

VCC Threshold Reset Procedure

The X5168, X5169 has a standard VCC threshold (V voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard V the V adjusted.

/RESET pin active. This signal prevents the

exceeds the device V

value for 200ms

TRIP

/RESET, allowing the

/RESET if supply voltage falls below a

. The RESET/RESET signal prevents

TRIP

/RESET signal remains

returns and exceeds V

is not exactly right, or for higher precision in

TRIP

value, the X5168, X5169 threshold may be

TRIP

for 200ms.

TRIP

)

Resetting the V

This procedure sets the V example, if the current V the new V

is something less than 1.7V. This procedure

TRIP

Voltage

to a “native” voltage level. For

TRIP

is 4.4V and the V

TRIP

must be used to set the voltage to a lower value.

To reset the V

5.5V to the Vcc pin. Tie the CS

pin HIGH. RESET Then apply the programming voltage V and pulse CS

voltage, apply a voltage between 2.7 and

TRIP

pin, the WP pin, and the SCK

/RESET and SO pins are left unconnected.

to the SI pin ONLY

LOW then HIGH. Remove VP and the

sequence is complete.

SCK

FIGURE 2. RESET V

VOLTAGE

TRIP

is reset,

Setting the V

This procedure sets the V example, if the current V

TRIP

Voltage

TRIP

to a higher voltage value. For

is 4.4V and the new V

TRIP

4.6V, this procedure directly makes the change. If the new setting is lower than the current setting, then it is necessary to reset the trip point before setting the new value.

To set the new V threshold to the V HIGH. RESET Then apply the programming voltage V and pulse CS

voltage, apply the desired V

TRIP

pin and tie the CS pin and the WP pin

TRIP

/RESET and SO pins are left unconnected.

to both SCK and SI

LOW then HIGH. Remove VP and the

sequence is complete.

SCK

FIGURE 1. SET V

VOLTAGE

TRIP

FN8130.1

September 16, 2005

X5168, X5169

Programming

TRIP

Execute

Reset V

TRIP

Sequence

Set VCC = VCC Applied =

Desired V

TRIP

New VCC Applied =

Old V

Applied + Error

Error ≥ Emax

Emax = Maximum Desired Error

Execute

Set V

Sequence

Apply 5V to V

Decrement V

= VCC - 10mV)

RESET pin

goes active?

Measured V

Desired V

DONE

TRIP

YES

TRIP

Error = 0

New VCC Applied =

Applied - Error

Old V

Execute

Reset V

TRIP

Sequence

Error > Emax

TRIP

Adj.

Program

4.7K

FIGURE 3. V

FIGURE 4. SAMPLE V

PROGRAMMING SEQUENCE FLOW CHART

TRIP

1 2 3 4

X5168/

X5169

8 7 6 5

10K

RESET CIRCUIT

TRIP

10K

4.7K RESET

Reset V Test V Set V

TRIP

FN8130.1

September 16, 2005

X5168, X5169

SPI Serial Memory

The memory portion of the device is a CMOS serial EEPROM array with Intersil’s block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.

The device utilizes Intersil’s proprietary Direct Write providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.

The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. It contains an 8-bit instruction register that is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS

™

cell,

must be

Write Enable Latch

The device contains a write enable latch. This latch must be SET before a write operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 3). This latch is automatically reset upon a power-up condition and after the completion of a valid write cycle.

Status Register

The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows:

7 65 4 3210

WPEN FLB 0 0 BL1 BL0 WEL WIP

LOW during the entire operation.

The Write-In-Progress (WIP) bit is a volatile, read only bit

All instructions (Table 1), addresses and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS

goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume

and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a “1”, a nonvolatile write operation is in progress. When set to a “0”, no write is in progress.

operations where left off.

TABLE 1. INSTRUCTION SET

INSTRUCTION NAME INSTRUCTION FORMAT* OPERATION

WREN 0000 0110 Set the write enable latch (enable write operations)

SFLB 0000 0000 Set flag bit

WRDI/RFLB 0000 0100 Reset the write enable latch/reset flag bit

RSDR 0000 0101 Read status register

WRSR 0000 0001 Write status register (watchdog, block lock, WPEN & flag bits)

READ 0000 0011 Read data from memory array beginning at selected address

WRITE 0000 0010 Write data to memory array beginning at selected address

Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

TABLE 2. BLOCK PROTECT MATRIX

WREN CMD STATUS REGISTER DEVICE PIN BLOCK BLOCK STATUS REGISTER

WPEN, BL0, BL1 WD0,

WEL WPEN WP# PROTECTED BLOCK UNPROTECTED BLOCK

0 X X Protected Protected Protected

1 1 0 Protected Writable Protected

1 0 X Protected Writable Writable

1 X 1 Protected Writable Writable

WD1

September 16, 2005

FN8130.1

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