intersil X5163, X5165 DATA SHEET

X5163, X5165

Data Sheet May 16, 2005

CPU Supervisor with 16Kbit SPI EEPROM

Description

These devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability.

Applying power to the device activates the power-on reset circuit which holds RESET time. This allows the power supply and oscillator to stabilize before the processor can execute code.

The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET the interval from three preset values. Once selected, the interval does not change, even after cycling the power.

The device’s low V

system from low voltage conditions, resetting the system when V

falls below the minimum VCC trip point. RESET/RESET is

asserted until V

returns to proper operating level and

stabilizes. Five industry standard V available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.

/RESET active for a period of

/RESET signal. The user selects

detection circuitry protects the user’s

thresholds are

TRIP

FN8128.1

Features

• Selectable watchdog timer

•Low V

- Five standard reset threshold voltages

- Re-program low V

- Reset signal valid to V

• Determine watchdog or low voltage reset with a volatile flag bit

• Long battery life with low power consumption

- <50µA max standby current, watchdog on

- <1µA max standby current, watchdog off

- <400µA max active current during read

• 16Kbits of EEPROM

• Built-in inadvertent write protection

- Power-up/power-down protection circuitry

- Protect 0, 1/4, 1/2 or all of EEPROM array with Block

- In circuit programmable ROM mode

• 2MHz SPI interface modes (0,0 & 1,1)

• Minimize EEPROM programming time

- 32-byte page write mode

- Self-timed write cycle

- 5ms write cycle time (typical)

• 2.7V to 5.5V and 4.5V to 5.5V power supply operation

• Available packages

- 14-lead TSSOP, 8-lead SOIC

detection and reset assertion

reset threshold voltage using

special programming sequence

= 1V

™

protection

Lock

Pinouts

CS/WDI

14-LEAD TSSOP

8-LEAD SOIC/PDIP

X5163, X5165

7 6

RESET

/RESET

SCK

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

CS/WDI

SO NC

NC NC

X5163, X5165

1 2

3 4

5 6

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

14 13

12 11

9 8

RESET NC NC NC SCK SI

/RESET

Block Diagram

X5163, X5165

SCK

/WDI

Watchdog Transition

Detector

Protect Logic

Data

Status

Command Decode &

Control

Logic

4K Bits

Watchdog

Timer Reset

Reset &

Watchdog

Timebase

VCC Threshold

Reset Logic

8K Bits

EEPROM Array

Power-on and

TRIP

Low Voltage

Reset

Generation

Pin Description

(SOIC/PDIP) PIN TSSOP NAME FUNCTION

1 1 CS/WDI Chip Select Input.

state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS

LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET

/RESET going active.

22SOSerial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The

falling edge of the serial clock (SCK) clocks the data out.

36WPWrite Protect. The WP

of the Watchdog Timer control and the memory write protect bits.

47V

Ground

58SISerial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this

pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first.

69SCKSerial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge

of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin.

7 13 RESET

RESET

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever V the minimum V RESET goes active if the Watchdog Timer is enabled and CS than the selectable Watchdog time out period. A falling edge of CS RESET

/RESET goes active on power-up at 1V and remains active for 200ms after the power

supply stabilizes.

814V

Supply Voltage

3-5,10-12 NC No internal connections

CS HIGH, deselects the device and the SO output pin is at a high impedance

pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting

falls below the minimum VCC sense level. It will remain active until VCC rises above

sense level for 200ms. RESET/

RESET/RESET

X5163 = RESET X5165 = RESET

is required

remains either HIGH or LOW longer

will reset the Watchdog Timer.

FN8128.1

May 16, 2005

X5163, X5165

Principles Of Operation

Power-on Reset

Application of power to the X516, /X5165 activates a Poweron Reset Circuit. This circuit goes active at 1V and pulls the RESET microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When V exceeds the device V circuit releases RESET begin executing code.

Low Voltage Monitoring

During operation, the X5163, X5165 monitors the VCC level and asserts RESET/RESET preset minimum V the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until V

Watchdog Timer

The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS RESET from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the Status Register determine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be “locked” by tying the WP the WPEN bit HIGH.

/RESET pin active. This signal prevents the system

value for 200ms (nominal) the

TRIP

/RESET, allowing the processor to

if supply voltage falls below a

. The RESET/RESET signal prevents

TRIP

returns and exceeds V

for 200ms.

TRIP

/WDI pin periodically to prevent a

/RESET signal. The CS/WDI pin must be toggled

pin LOW and setting

To set the new V threshold to the V pin HIGH. RESET apply the programming voltage V pulse CS

/WDI LOW then HIGH. Remove VP and the

voltage, apply the desired V

TRIP

pin and tie the CS/WDI pin and the WP

TRIP

and SO pins are left unconnected. Then

to both SCK and SI and

sequence is complete.

SCK

FIGURE 1. SET V

Resetting the V

TRIP

Voltage

This procedure sets the V example, if the current V the new V

is something less than 1.7V. This procedure

TRIP

VOLTAGE

TRIP

to a “native” voltage level. For

is 4.4V and the V

TRIP

must be used to set the voltage to a lower value.

To reset the V

5.5V to the V THE SCK pin HIGH. RESET

voltage, apply a voltage between 2.7 and

TRIP

pin. Tie the CS/WDI pin, the WP pin, AND

and SO pins are left unconnected. Then apply the programming voltage V SI pin ONLY and pulse CS

/WDI LOW then HIGH. Remove VP

and the sequence is complete.

is reset,

to the

VCC Threshold Reset Procedure

The X5163, X5165 has a standard VCC threshold (V voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard V the V

TRIP

is not exactly right, or for higher precision in

TRIP

value, the X5163, X5165 threshold may be

adjusted.

Setting the V

This procedure sets the V example, if the current V

TRIP

Voltage

TRIP

to a higher voltage value. For

is 4.4V and the new V

4.6V, this procedure directly makes the change. If the new setting is lower than the current setting, then it is necessary to reset the trip point before setting the new value.

TRIP

)

SCK

FIGURE 2. RESET V

VOLTAGE

TRIP

FN8128.1

May 16, 2005

X5163, X5165

PROGRAMMING

TRIP

EXECUTE

RESET V

TRIP

SEQUENCE

SET VCC = VCC APPLIED =

DESIRED V

TRIP

NEW VCC APPLIED =

APPLIED + ERROR

OLD V

ERROR > -EMAX

EMAX = MAXIMUM DESIRED ERROR

EXECUTE SET V

TRIP

SEQUENCE

APPLY 5V TO V

DECREMENT V

= VCC - 50MV)

RESET PIN

GOES ACTIVE?

YES

MEASURED V

DESIRED V

ERROR < EMAX

DONE

TRIP

–

NEW VCC APPLIED =

APPLIED - ERROR

OLD V

EXECUTE

RESET V

SEQUENCE

ERROR > EMAX

TRIP

ADJ.

PROGRAM

4.7K

FIGURE 3. V

FIGURE 4. SAMPLE V

PROGRAMMING SEQUENCE FLOW CHART

TRIP

X5163, X5165

1 2 3 4

8 7 6 5

10K

RESET CIRCUIT

TRIP

10K

4.7K RESET

RESET V TEST V SET V

TRIP

May 16, 2005

FN8128.1

X5163, X5165

SPI Serial Memory

The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.

The device utilizes Intersil’s proprietary Direct Write providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.

The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. It contains an 8-bit instruction register that is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS LOW during the entire operation.

All instructions (Table 1), addresses and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS

goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off.

INSTRUCTION NAME INSTRUCTION FORMAT* OPERATION

WREN 0000 0110 Set the Write Enable Latch (Enable Write Operations)

SFLB 0000 0000 Set Flag Bit

WRDI/RFLB 0000 0100 Reset the Write Enable Latch/Reset Flag Bit

RSDR 0000 0101 Read Status Register

WRSR 0000 0001 Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)

READ 0000 0011 Read Data from Memory Array Beginning at Selected Address

WRITE 0000 0010 Write Data to Memory Array Beginning at Selected Address

NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

™

cell,

must be

TABLE 1. INSTRUCTION SET

Write Enable Latch

The device contains a Write Enable Latch. This latch must be SET before a Write Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 7). This latch is automatically reset upon a power-up condition and after the completion of a valid Write Cycle.

Status Register

The RDSR instruction provides access to the Status Register. The Status Register may be read at any time, even during a Write Cycle. The Status Register is formatted as follows:

7 65 43210

WPEN FLB WD1 WD0 BL1 BL0 WEL WIP

The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a “1”, a nonvolatile write operation is in progress. When set to a “0”, no write is in progress.

TABLE 2. BLOCK PROTECT MATRIX

WREN CMD STATUS REGISTER DEVICE PIN BLOCK BLOCK STATUS REGISTER

WPEN, BL0, BL1, WD0,

WEL WPEN WP# PROTECTED BLOCK UNPROTECTED BLOCK

0 X X Protected Protected Protected

1 1 0 Protected Writable Protected

1 0 X Protected Writable Writable

1 X 1 Protected Writable Writable

WD1

FN8128.1

May 16, 2005

X5163, X5165

The Write Enable Latch (WEL) bit indicates the Status of the Write Enable Latch. When WEL = 1, the latch is set HIGH and when WEL = 0 the latch is reset LOW. The WEL bit is a volatile, read only bit. It can be set by the WREN instruction and can be reset by the WRDS instruction.

The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any portion of the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory.

STATUS

BL1 BL0 X516X

0 0 None

0 1 $0600-$07FF

1 0 $0400-$07FF

1 1 $0000-$07FF

The Watchdog Timer bits, WD0 and WD1, select the Watchdog Time Out Period. These nonvolatile bits are programmed with the WRSR instruction.

STATUS REGISTER BITS

0 0 1.4 seconds

0 1 600 milliseconds

WATCHDOG TIME OUT

(TYPICAL)WD1 WD0

STATUS REGISTER BITS

1 0 200 milliseconds

1 1 disabled

WATCHDOG TIME OUT

(TYPICAL)WD1 WD0

The FLAG bit shows the status of a volatile latch that can be set and reset by the system using the SFLB and RFLB instructions. The Flag bit is automatically reset upon powerup. This flag can be used by the system to determine whether a reset occurs as a result of a watchdog time out or power failure.

The nonvolatile WPEN bit is programmed using the WRSR instruction. This bit works in conjunction with the WP

pin to

provide an In-Circuit Programmable ROM function (Table

2). WP

is LOW and WPEN bit programmed HIGH disables

all Status Register Write Operations.

In Circuit Programmable ROM Mode

This mechanism protects the block lock and Watchdog bits from inadvertent corruption.

In the locked state (Programmable ROM Mode) the WP is LOW and the nonvolatile bit WPEN is “1”. This mode disables nonvolatile writes to the device’s Status Register.

Setting the WP

pin LOW while WPEN is a “1” while an internal write cycle to the Status Register is in progress will not stop this write operation, but the operation disables subsequent write attempts to the Status Register.

SCK

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30

INSTRUCTION 16 BIT ADDRESS

HIGH IMPEDANCE

FIGURE 5. READ EEPROM ARRAY SEQUENCE

15 14 13 3 2 1 0

DATA OUT

76543210

MSB

FN8128.1

May 16, 2005

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