intersil X5083 DATA SHEET

X5083

Data Sheet September 16, 2005

CPU Supervisor with 8Kbit SPI EEPROM

This device combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability.

Applying power to the device activates the power-on reset circuit which holds RESET

active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code.

The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET

signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power.

The device’s low V

detection circuitry protects the user’s

system from low voltage conditions, resetting the system when V asserted until V stabilizes. Five industry standard V

falls below the minimum VCC trip point. RESET is

returns to the proper operating level and

thresholds are

TRIP

available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to finetune the threshold for applications requiring higher precision.

Pinouts

8 Ld TSSOP

RESET

CS/WDI

1 2 3 4

X5083

SCK

FN8127.2

Features

•Low VCC detection and reset assertion

- Four standard reset threshold voltages

4.63V, 4.38V, 2.93V, 2.63V

- Re-program low V

reset threshold voltage using

special programming sequence

- Reset signal valid to V

= 1V

• Selectable time out watchdog timer

• Long battery life with low power consumption

- <50µA max standby current, watchdog on

- <1µA max standby current, watchdog off

- <400µA max active current during read

• 8Kbits of EEPROM

™

• Save critical data with Block Lock

memory

- Block lock first or last page, any 1/4 or lower 1/2 of EEPROM array

• Built-in inadvertent write protection

- Write enable latch

- Write protect pin

• SPI Interface - 3.3MHz clock rate

• Minimize programming time

- 16 byte page write mode

- 5ms write cycle time (typical)

• SPI modes (0,0 & 1,1)

• Available packages

- 8 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP

• Pb-free plus anneal available (RoHS compliant)

Applications

8 Ld SOIC, 8 Ld PDIP

1 2

X5083

3 4

/WDI

• Communications Equipment

- Routers, Hubs, Switches

- Set Top Boxes

RESET SCK

• Industrial Systems

- Process Control

- Intelligent Instrumentation

• Computer Systems

- Desktop Computers

- Network Servers

• Battery Powered Equipment

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Typical Application

X5083

2.7-5.0V

Block Diagram

TRIP

VCC

X5083

RESET

VSS

10K

SCK

WATCHDOG TRANSITION

DETECTOR

VCC

RESET

SPI

VSS

POR AND LOW

VOLTAGE RESET

GENERATION

RESET & WATCHDOG

TIMEBASE

WATCHDOG

TIMER

RESET

RESET (X5083)

X5083

STANDARD V

LEVEL SUFFIX

TRIP

4.63V (+/-2.5%) -4.5A

/WDI

SCK

COMMAND DECODE &

CONTROL

LOGIC

PROTECT LOGIC

STATUS

EEPROM

ARRAY 8KBITS

2.93V (+/-2.5%) -2.7A

2.63V (+/-2.5%) -2.7

See “Ordering Information” on page 3 for more details

For Custom Settings, call Intersil.

4.38V (+/-2.5%) -4.5

FN8127.2

September 16, 2005

X5083

Ordering Information

PART NUMBER RESET

(ACTIVE LOW) PART MARKING V

X5083P-4.5A X5083P AL 4.5-5.5 4.5-4.75 0 to 70 8 Ld PDIP

X5083PI-4.5A X5083P AM -40 to 85 8 Ld PDIP

X5083S8-4.5A X5083 AL 0 to 70 8 Ld SOIC

X5083S8Z-4.5A (Note) X5083 Z AL 0 to 70 8 Ld SOIC (Pb-free)

X5083S8I-4.5A* X5083 AM -40 to 85 8 Ld SOIC

X5083S8IZ-4.5A* (Note) X5083 Z AM -40 to 85 8 Ld SOIC (Pb-free)

X5083V8-4.5A 583AL 0 to 70 8 Ld TSSOP

X5083V8I-4.5A 583AM -40 to 85 8 Ld TSSOP

X5083P X5083P 4.5-5.5 4.25-4.5 0 to 70 8 Ld PDIP

X5083PI X5083P I -40 to 85 8 Ld PDIP

X5083SI X5083 I -40 to 85 8 Ld SOIC

X5083S8 X5083 0 to 70 8 Ld SOIC

X5083S8Z (Note) X5083 Z 0 to 70 8 Ld SOIC (Pb-free)

X5083S8I* X5083 I -40 to 85 8 Ld SOIC

X5083S8IZ* (Note) X5083 Z I -40 to 85 8 Ld SOIC (Pb-free)

X5083V8 X583 0 to 70 8 Ld TSSOP

X5083V8I 583I -40 to 85 8 Ld TSSOP

X5083P-2.7A X5083P AN 2.7-5.5 2.85-3.0 0 to 70 8 Ld PDIP

X5083PI-2.7A X5083P AP -40 to 85 8 Ld PDIP

X5083S8-2.7A X5083 AN 0 to 70 8 Ld SOIC

X5083S8Z-2.7A (Note) X5083 Z AN 0 to 70 8 Ld SOIC (Pb-free)

X5083S8I-2.7A X5083 AP -40 to 85 8 Ld SOIC

X5083S8IZ-2.7A (Note) X5083 Z AP -40 to 85 8 Ld SOIC (Pb-free)

X5083V8-2.7A 583AN 0 to 70 8 Ld TSSOP

X5083V8I-2.7A 583AP -40 to 85 8 Ld TSSOP

X5083P-2.7 X5083P F 2.7-5.5 2.55-2.7 0 to 70 8 Ld PDIP

X5083PI-2.7 X5083P G -40 to 85 8 Ld PDIP

X5083S8-2.7* X5083 F 0 to 70 8 Ld SOIC

X5083S8Z-2.7* (Note) X5083 Z F 0 to 70 8 Ld SOIC (Pb-free)

X5083S8I-2.7* X5083 G -40 to 85 8 Ld SOIC

X5083S8IZ-2.7* (Note) X5083 Z G -40 to 85 8 Ld SOIC (Pb-free)

X5083V8-2.7 583F 0 to 70 8 Ld TSSOP

X5083V8I-2.7 583G -40 to 85 8 Ld TSSOP

X5083V8IZ-2.7 (Note) -40 to 85 8 Ld TSSOP (Pb-free)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

*Add "-T1" suffix for tape and reel.

RANGE (V) V

RANGE TEMPERATURE RANGE (°C) PACKAGE

TRIP

FN8127.2

September 16, 2005

X5083

Pin Description

(SOIC/

PDIP)

13CS

24SOSerial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the

57SISerial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising

68SCKSerial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches

35WP

46VSSGround

82V

7 1 RESET

TSSOP NAME FUNCTION

/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless

a nonvolatile write cycle is underway, the device will be in the standby power mode. CS device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET

serial clock (SCK) clocks the data out.

edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first.

in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin.

Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited. This “Locks” the memory to protect it against inadvertent changes when WP

Supply Voltage

Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below the minimum V RESET

goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out period. A falling edge of CS power-up at about 1V and remains active for 250ms after the power supply stabilizes.

is required.

sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms.

will reset the watchdog timer. RESET goes active on

LOW enables the

going active.

is HIGH, the device operates normally.

Principles of Operation

Power-on Reset

Application of power to the X5083 activates a power-on reset circuit. This circuit goes LOW at 1V and pulls the RESET

pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. RESET active also blocks communication to the device through the SPI interface. When V 200ms (nominal) the circuit releases RESET processor to begin executing code. While V

exceeds the device V

TRIP

, allowing the

< V

communications to the device are inhibited.

Low Voltage Monitoring

During operation, the X5083 monitors the VCC level and asserts RESET minimum V microprocessor from operating in a power fail or brownout condition and terminates any SPI communication in progress. The RESET drops below 1V. It also remains active until V exceeds V

When V progress are terminated and communications are inhibited until V

if supply voltage falls below a preset

. The RESET signal prevents the

TRIP

signal remains active until the voltage

for 200ms.

TRIP

falls below V

exceeds V

TRIP

, any communications in

TRIP

for t

PURST

value for

TRIP

returns and

Watchdog Timer

The watchdog timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS

/WDI pin periodically to prevent a RESET signal. The

/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the status register determine the watchdog timer period. The microprocessor can change these watchdog bits with no action taken by the microprocessor these bits remain unchanged, even after total power failure.

VCC Threshold Reset Procedure

The X5083 is shipped with a standard VCC threshold (V voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard V needed in the V

is not exactly right, or if higher precision is

TRIP

value, the X5083 threshold may be

TRIP

adjusted. The procedure is described below, and uses the application of a high voltage control signal.

Setting the V

This procedure is used to set the V value. For example, if the current V V

is 4.6V, this procedure will directly make the change. If

TRIP

Voltage

to a higher voltage

TRIP

is 4.4V and the new

TRIP

the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value.

TRIP

)

FN8127.2

September 16, 2005

X5083

To set the new V threshold voltage to the V programming voltage V followed by a write of Data 00h to address 01h. CS HIGH on the write operation initiates the V sequence. Bring WP

voltage, apply the desired V

TRIP

pin and tie the WP pin to the

. Then send a WREN command,

TRIP

LOW to complete the operation.

TRIP

going

programming

Note: This operation also writes 00h to array address 01h.

Resetting the V

This procedure is used to set the V level. For example, if the current V V

must be 4.0V, then the V

TRIP

is reset, the new V

TRIP

01234567

SCK

Voltage

TRIP

to a “native” voltage

TRIP

is 4.4V and the new

TRIP

must be reset. When

TRIP

is something less than 1.7V.

TRIP

012345678910 20 21 22 23

06h

WREN Write Address Data

VP = 15-18V

02h

This procedure must be used to set the voltage to a lower value.

To reset the new V threshold voltage to the Vcc pin and tie the WP programming voltage V followed by a write of data 00h to address 03h. CS HIGH on the write operation initiates the V sequence. Bring WP

voltage, apply the desired V

TRIP

. Then send a WREN command,

programming

LOW to complete the operation.

TRIP

pin to the

going

Note: This operation also writes 00h to array address 03h.

16 Bits

0001h

00h

SCK

FIGURE 1. SET V

01234567

06h

WREN

FIGURE 2. RESET V

LEVEL SEQUENCE (V

TRIP

VP = 15-18V

012345678910 20 21 22 23

02h

Write

LEVEL SEQUENCE (VCC > 3V. WP = 15-18V)

TRIP

= DESIRED V

TRIP

16 Bits

0003h

Address

VALUE)

00h

Data

FN8127.2

September 16, 2005

X5083

TRIP

Adj.

Adjust

Run

1 2 3

X5083

8 7 6 5

RESET

µC

SCK SI

4.7K

FIGURE 3. SAMPLE V

TRIP

Programming

TRIP

RESET CIRCUIT

Execute

Reset V

TRIP

Sequence

Set VCC = VCC Applied =

Desired V

TRIP

New VCC Applied =

Old V

Applied + Error

Error ≤ –Emax

Emax = Maximum Desired Error

FIGURE 4. V

Execute

Set V

TRIP

Sequence

Apply 5V to V

Decrement V

= VCC - 50mV)

RESET pin

goes active?

YES

Measured V

Desired V

TRIP

–Emax < Error < Emax

DONE

PROGRAMMING SEQUENCE

TRIP

New VCC Applied =

Applied - Error

Old V

Execute

Reset V

TRIP

Sequence

Error

≥

Emax

FN8127.2

September 16, 2005

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