intersil X5083 DATA SHEET

®

X5083

Data Sheet September 16, 2005

CPU Supervisor with 8Kbit SPI EEPROM

This device combines four popular functions, Power-on Reset
Control, Watchdog Timer, Supply Voltage Supervision, and
Block Lock Serial EEPROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.

Applying power to the device activates the power-on reset
circuit which holds RESET

active for a period of time. This
allows the power supply and oscillator to stabilize before the
processor can execute code.

The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller fails to
restart a timer within a selectable time out interval, the device
activates the RESET

signal. The user selects the interval
from three preset values. Once selected, the interval does
not change, even after cycling the power.

The device’s low V

detection circuitry protects the user’s

CC

system from low voltage conditions, resetting the system
when V
asserted until V
stabilizes. Five industry standard V

falls below the minimum VCC trip point. RESET is

CC

returns to the proper operating level and

CC

thresholds are

TRIP

available, however, Intersil’s unique circuits allow the threshold
to be reprogrammed to meet custom requirements or to fine­tune the threshold for applications requiring higher precision.

Pinouts

8 Ld TSSOP

RESET

V

CC

CS/WDI

SO

1
2
3
4

X5083

SCK

8

SI

7

V

6

SS

WP

5

FN8127.2

Features

•Low VCC detection and reset assertion

- Four standard reset threshold voltages

4.63V, 4.38V, 2.93V, 2.63V

- Re-program low V

reset threshold voltage using

CC

special programming sequence

- Reset signal valid to V

CC

= 1V

• Selectable time out watchdog timer

• Long battery life with low power consumption

- <50µA max standby current, watchdog on

- <1µA max standby current, watchdog off

- <400µA max active current during read

• 8Kbits of EEPROM

™

• Save critical data with Block Lock

memory

- Block lock first or last page, any 1/4 or lower 1/2 of
EEPROM array

• Built-in inadvertent write protection

- Write enable latch

- Write protect pin

• SPI Interface - 3.3MHz clock rate

• Minimize programming time

- 16 byte page write mode

- 5ms write cycle time (typical)

• SPI modes (0,0 & 1,1)

• Available packages

- 8 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP

• Pb-free plus anneal available (RoHS compliant)

Applications

8 Ld SOIC, 8 Ld PDIP

SO

WP

V

1
2

X5083

3
4

SS

CS

/WDI

• Communications Equipment

- Routers, Hubs, Switches

- Set Top Boxes

V

8

CC

7

RESET
SCK

6

SI

5

• Industrial Systems

- Process Control

- Intelligent Instrumentation

• Computer Systems

- Desktop Computers

- Network Servers

• Battery Powered Equipment

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2005. All Rights Reserved

Typical Application

X5083

2.7-5.0V

Block Diagram

V

CC

V

TRIP

VCC

X5083

RESET

VSS

10K

CS

SCK

SI

SO

WP

+

-

WATCHDOG
TRANSITION

DETECTOR

VCC

uC

RESET

SPI

VSS

POR AND LOW

VOLTAGE RESET

GENERATION

RESET & WATCHDOG

TIMEBASE

WATCHDOG

TIMER

RESET

RESET (X5083)

X5083

STANDARD V

LEVEL SUFFIX

TRIP

4.63V (+/-2.5%) -4.5A

CS

/WDI

SO

SCK

WP

SI

COMMAND
DECODE &

CONTROL

LOGIC

PROTECT LOGIC

STATUS

REGISTER

EEPROM

ARRAY
8KBITS

2.93V (+/-2.5%) -2.7A

2.63V (+/-2.5%) -2.7

See “Ordering Information” on page 3 for
more details

For Custom Settings, call Intersil.

4.38V (+/-2.5%) -4.5

2

FN8127.2

September 16, 2005

X5083

Ordering Information

PART NUMBER RESET

(ACTIVE LOW) PART MARKING V

X5083P-4.5A X5083P AL 4.5-5.5 4.5-4.75 0 to 70 8 Ld PDIP

X5083PI-4.5A X5083P AM -40 to 85 8 Ld PDIP

X5083S8-4.5A X5083 AL 0 to 70 8 Ld SOIC

X5083S8Z-4.5A (Note) X5083 Z AL 0 to 70 8 Ld SOIC (Pb-free)

X5083S8I-4.5A* X5083 AM -40 to 85 8 Ld SOIC

X5083S8IZ-4.5A* (Note) X5083 Z AM -40 to 85 8 Ld SOIC (Pb-free)

X5083V8-4.5A 583AL 0 to 70 8 Ld TSSOP

X5083V8I-4.5A 583AM -40 to 85 8 Ld TSSOP

X5083P X5083P 4.5-5.5 4.25-4.5 0 to 70 8 Ld PDIP

X5083PI X5083P I -40 to 85 8 Ld PDIP

X5083SI X5083 I -40 to 85 8 Ld SOIC

X5083S8 X5083 0 to 70 8 Ld SOIC

X5083S8Z (Note) X5083 Z 0 to 70 8 Ld SOIC (Pb-free)

X5083S8I* X5083 I -40 to 85 8 Ld SOIC

X5083S8IZ* (Note) X5083 Z I -40 to 85 8 Ld SOIC (Pb-free)

X5083V8 X583 0 to 70 8 Ld TSSOP

X5083V8I 583I -40 to 85 8 Ld TSSOP

X5083P-2.7A X5083P AN 2.7-5.5 2.85-3.0 0 to 70 8 Ld PDIP

X5083PI-2.7A X5083P AP -40 to 85 8 Ld PDIP

X5083S8-2.7A X5083 AN 0 to 70 8 Ld SOIC

X5083S8Z-2.7A (Note) X5083 Z AN 0 to 70 8 Ld SOIC (Pb-free)

X5083S8I-2.7A X5083 AP -40 to 85 8 Ld SOIC

X5083S8IZ-2.7A (Note) X5083 Z AP -40 to 85 8 Ld SOIC (Pb-free)

X5083V8-2.7A 583AN 0 to 70 8 Ld TSSOP

X5083V8I-2.7A 583AP -40 to 85 8 Ld TSSOP

X5083P-2.7 X5083P F 2.7-5.5 2.55-2.7 0 to 70 8 Ld PDIP

X5083PI-2.7 X5083P G -40 to 85 8 Ld PDIP

X5083S8-2.7* X5083 F 0 to 70 8 Ld SOIC

X5083S8Z-2.7* (Note) X5083 Z F 0 to 70 8 Ld SOIC (Pb-free)

X5083S8I-2.7* X5083 G -40 to 85 8 Ld SOIC

X5083S8IZ-2.7* (Note) X5083 Z G -40 to 85 8 Ld SOIC (Pb-free)

X5083V8-2.7 583F 0 to 70 8 Ld TSSOP

X5083V8I-2.7 583G -40 to 85 8 Ld TSSOP

X5083V8IZ-2.7 (Note) -40 to 85 8 Ld TSSOP (Pb-free)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

*Add "-T1" suffix for tape and reel.

RANGE (V) V

CC

RANGE TEMPERATURE RANGE (°C) PACKAGE

TRIP

3

FN8127.2

September 16, 2005

X5083

Pin Description

PIN

(SOIC/

PDIP)

13CS

24SOSerial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the

57SISerial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising

68SCKSerial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches

35WP

46VSSGround

82V

7 1 RESET

PIN

TSSOP NAME FUNCTION

/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless

a nonvolatile write cycle is underway, the device will be in the standby power mode. CS
device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW
transition on CS
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a
HIGH to LOW transition within the watchdog time out period results in RESET

serial clock (SCK) clocks the data out.

edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first.

in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO
pin.

Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited. This “Locks” the
memory to protect it against inadvertent changes when WP

Supply Voltage

CC

Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below the
minimum V
RESET

goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the
selectable watchdog time out period. A falling edge of CS
power-up at about 1V and remains active for 250ms after the power supply stabilizes.

is required.

sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms.

CC

will reset the watchdog timer. RESET goes active on

LOW enables the

going active.

is HIGH, the device operates normally.

Principles of Operation

Power-on Reset

Application of power to the X5083 activates a power-on
reset circuit. This circuit goes LOW at 1V and pulls the
RESET

pin active. This signal prevents the system
microprocessor from starting to operate with insufficient
voltage or prior to stabilization of the oscillator. RESET
active also blocks communication to the device through the
SPI interface. When V
200ms (nominal) the circuit releases RESET
processor to begin executing code. While V

exceeds the device V

CC

TRIP

, allowing the

< V

CC

communications to the device are inhibited.

Low Voltage Monitoring

During operation, the X5083 monitors the VCC level and
asserts RESET
minimum V
microprocessor from operating in a power fail or brownout
condition and terminates any SPI communication in
progress. The RESET
drops below 1V. It also remains active until V
exceeds V

When V
progress are terminated and communications are inhibited
until V

CC

if supply voltage falls below a preset

. The RESET signal prevents the

TRIP

signal remains active until the voltage

for 200ms.

TRIP

falls below V

CC

exceeds V

TRIP

, any communications in

TRIP

for t

PURST

.

CC

value for

TRIP

returns and

Watchdog Timer

The watchdog timer circuit monitors the microprocessor activity
by monitoring the WDI input. The microprocessor must toggle
the CS

/WDI pin periodically to prevent a RESET signal. The

CS

/WDI pin must be toggled from HIGH to LOW prior to the
expiration of the watchdog time out period. The state of two
nonvolatile control bits in the status register determine the
watchdog timer period. The microprocessor can change these
watchdog bits with no action taken by the microprocessor
these bits remain unchanged, even after total power failure.

VCC Threshold Reset Procedure

The X5083 is shipped with a standard VCC threshold (V
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard V
needed in the V

is not exactly right, or if higher precision is

TRIP

value, the X5083 threshold may be

TRIP

adjusted. The procedure is described below, and uses the
application of a high voltage control signal.

Setting the V

This procedure is used to set the V
value. For example, if the current V
V

is 4.6V, this procedure will directly make the change. If

TRIP

TRIP

Voltage

to a higher voltage

TRIP

is 4.4V and the new

TRIP

the new setting is to be lower than the current setting, then it
is necessary to reset the trip point before setting the new
value.

TRIP

)

4

FN8127.2

September 16, 2005

X5083

To set the new V
threshold voltage to the V
programming voltage V
followed by a write of Data 00h to address 01h. CS
HIGH on the write operation initiates the V
sequence. Bring WP

voltage, apply the desired V

TRIP

pin and tie the WP pin to the

CC

. Then send a WREN command,

P

TRIP

LOW to complete the operation.

TRIP

going

programming

Note: This operation also writes 00h to array address 01h.

Resetting the V

This procedure is used to set the V
level. For example, if the current V
V

must be 4.0V, then the V

TRIP

V

is reset, the new V

TRIP

WP

CS

01234567

SCK

SI

Voltage

TRIP

to a “native” voltage

TRIP

is 4.4V and the new

TRIP

must be reset. When

TRIP

is something less than 1.7V.

TRIP

012345678910 20 21 22 23

06h

WREN Write Address Data

VP = 15-18V

02h

This procedure must be used to set the voltage to a lower
value.

To reset the new V
threshold voltage to the Vcc pin and tie the WP
programming voltage V
followed by a write of data 00h to address 03h. CS
HIGH on the write operation initiates the V
sequence. Bring WP

voltage, apply the desired V

TRIP

. Then send a WREN command,

P

programming

LOW to complete the operation.

TRIP

TRIP

pin to the

going

Note: This operation also writes 00h to array address 03h.

16 Bits

0001h

00h

WP

CS

SCK

FIGURE 1. SET V

01234567

SI

06h

WREN

FIGURE 2. RESET V

LEVEL SEQUENCE (V

TRIP

VP = 15-18V

012345678910 20 21 22 23

02h

Write

LEVEL SEQUENCE (VCC > 3V. WP = 15-18V)

TRIP

= DESIRED V

CC

TRIP

16 Bits

0003h

Address

VALUE)

00h

Data

5

FN8127.2

September 16, 2005

X5083

V

TRIP

Adj.

V

P

Adjust

Run

1
2
3

4

X5083

8
7
6
5

RESET

µC

SCK
SI

SO

CS

4.7K

FIGURE 3. SAMPLE V

V

TRIP

Programming

TRIP

RESET CIRCUIT

Execute

Reset V

TRIP

Sequence

Set VCC = VCC Applied =

Desired V

TRIP

New VCC Applied =

Old V

Applied + Error

CC

Error ≤ –Emax

Emax = Maximum Desired Error

FIGURE 4. V

Execute

Set V

TRIP

Sequence

NO

Apply 5V to V

Decrement V

(V

= VCC - 50mV)

CC

RESET pin

CC

CC

goes active?

YES

Measured V

Desired V

TRIP

TRIP

–Emax < Error < Emax

DONE

PROGRAMMING SEQUENCE

TRIP

New VCC Applied =

Applied - Error

Old V

CC

Execute

Reset V

TRIP

Sequence

Error

≥

-

Emax

6

FN8127.2

September 16, 2005

X5083

SPI Serial Memory

The memory portion of the device is a CMOS serial EEPROM
array with Intersil’s block lock protection. The array is
internally organized as x 8. The device features a Serial
Peripheral Interface (SPI) and software protocol allowing
operation on a simple four-wire bus.

The device utilizes Intersil’s proprietary Direct Write
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.

The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.

The device monitors the bus and asserts RESET
watchdog timer is enabled and there is no bus activity within
the user selectable time out period or the supply voltage falls
below a preset minimum V

TRIP

.

The device contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on the
rising edge of SCK. CS

must be LOW during the entire

operation.

All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS

goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.

™

cell,

output if the

Write Enable Latch

The device contains a Write Enable Latch. This latch must
be SET before a Write Operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 7). This latch is automatically reset
upon a power-up condition and after the completion of a
valid Write Cycle.

Status Register

The RDSR instruction provides access to the status register.
The status register may be read at any time, even during a
write cycle. The status register is formatted as follows.

Status Register/Block Lock/WDT Byte

765 4 3 210

0 0 0 WD1 WD0 BL2 BL1 BL0

Block Lock Memory

Intersil’s block lock memory provides a flexible mechanism to
store and lock system ID and parametric information. There
are seven distinct block lock memory areas within the array
which vary in size from one page to as much as half of the
entire array. These areas and associated address ranges are
block locked by writing the appropriate two byte block lock
instruction to the device as described in Table 1 and Figure 9.
Once a block lock instruction has been completed, that block
lock setup is held in the nonvolatile status register until the
next block lock instruction is issued. The sections of the
memory array that are block locked can be read but not
written until block lock is removed or changed.

TABLE 1. INSTRUCTION SET AND BLOCK LOCK PROTECTION BYTE DEFINITION

INSTRUCTION FORMAT INSTRUCTION NAME AND OPERATION

0000 0110 WREN: set the write enable latch (write enable operation)

0000 0100 WRDI: reset the write enable latch (write disable operation)

0000 0001 Write status instruction—followed by:

0000 0101 READ STATUS: reads status register & provides write in progress status on SO pin

0000 0010 WRITE: write operation followed by address and data

0000 0011 READ: read operation followed by address

Block lock/WDT byte: (See Figure 1)

000WD
000WD
000WD
000WD
000WD
000WD
000WD
000WD

WD2000 --->no block lock: 00h-00h--->none of the array

1

WD2001 --->block lock Q1: 0000h-00FFh--->lower quadrant (Q1)

1

WD2010 --->block lock Q2: 0100h-01FFh--->Q2

1

WD2011 --->block lock Q3: 0200h-02FFh--->Q3

1

WD2100 --->block lock Q4: 0300h-03FFh--->upper quadrant (Q4)

1

WD2101 --->block lock H1: 0000h-01FFh--->lower half of the array (H1)

1

WD2110 --->block lock P0: 0000h-000Fh--->lower page (P0)

1

WD2111 --->block lock Pn: 03F0h-03FFh--->upper page (PN)

1

7

FN8127.2

September 16, 2005

X5083

Watchdog Timer

The watchdog timer bits, WD0 and WD1, select the
watchdog time out period. These nonvolatile bits are
programmed with the WRSR instruction. A change to the
Watchdog Timer, either setting a new time out period or
turning it off or on, takes effect, following either the next
command (read or write) or cycling the power to the device.

The recommended procedure for changing the Watch-dog
Timer settings is to do a WREN, followed by a write status
register command. Then execute a soft-ware loop to read
the status register until the MSB of the status byte is zero. A
valid alternative is to do a WREN, followed by a write status
register command. Then wait 10ms and do a read status
command.

TABLE 2. WATCHDOG TIMER DEFINITION

STATUS REGISTER BITS

0 0 1.4s

0 1 600ms

1 0 200ms

1 1 disabled (factory default)

WATCHDOG TIME OUT

(TYPICAL)WD1 WD0

Read Sequence

When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 16-bit address.
After the READ opcode and address are sent, the data
stored in the memory at the selected address is shifted out
on the SO line. The data stored in memory at the next
address can be read sequentially by continuing to provide
clock pulses. The address is automatically incremented to
the next higher address after each byte of data is shifted out.
When the highest address is reached, the address counter
rolls over to address $0000 allowing the read cycle to be
continued indefinitely. The read operation is terminated by
taking CS

high. Refer to the read EEPROM array sequence

(Figure 5).

To read the status register, the CS

line is first pulled low to
select the device followed by the 8-bit RDSR instruction.
After the RDSR opcode is sent, the contents of the status
register are shifted out on the SO line. Refer to the read status
register sequence (Figure 6).

Write Sequence

Prior to any attempt to write data into the device, the “Write
Enable” Latch (WEL) must first be set by issuing the WREN
instruction (Figure 7). CS
instruction is clocked into the device. After all eight bits of the
instruction are transmitted, CS
the user continues the write operation without taking CS
HIGH after issuing the WREN instruction, the write operation
will be ignored.

is first taken LOW, then the WREN

must then be taken HIGH. If

To write data to the EEPROM memory array, the user then
issues the WRITE instruction followed by the 16 bit address
and then the data to be written. Any unused address bits are
specified to be “0’s”. The WRITE operation minimally takes
32 clocks. CS

must go low and remain low for the duration of
the operation. If the address counter reaches the end of a
page and the clock continues, the counter will roll back to the
first address of the same page and overwrite any data that
may have been previously written.

For a write operation (byte or page write) to be completed,
CS

can only be brought HIGH after bit 0 of the last data byte
to be written is clocked in. If it is brought HIGH at any other
time, the write operation will not be completed (Figure 8).

To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 9). Data bits 5, 6
and 7 must be “0”.

Read Status Operation

If there is not a nonvolatile write in progress, the read status
instruction returns the block lock setting from the status
register which contains the watchdog timer bits WD1, WD0,
and the block lock bits IDL2-IDL0 (Figure 6). The block lock
bits define the block lock condition (Table 1). The watchdog
timer bits set the operation of the watchdog timer (Table 2).
The other bits are reserved and will return ’0’ when read. See
Figure 6.

During an internal nonvolatile write operaiton, the Read
Status Instruction returns a HIGH on SO in the first bit
following the RDSR instruction (the MSB). The remaining
bits in the output status byte are undefined. Repeated Read
Status Instructions return the MSB as a ‘1’ until the
nonvolatile write cycle is complete. When the nonvolatile
write cycle is completed, the RDSR instruction returns a ‘0’
in the MSB position with the remaining bits of the status
register undefined. Subsequent RDSR instructions return
the Status Register Contents. See Figure 10.

RESET Operation

The RESET output is designed to go LOW whenever VCC
has dropped below the minimum trip point and/or the
watchdog timer has reached its programmable time out limit.

The RESET

output is an open drain output and requires a

pull up resistor.

Operational Notes

The device powers-up in the following state:

• The device is in the low power standby state.

• A HIGH to LOW transition on CS

active state and receive an instruction.

• SO pin is high impedance.

• The write enable latch is reset.

• Reset signal is active for t

is required to enter an

.

PURST

8

FN8127.2

September 16, 2005

Data Protection

The following circuitry has been included to prevent
inadvertent writes:

• A WREN instruction must be issued to set the write enable
latch.

•CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.

• When V
are inhibited.

CS

is below V

CC

, communications to the device

TRIP

X5083

SCK

SO

0123456789

Read Instruction

(1 Byte)

SI

High Impedance

FIGURE 5. READ OPERATION SEQUENCE

CS

01234567

SCK

Read Status
Instruction

SI

Byte Address (2 Byte)

1514 3210

20 21 22 23 24 25 26 27 28 29 30

Data Out

76543210

...
...

SO

W

W

D
1

SO = Status Reg When no Nonvolatile

Write Cycle

FIGURE 6. READ STATUS OPERATION SEQUENCE

9

B

B

B

D

L

0

L

2

1

...

L
0

FN8127.2

September 16, 2005

CS

SCK

SI

X5083

01234567

Instruction

(1 Byte)

CS

SCK

CS

SCK

SO

012345678910

Instruction 16 Bit Address

SI

32 33 34 35 36 37 38 39

Data Byte 2

SI

76543210

High Impedance

FIGURE 7. WREN/WRDI SEQUENCE

15 14 13 3 2 1 0

40 41 42 43 44 45 46 47

Data Byte 3

76543210

20 21 22 23 24 25 26 27 28 29 30 31

Data Byte 1

76543210

Data Byte N

654 3210

CS

SCK

SO

FIGURE 8. EEPROM ARRAY WRITE SEQUENCE

0123456789

Instruction

SI

High Impedance

FIGURE 9. STATUS REGISTER WRITE SEQUENCE

10

10 11 12 13 14 15

Data Byte

6543210

W

D
1

B
L

2

BB

L

L

1

0

W

D
0

FN8127.2

September 16, 2005

CS

X5083

CS

SCK

SI

SCK

SO

01234567

READ STATUS
INSTRUCTION

01234567

READ STATUS
INSTRUCTION

SI

NONVOLATILE WRITE IN PROGRESS

SO MSB HIGH while
in the Nonvolatile write cycle

01234567

READ STATUS
INSTRUCTION

01234567

SO MSB still HIGH indicates
Nonvolatile write cycle still in progress

READ STATUS
INSTRUCTION

SO

NONVOLATILE
WRITE ENDS

1st detected SO MSB LOW
indicates end of Nonvolatile write cycle

FIGURE 10. READ NONVOLATILE WRITE STATUS

43210

BL2

WD0

BL1

WD1

BL0

11

FN8127.2

September 16, 2005

CS

t

WC

X5083

SCK

SI

Non-volatile

Write

Operation

Symbol Table

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from LOW
to HIGH

May change
from HIGH
to LOW

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from LOW
to HIGH

Will change
from HIGH
to LOW

Changing:
State Not
Known

is High
Impedance

012345

NEXT

INSTRUCTION

Wait tWC after a write for new operation,
if not using polling procedure

FIGURE 11. END OF NONVOLATILE WRITE (NO POLLING)

67

12

FN8127.2

September 16, 2005

X5083

Absolute Maximum Ratings Operating Conditions

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . -65°C to 135°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to 150°C

Voltage on Any Pin with Respect To V

. . . . . . . . . . . . . -1.0V to 7V

ss

D.C. Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

DC Electrical Specifications (Over the recommended operating conditions unless otherwise specified.)

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

CC2

I

SB1

I

SB2

I

SB3

I

I

LO

V

(Note 1) Input LOW Voltage -0.5 V

IL

VIH (Note 1) Input HIGH Voltage V

V

OL1

V

OL2

V

OL3

V

OH1

V

OH2

V

OH3

V

OLRS

VCC Write Current (Active) SCK = VCC x 0.1/VCC x 0.9 @ 5MHz,

SO = Open

VCC Read Current (Active) SCK = VCC x 0.1/VCC x 0.9 @ 5MHz,

SO = Open

VCC Standby Current WDT = OFF CS = VCC, VIN = VSS or VCC,

= 5.5V

V

CC

VCC Standby Current WDT = ON CS = VCC, VIN = VSS or VCC,

= 5.5V

V

CC

VCC Standby Current WDT = ON CS = VCC, VIN = VSS or VCC,

V

= 3.6V

CC

Input Leakage Current VIN = VSS to VCC 0.1 10 µA

LI

Output Leakage Current V

= VSS to V

OUT

CC

Output LOW Voltage VCC > 3.3V, IOL = 2.1mA 0.4 V

Output LOW Voltage 2V < VCC ≤ 3.3V, IOL = 1mA 0.4 V

Output LOW Voltage VCC ≤ 2V, IOL = 0.5mA 0.4 V

Output HIGH Voltage VCC > 3.3V, IOH = -1.0mA V

Output HIGH Voltage 2V < VCC ≤ 3.3V, IOH = -0.4mA V

Output HIGH Voltage VCC ≤ 2V, IOH = -0.25mA V

Reset Output LOW Voltage I

= 1mA 0.4 V

OL

Temperature Range

Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C

V

Range

CC

-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

Blank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

LIMITS

UNITMIN TYP MAX

5mA

0.4 mA

1µA

50 µA

20 µA

0.1 10 µA

x 0.3 V

CC

x 0.7 V

CC

- 0.8 V

CC

- 0.4 V

CC

- 0.2 V

CC

+ 0.5 V

CC

Power-Up Timing

SYMBOL PARAMETER MIN MAX UNIT

(Note 2) Power-up to read operation 1 ms

t

PUR

t

(Note 2) Power-up to write operation 5 ms

PUW

.

Capacitance T

SYMBOL TEST MAX UNIT CONDITIONS

C

(Note 2) Output capacitance (SO, RESET, RESET) 8 pF V

OUT

C

(Note 2) Input capacitance (SCK, SI, CS, WP)6pFV

IN

NOTES:

min. and VIH max. are for reference only and are not tested.

1. V

IL

2. This parameter is periodically sampled and not 100% tested.

= +25°C, f = 1MHz, VCC = 5V

A

13

= 0V

OUT

= 0V

IN

FN8127.2

September 16, 2005

X5083

Equivalent A.C. Load Circuit at 5V V

5V

5V

CC

A.C. Test Conditions

Input pulse levels VCC x 0.1 to VCC x 0.9

Input rise and fall times 10ns

SO

OUTPUT

1.64kΩ

1.64kΩ

100pF

3.3kΩ

RESET

30pF

Input and output timing level V

CC

x 0.5

AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified)

2.7V-5.5V

SYMBOL PARAMETER

DATA INPUT TIMING

f

SCK

t

CYC

t

LEAD

t

LAG

t

WH

t

WL

t

SU

t

H

t

(Note 3) Input rise time 2µs

RI

t

(Note 3) Input fall time 2µs

FI

t

CS

t

(Note 4) Write cycle time 10 ms

WC

Clock frequency 0 3.3 MHz

Cycle time 300 ns

CS lead time 150 ns

CS lag time 150 ns

Clock HIGH time 130 ns

Clock LOW time 130 ns

Data setup time 20 ns

Data hold time 20 ns

CS deselect time 100 ns

DATA OUTPUT TIMING

f

SCK

t

DIS

t

V

t

HO

t

(Note 3) Output rise time 50 ns

RO

t

(Note 3) Output fall time 50 ns

FO

Clock frequency 0 3.3 MHz

Output disable time 150 ns

Output valid from clock low 130 ns

Output hold time 0 ns

NOTES:

3. This parameter is periodically sampled and not 100% tested.

is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.

4. t

WC

UNITMIN MAX

14

FN8127.2

September 16, 2005

Serial Output Timing

CS

SCK

t

CYC

X5083

t

WH

t

LAG

SO

ADDR

SI

LSB IN

Serial Input Timing

CS

SCK

t

SU

SI

SO

t

V

t

HO

t

WL

MSB Out MSB–1 Out LSB Out

t

LEAD

t

H

t

RI

MSB IN

High Impedance

t

FI

LSB IN

t

DIS

t

CS

t

LAG

Power-Up and Power-Down Timing

V

0 Volts

TRIP

t

PURST

t

t

R

PURST

15

V

CC

RESET

V

TRIP

t

t

RPD

F

FN8127.2

September 16, 2005

X5083

RESET

Output Timing

SYMBOL PARAMETER MIN TYP MAX UNIT

V

TRIP

Reset trip point voltage, X5083PT-4.5A (Note 6)
Reset trip point voltage, X5083PT
Reset trip point voltage, X5083PT-2.7A
Reset trip point voltage, X5083PT-2.7

t

PURST

t

(Note 5) VCC detect to reset/output 500 ns

RPD

t

(Note 5) VCC fall time 0.1 ns

F

t

(Note 5) VCC rise time 0.1 ns

R

V

RVALID

Power-up reset time out 100 200 280 ms

Reset valid V

CC

4.5

4.25

2.85

2.55

1V

4.63

4.38

2.93

2.63

4.75

4.5

3.00

2.7

NOTES:

5. This parameter is periodically sampled and not 100% tested.

6. PT = Package/Temperature

CS vs. RESET Timing

CS

t

CST

RESET

V

t

WDO

t

RST

t

WDO

t

RST

RESET Output Timing

SYMBOL PARAMETER MIN TYP MAX UNIT

t

WDO

t

t

CST

RST

Watchdog time out period,

WD1 = 1, WD0 = 1(default)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0

100
450

1

OFF

200
600

1.4

300
800

2

CS pulse width to reset the watchdog 400 ns

Reset time out 100 200 300 ms

ms
ms
sec

16

FN8127.2

September 16, 2005

V

Programming Timing Diagram

TRIP

V

CC

(V

)

TRIP

V

P

V

PE

X5083

V

TRIP

t

TSU

t

THD

t

VPH

t

VPO

t

RP

CS

t

VPS

t

PCS

SCK

SI

0001h (set)

0003h (reset)WREN Write

Addr.

00
Data

V

Programming Parameters

TRIP

02h06h

PARAMETER DESCRIPTION MIN MAX UNIT

t

t

t

t

t

t

t

V

TRAN

VPS

VPH

PCS

TSU

THD

WC

VPO

t

RP

V

V

P

tv

V

program enable voltage setup time 1 µs

TRIP

V

program enable voltage hold time 1 µs

TRIP

V

programming CS inactive time 1 µs

TRIP

V

setup time 1µs

TRIP

V

hold (stable) time 10 ms

TRIP

V

write cycle time 10 ms

TRIP

V

program enable voltage off time (between successive adjustments) 0 µs

TRIP

V

program recovery period (between successive adjustments) 10 ms

TRIP

Programming voltage 15 18 V

V

programmed voltage range 2.0 5.0 V

TRIP

V

program variation after programming (0-75°C). (programmed at 25°C) -25 +25 mV

TRIP

NOTES:

7. V

programming parameters are periodically sampled and are not 100% tested.

TRIP

8. For custom V

settings, Contact Factory.

TRIP

17

FN8127.2

September 16, 2005

Packaging Information

All End Pins Optional

8-Lead Plastic Dual In-Line Package Type P

Pin 1 Index

Half Shoulder Width On

Seating
Plane

Pin 1

X5083

0.430 (10.92)

0.360 (9.14)

(7.62) Ref.

0.300

0.260 (6.60)

0.240 (6.10)

0.060 (1.52)

0.020 (0.51)

0.145 (3.68)

0.128 (3.25)

0.150 (3.81)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

.073 (1.84)

Max.

Typ. 0.010 (0.25)

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.325 (8.25)

0.300 (7.62)

0.025 (0.64)

0.015 (0.38)

0.065 (1.65)

0.045 (1.14)

0.020 (0.51)

0.016 (0.41)

0°

15°

18

FN8127.2

September 16, 2005

Packaging Information

X5083

8-Lead Plastic Small Outline Gull Wing Package Type S

Pin 1 Index

(4X) 7°

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

Pin 1

X 45°

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

0.150 (3.80)

0.158 (4.00)

0.004 (0.19)

0.010 (0.25)

0.228 (5.80)

0.244 (6.20)

0.053 (1.35)

0.069 (1.75)

0.050" Typical

0° - 8°

0.0075 (0.19)

0.010 (0.25)

0.016 (0.410)

0.037 (0.937)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.250"

19

0.030"

Typical

8 PlacesFOOTPRINT

0.050"
Typical

FN8127.2

September 16, 2005

Packaging Information

X5083

8-Lead Plastic, TSSOP, Package Type V

.025 (.65) BSC

0° - 8°

.019 (.50)
.029 (.75)

Detail A (20X)

.114 (2.9)
.122 (3.1)

.0075 (.19)
.0118 (.30)

.010 (.25)

.169 (4.3)
.177 (4.5)

.002 (.05)
.006 (.15)

Gage Plane

Seating Plane

.252 (6.4) BSC

.047 (1.20)

(4.16)

(7.72)

(1.78)

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

(0.42)

(0.65)

All Measurements Are Typical

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

20

FN8127.2

September 16, 2005