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®
X40010, X40011, X40014, X40015
Data Sheet March 28, 2005
Dual Voltage Monitor with Integrated CPU
Supervisor
FEATURES
• Dual voltage detection and reset assertion
—Standard reset threshold settings
See Selection table on page 2.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to V
—Monitor three voltages or detect power fail
• Independent Core Voltage Monitor (V2MON)
• Fault detection register
• Selectable power on reset timeout (0.05s,
0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval (25ms,
200ms,1.4s, off)
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8-lead SOIC, TSSOP
• Monitor Voltages: 5V to 0.9V
• Independent Core Voltage Monitor
CC
= 1V
FN8111.0
APPLICATIONS
• Communication Equipment
—Routers, Hubs, Switches
—Disk Arrays, Network Storage
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
—Computers
—Network Servers
DESCRIPTION
The X40010/11/14/15 combines power-on reset control, watchdog timer, supply voltage supervision, and
secondary voltage supervision, in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to V
circuit which holds RESET/RESET
activates the power on reset
CC
active for a period of
time. This allows the power supply and system oscillator to stabilize before the processor can execute code.
BLOCK DIAGRAM
SDA
SCL
V
CC
(V1MON)
V2MON
Data
Register
Command
Decode Test
& Control
Logic
Threshold
Reset Logic
User Programmable
V
TRIP1
User Programmable
V
TRIP2
Fault Detection
Register
Status
Register
+
V2MON
V
CC
+
-
*X40010/11 = V2MON*
X40014/15 = V
Watchdog Timer
and
Reset Logic
Power on,
Low Voltage
Reset
Generation
CC
WDO
RESET
X40010/14
RESET
X40011/15
V2FAIL
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
X40010, X40011, X40014, X40015
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system
when V
RESET/RESET
falls below the minimum V
CC
is active until VCC returns to proper
TRIP1
point.
operating level and stabilizes. A second voltage monitor circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Intersil’s unique circuits allows the
threshold for either voltage monitor to be repro-
The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable
time out interval, the device activates the WDO
The user selects the interval from th ree preset values.
Once selected, the interval does not change, even
after cycling the power.
The device features a 2-wire interface and software
protocol allowing operation on an I
2C®
grammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
Dual Voltage Monitors
Table 1:
Device Expected System Voltages Vtrip1(V) Vtrip2(V) POR (system)
X40010/11
-A
-B
-C
X40014/15
-A
-B
-C
5V; 3V or 3.3V
5V; 3V
3V; 3.3V; 1.8V
3V; 3.3V; 1.5V
3V; 1.5V
3V or 3.3V; 1.1 or 1.2V
2.0–4.75*
4.55–4.65*
4.35–4.45*
2.85–2.95*
2.0–4.75*
2.85–2.95*
2.55–2.65*
2.85–2.95*
1.70–4.75
2.85–2.95
2.55–2.65
1.65–1.75
0.90–3.50*
1.25–1.35*
1.25–1.35*
0.95–1.05*
RESET = X40010
RESET
RESET = X40014
RESET
signal.
bus.
= X40011
= X40015
*Voltage monitor requires VCC to operation. Others are independent of VCC.
PIN CONFIGURATION
X40010/14, X40011/15
WDO
V2FAIL
V2MON
1
V
2
CC
3
4
8-Pin TSSOP
SCL
8
SDA
7
V
6
SS
RESET/RESET
5
V2FAIL
V2MON
RESET/RESET
V
SS
X40010/14, X40011/15
8-Pin SOIC
1
2
3
4
8
7
6
5
V
CC
WDO
SCL
SDA
PIN DESCRIPTION
Pin
Name FunctionSOIC TSSOP
13V2FAILV2 Voltage Fail Output. This open drain output goes LOW when V2MON is less tha n V
goes HIGH when V2MON exceeds V
24V2MONV2 Voltage Monitor Input. When the V2MON input is less than the V
. There is no power up reset delay circuitry on this pin.
TRIP2
voltage, V2FAIL goes
TRIP2
TRIP2
LOW. This input can monitor an unregulated power supply with an external resisto r divider or can
monitor a second power supply with no external components. Connect V2MON to V
not used.The V2MON comparator is supplied by V2MON (X40010/11) or by V
35RESET
RESET
/
RESET Output. (X40011/15) This is an active LOW, open drain output which goes active whenever
V
CC
falls below V
. It will remain active until VCC rises above V
TRIP1
TRIP1
CC
and for the t
or VCC when
SS
Input (X40014/15).
thereafter.
PURST
RESET Output. (X40010/14) This is an active HIGH CMOS output which goes active whenever V
46V
SS
falls below V
Ground
. It will remain active until VCC rises above V
TRIP1
and for the t
TRIP1
PURST
thereafter.
57SDASerial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires
a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to
LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the watchdog time out period results in WDO
going active.
and
CC
2
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
PIN DESCRIPTION (Continued)
Pin
Name FunctionSOIC TSSOP
68SCLSerial Clock. The Serial Clock controls the serial bus timing for data input and output.
71WDO
82V
WDO Output. WDO is an active LOW, open drain output which goes active wh enever the watchdog timer goes active.
Supply Voltage
CC
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X40010/11/14/15 activates a
Power On Reset Circuit that pulls the RESET/RESET
pins active. This signal provides several benefits.
– It prevents the system microprocessor from starting to
operate with insufficient voltage.
– It prevents the processor from operating prior to stabili-
zation of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When V
t
PURST
exceeds the device V
CC
threshold value for
TRIP1
(selectable) the circuit releases the RESET
(X40011) and RESET (X40010) pin allowing the system
to begin operation.
Low Voltage V
(V1 Monitoring)
CC
During operation, the X40010/11/14/15 monitors the
V
level and asserts RESET/RESET if supply voltage
CC
falls below a preset minimum V
RESET/RESET
signal prevents the microprocessor
TRIP1
. The
from operating in a power fail or brownout condition.
The V1FAIL
drops below 1V. It also remains active until V
and exceeds V
signal remains active until the voltage
returns
CC
TRIP1
for t
PURST
.
Low Voltage V2 Monitoring
The X40010/11/14/15 also monitors a second voltage
level and asserts V2FAIL
preset minimum V
TRIP2
if the voltage falls below a
. The V2FAIL signal is either
ORed with RESET to prevent the microprocessor from
operating in a power fail or brownout condition or used to
interrupt the microprocessor with notification of an
impending power failure. For the X40010/11 the V2FAIL
signal remains active until the VCC drops below 1V (V
CC
falling). It also remains active until V2MON returns and
exceeds V
by 0.2V. This voltage sense circuitry
TRIP2
monitors the power supply connected to the V2MON pin.
If V
= 0, V2MON can still be monitored.
CC
For the X40014/15 devices, the V2FAIL
actice until V
drops below 1Vx and remains active
CC
until V2MON returns and exceeds V
circuitry is powered by V
. If VCC = 0, V2MON cannot
CC
signal remains
. This sense
TRIP2
be monitored.
Figure 1. Two Uses of Multiple Voltage Monitoring
V
V2MON
X40011-A
3.3V
Reg
1.2V
Reg
5V
Reg
6–10V
1M
1M
Resistors selected so 3V appears on V2MON when unregulated
Unreg.
Supply
Notice: No external components required to monitor two voltages.
V
CC
RESET
V2MON
(2.9V)
V2FAIL
supply reaches 6V.
X40014-C
V
CC
RESET
V2MON
V2FAIL
CC
System
Reset
V
CC
System
Reset
3
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
Figure 2. V
WDO
SCL
SDA
Set/Reset Conditions
TRIPX
V
TRIPX
A0h
(X = 1, 2)
7
VCC/V2MON
0
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to LOW periodically, while SCL also toggles from HIGH to LOW (this is
a start bit) followed by a stop condition prior to the expiration of the watchdog time out period to prevent a WDO
signal going active. The state of two nonvolatile control
bits in the Status Register determines the watchdog timer
period. The microprocessor can change these watchdog
bits by writing to the X40010/11/14/15 control register
(also refer to page 19).
Figure 3. Watchdog Restart
.6µs
SCL
SDA
1.3µs
Timer Start
V1 AND V2 THRESHOLD PROGRAM PROCEDURE
(OPTIONAL)
The X40010/11/14/15is shipped with standard V1 and
V2 threshold (V
TRIP1, VTRIP2
) voltages. These values
will not change over normal operating and storage
conditions. However, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the
X40010/11/14/15trip points may be adjusted. The procedure is described below, and uses the application of
a high voltage control signal.
V
P
70 70
t
00h
Setting a V
Voltage (x = 1, 2)
TRIPx
WC
There are two procedures used to set the threshold
voltages (V
), depending if the threshold voltage to
TRIPx
be stored is higher or lower than the present value. For
example, if the present V
V
is 3.2 V, the new voltage can be stored directly
TRIPx
into the V
cell. If however, the new setting is to be
TRIPx
is 2.9 V and the new
TRIPx
lower than the present setting, then it is necessary to
“reset” the V
Setting a Higher V
To set a V
voltage before setting the new value.
TRIPx
Voltage (x = 1, 2)
TRIPx
threshold to a new voltage which is
TRIPx
higher than the present threshold, the user must apply
the desired V
threshold voltage to the corre-
TRIPx
sponding input pin Vcc(V1MON), or V2MON. The
Vcc(V1MON) and V2MON must be tied together during this sequence. Then, a programming voltage (Vp)
must be applied to the WDO
pin before a START condition is set up on SDA. Next, issue on the SDA pin the
Slave Address A0h, followed by the Byte Address 01h
for V
order to program V
and 09h for V
TRIP1
, and a 00h Data Byte in
TRIP2
. The STOP bit following a
TRIPx
valid write operation initiates the programming
sequence. Pin WDO
must then be brought LOW to
complete the operation.
Note: This operation does not corrupt the memory
array.
Setting a Lower V
In order to set V
present value, then V
Voltage (x = 1, 2)
TRIPx
to a lower voltage than the
TRIPx
must first be “reset” accord-
TRIPx
ing to the procedure described below. Once V
has been “reset”, then V
can be set to the desired
TRIPx
voltage using the procedure described in “Setting a
Higher V
TRIPx
Voltage”.
TRIPx
4
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
Resetting the V
To reset a V
TRIPx
age (Vp) to the WDO
Voltage
TRIPx
voltage, apply the programming volt-
pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V
and 0Bh for V
TRIP1
Data Byte in order to reset V
, followed by 00h for the
TRIP2
. The STOP bit fol-
TRIPx
lowing a valid write operation initiates the programming sequence. Pin WDO
must then be brought LOW
to complete the operation.
After being reset, the value of V
becomes a nomi-
TRIPx
nal value of 1.7V or lesser.
Note: This operation does not corrupt the memory
array.
CONTROL REGISTER
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer settings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.
The Control Register is accessed with a special preamble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte write
operation directly to the address of the register and only
one data byte is allowed for each register write operation. Prior to writing to the Control Register, the WEL
and RWEL bits must be set using a two step process,
with the whole sequence requiring 3 steps. See "Writing
to the Control Registers" on page 7.
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, BP1, and BP0. The
X40010/11/14/15 will not acknowledge any data bytes
written after the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address 01Fh,
using the special preamble. Only one byte is read by
each register read operation. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation.
76543210
PUP1 WD1 WD0 BP 0 RWEL WEL PUP0
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Figure 4. Sample V
V
TRIP1
Adj.
Reset Circuit
TRIP
V2FAIL
V
TRIP2
Adj.
RESET
4.7K
1
3
2
4
SOIC
X4001x
V
P
Adjust
8
7
6
5
Run
µC
SCL
SDA
5
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
Figure 5. V
Set/Reset Sequence (X = 1, 2)
TRIPX
applied =
New V
Old V
X
applied + | Error |
X
NO
No
V
TRIPX
Present Value
V
TRIPX
Set Higher V
Set Higher V
Apply V
> Desired V
Decrease
Programming
Desired
V
TRIPX
YES
Execute
Reset Sequence
Execute
Sequence
TRIPX
Execute
Sequence
X
and Voltage
CC
TRIPX
to
V
V
X
Vx = V
Note: X = 1, 2
Let: MDE = Maximum Desired Error
New VX applied =
applied - | Error |
Old V
X
Execute Reset V
X
Sequence
, VxMON
CC
+
MDE
Desired Value
–
MDE
Error = Actual - Desired
TRIPX
Acceptable
Error Range
Output Switches?
Error < MDE
–
Actual
Desired
DONE
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and zeros
to the other bits of the control register.
YES
V
TRIPX -
V
TRIPX
| Error | < | MDE |
Once set, WEL remains set until either it is reset to 0
(by writing a “0” to the WEL bit and zeros to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high voltage write cycle, so the device is ready for the next
operation immediately after the stop condition.
Error > MDE
+
6
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
PUP1, PUP0: Power Up Bits (Nonvolatile)
The Power Up bits, PUP1 and PUP0, determine the
t
time delay. The nominal power up times are
PURST
shown in the following table.
PUP1 PUP0 Power on Reset Delay (
0 0 50ms
0 1 200ms (factory setting)
1 0 400ms
1 1 800ms
t
PURST
)
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
WD1 WD0 Watchdog Time Out Period
0 0 1.4 seconds
0 1 200 milliseconds
1 0 25 milliseconds
1 1 disabled (factory setting)
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded by a start and ended with a stop).
– Write a 06H to the Control Register to set the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
– Write a one byte value to the Control Register that
has all the control bits set to the desired state. The
Control register can be represented as qxys 001r in
binary, where xy are the WD bits, s isthe BP bit and
qr are the power up bits. This operation proceeded
by a start and ended with a stop bit. Since this is a
nonvolatile write cycle it will take up to 10ms to
complete. The RWEL bit is reset by this cycle and
the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step
(qxys 011r) then the RWEL bit is set, but the WD1,
WD0, PUP1, PUP0, and BP bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.
– A read operation occurring between any of the
previous operations will not interrupt the register
write operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains se t.
FAULT DETECTION REGISTER
The Fault Detection Register (FDR) provides the user
the status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and three
Low Voltage Fail bits are volatile.
76543210
LV1F LV2F 0 WDF 0 0 0 0
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
can only be modified by performing a byte write
operation directly to the address of the register and
only one data byte is allowed for each register write
operation.
There is no need to set the WEL or RWEL in the
control register to access this fault detection register.
7
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
Figure 6. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable Data Change Data Stable
At power-up, the Fault Detection Reg ister is defaulted
to all “0”. The system needs to initialize this register to
all “1” before the actual monitoring take place. In the
event of any one of the monitored sources failed. The
corresponding bits in the register will change from a
“1” to a “0” to indicate the failure. At this moment, the
system should perform a read to the register and
noted the cause of the reset. After reading th e regis ter
the system should reset the register back to all “1”
again. The state of the Fault Detection Register can be
read at any time by performing a random read at
address 0FFh, using the special preamble.
The FDR can be read by performing a random read at
OFFh address of the register at any time. Only one
byte of data is read by the register read operation.
WDF, Watchdog Timer Fail Bit (Volatile)
The WDF bit will set to “0” when the WDO
LV1F, Low V
Reset Fail Bit (Volatile)
CC
The LV1F bit will be set to “0” when V
falls below V
TRIP1
.
goes active.
(V1MON)
CC
LV2F, Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to “0” when V2MON falls
below V
TRIP2
.
SERIAL INTERFACE
Interface Conventions
The device supports a bidirectional bus orie nted protocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 6.
Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 6.
Serial Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 6.
8
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
Figure 7. Valid Start and Stop Conditions
SCL
SDA
Start Stop
Serial Acknowledge
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device,
either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. See Figure 8.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are c ontained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Serial Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives
the master access to any one of the words in the
array. After receipt of the Word Address Byte, the
device responds with an acknowledge, and awaits the
next eight bits of data. After receiving the 8 bits of the
Data Byte, the device again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile
memory. During this internal write cycle, the device
inputs are disabled, so the device will not respond to any
requests from the master. The SDA output is at high
impedance. See Figure 9.
A write to a protected block of memory will suppress
the acknowledge bit.
Figure 8. Acknowledge Response From Receiver
SCL from
Master
Data Output
from
Data Output
from Receiver
Start Acknowledge
9
81 9
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
Read Operation
Prior to issuing the Slave Address Byte with the R/W
bit
set to one, the master must first perform a “dummy” write
operation. The master issues the start condition and the
Slave Address Byte, receives an acknowledge, then
issues the Word Address Bytes. After acknowledging
receipts of the Word Address Bytes, the master immedi-
Figure 9. Read Sequence
S
Signals from
the Master
SDA Bus
Signals from
the Slave
t
a
r
t
101001
Slave
Address
0
A
C
K
Byte
Address
11111111
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.
Acknowledge Polling
The disabling of the inputs during high voltage cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the
device initiates the internal high voltage cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
See Figure 12.
ately issues another start condition and the Slave
Address Byte with the R/W
bit set to one. This is followed
by an acknowledge from the device and then by the eight
bit word. The master terminates the read operation by
not responding with an acknowledge and then issuing a
stop condition. See Figure 12 for the address, acknowledge, and data transfer sequence.
S
Slave
t
a
Address
r
t
1
A
C
K
A
C
K
Data
S
t
o
p
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W
bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Random Reads, and Sequential Reads.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The
master terminates the read oper ation when it does no t
respond with an acknowledge during the ninth clock
and then issues a stop condition. See Figure 13 for the
address, acknowledge, and data transfer sequence.
10
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
Figure 10. Acknowledge Polling Sequence
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
ACK
Returned?
YES
High Voltage Cycle
Complete. Continue
Command Sequence?
YES
Continue Normal
Read or Write
Command Sequence
PROCEED
Issue STOP
NO
Issue STOP
NO
A similar operation called “Set Current Address” where
the device will perform this operation if a stop is issued
instead of the second start shown in Figure 13. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected.
This operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicating it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one operation. At the end of the address space the counter “rolls
over” to address 0000
and the device continues to out-
H
put data for each acknowledge received. See Figure 15
for the acknowledge and data transfer sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Random Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W
bit set to one, the master
must first perform a “dummy” write operation. The master
issues the start condition and the Slave Address Byte,
receives an acknowledge, then issues the Word Address
Bytes. After acknowledging receipts of the Word Address
Bytes, the master immediately issues another start condition and the Slave Address Byte with the R/W
bit set to
one. This is followed by an acknowledge from the device
and then by the eight bit word. The master terminates the
read operation by not responding with an acknowledge
and then issuing a stop condition. See Figure 14 for the
address, acknowledge, and data transfer sequence.
11
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF
hex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF
hex
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always ‘101x’. Where
x=0 is for Array, x=1 is for Control Register or Fault
Detection Register.
– next two bits are ‘0’.
– next bit that becomes the MSB of the address.
Figure 12. Current Address Read Sequence
Signals from
the Master
SDA Bus
S
t
a
r
t
Slave
Address
1010 00
– One bit of the slave command byte is a R/W
R/W
bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W
bit is a one,
then a read operation is selected. A zero selects a
write operation.
Figure 11. X40010/11/14/15 Addressing
Slave Byte
Control Register
Fault Detection Register
Control Register
Fault Detection Register
1
1011
10110000
Word Address
1
111111111111111
S
t
o
p
bit. The
1
R/W
0
R/W
Signals from
the Slave
Figure 13. Random Address Read Sequence
S
t
Signals from
the Master
SDA Bus
Signals from
the Slave
a
r
t
101 00
Slave
Address
0
A
C
K
Byte
Address
Data
S
Slave
t
a
Address
r
t
1
A
C
K
A
C
K
Data
S
t
o
p
12
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power up condition.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
– RESET/RESET
Signal is active for t
PURST
.
Figure 14. Sequential Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
Slave
Address
1
A
C
K
A
C
K
Data
(1)
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
Data
(2)
A
C
K
Data
(n-1)
(n is any integer greater than 1)
A
C
K
Data
(n)
S
t
o
p
13
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
ABSOLUTE MAXIMUM RATINGS
Temperature under bias....................-65°C to +135°C
Storage temperature .........................-65°C to +150°C
Voltage on any pin with
respect to V
...................................... -1.0V to +7V
SS
D.C. output current...............................................5mA
Lead temperature (soldering, 10 seconds)........ 300°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C 70°C
Industrial –40°C +85°C
Version
X40010/11
-A or -B
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified)
Symbol Parameter Min. Typ.
(1)
V
I
I
V
I
I
SB1
SB2
V
CC
CC1
CC2
(1)(6)
(2)(6)
I
LI
I
LO
V
IL
V
IH
HYS
V
OL
V
OH
Supply
TRIP1
Active Supply Current (VCC) Read 1.5 mA VIL = VCC x 0.1
(1)
Active Supply Current (VCC) Read 3.0 mA
Standby Current (VCC) AC (WDT off) 6 10 µA VIL = VCC x 0.1
Standby Current (VCC) DC (WDT on) 25 30 µA V
Input Leakage Current (SCL) 10 µA VIL = GND to V
Output Leakage Current (SDA,
V2FAIL
(3)
Input LOW Voltage (SDA, SCL) -0.5 V
(3)
Input HIGH Voltage (SDA, SCL) V
(6)
Schmitt Trigger Input Hysteresis
• Fixed input level
•
, WDO, RESET)
V
related level
CC
x 0.7 V
CC
0.2
.05 x V
CC
Output LOW Voltage (SDA, RESET/RESET
, V2FAIL, WDO)
Output (RESET) HIGH Voltage VCC - 0.8
V
- 0.4
CC
(5)
V
Trip Point Voltage Range 2.0 4.75 V
CC
(4)
4.55 4.6 4.65 V X40010/11-A
4.35 4.4 4.45 V X40010/11-B
2.85 2.9 2.95 V X40010/11-C,
2.55 2.6 2.65 V X40014/15-B
(6)
t
RPD2
V
to V2FAIL 5µS
TRIP2
Table 2:
Chip Supply Volt-
age
2.7V to 5.5V 2.6V to 5V
Max. Unit Test Conditions
= VCC x 0.9,
V
IH
f
SCL
VIH =
f
SCL
SDA
Others = GND or V
10 µA V
SDA
Device is in Standby
x 0.3 V
CC
+ 0.5 V
CC
V
V
0.4 V I
VI
= 3.0mA (2.7-5.5V)
OL
= 1.8mA (2.7-3.6V)
I
OL
= -1.0mA (2.7-5.5V)
OH
= -0.4mA (2.7-3.6V)
I
OH
X40014/15-A&C
Monitored*
Voltages
= 400kHz
V
x 0.9
CC
, f
= 400kHz
SDA
= V
SCL
= V
= GND to V
CC
CC
CC
CC
(2)
14
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
D.C. OPERATING CHARACTERISTICS (Continued)
(Over the recommended operating conditions unless otherwise specified)
Symbol Parameter Min. Typ.
(4)
Max. Unit Test Conditions
Second Supply Monitor
V
I
V2
TRIP2
V2MON Current 15 µA
(5)
V2MON Trip Point Voltage Range 1.7
0.9
4.75
3.5
VVX40010/11
X40014/15
2.85 2.9 2.95 V X40010/11-A
2.55 2.6 2.65 V X40010/11-B
1.65 1.7 1.75 V X40010/11-C
1.25 1.3 1.35 V X40014/15-A&B
0.95 1.0 1.05 V X40014/15-C
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or t
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; t
high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) V
Min. and VIH Max. are for reference only and are not tested.
IL
(4) At 25°C, V
(5) See Ordering Information for standard programming levels. For custom programmed levels, contact factory.
(6) Based on characterization data.
CC
= 5V.
after a stop ending a write operation.
WC
WC
after a stop that initiates a
EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2)
∆V
V
ref
VxMON
R
+
V
C
REF
–
t
RPDX
Output Pin
= 5µs worst case
∆V = 100mV
CAPACITANCE
Symbol Parameter Max. Unit Test Conditions
(1)
C
OUT
(1)
C
IN
Note: (1) This parameter is not 100% tested.
Output Capacitance (SDA, RESET, RESET, V2FAIL,
)
WDO
Input Capacitance (SCL) 6 pF VIN = 0V
8pFV
OUT
= 0V
15
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR
V
= 5V
CC
SDA
5V
2.06KΩ
RESET
30pF
WDO
V
OUT
4.6KΩ
V2FAIL
30pF
V2MON
4.6KΩ
30pF
A.C. TEST CONDITIONS
Input pulse levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing levels
V
x 0.5
CC
Output load Standard output load
SYMBOL TABLE
WAVEFORM INPUTS OUTPUTS
Must be
steady
May change
from LOW
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A Center Line
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
is High
Impedance
16
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
A.C. CHARACTERISTICS
400kHz
Symbol Parameter
f
SCL
t
IN
t
AA
t
BUF
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
DH
t
R
t
F
Cb Capacitive load for each bus line 400 pF
SCL Clock Frequency 0 400 kHz
Pulse width Suppression Time at inputs 50 ns
SCL LOW to SDA Data Out Valid 0.1 0.9 µs
Time the bus free before start of new transmission 1.3 µs
Clock LOW Time 1.3 µs
Clock HIGH Time 0.6 µs
Start Condition Setup Time 0.6 µs
Start Condition Hold Time 0.6 µs
Data In Setup Time 100 ns
Data In Hold Time 0 µs
Stop Condition Setup Time 0.6 µs
Data Output Hold Time 50 ns
SDA and SCL Rise Time 20 +.1Cb
SDA and SCL Fall Time 20 +.1Cb
(1)
(1)
300 ns
300 ns
UnitMin. Max.
Note: (1) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
t
F
SCL
SDA IN
SDA OUT
t
SU:STA
t
HD:STA
t
SU:DAT
t
HIGH
t
LOW
t
HD:DAT
t
R
t
SU:STO
t
t
DH
AA
t
BUF
17
FN8111.0
March 28, 2005
Write Cycle Timing
SCL
X40010, X40011, X40014, X40015
SDA
8th Bit of Last Byte
ACK
Stop
Condition
t
WC
Start
Condition
Nonvolatile Write Cycle Timing
Symbol Parameter Min. Typ.
(1)
t
WC
Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Write Cycle Time 5 10 ms
(1)
Max. Unit
Power Fail Timings
t
V
TRIPX
V
or
CC
V2MON
[]
LOWLINE or
[]
V2FAIL
V3FAIL
or
R
t
RPDL
t
RPDX
V
RVALID
t
RPDL
t
RPDX
t
RPDL
t
RPDX
t
F
X = 2, 3
18
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
RESET/RESET Timings
V
TRIP1
V
CC
t
PURST
t
R
RESET
RESET
V
RVALID
LOW VOLTAGE AND WATCHDOG TIMING PARAMETERS
t
RPD1
t
PURST
t
F
Symbol Parameters Min. Typ.
(2)
t
RPD1
t
RPDX
t
PURST
V
to RESET/RESET (Power down only) 5 µs
TRIP1
(2)
V
to V2FAIL 5µs
TRIP2
Power On Reset delay:
PUP1=0, PUP0=0
PUP1=0, PUP0=1 (factory setting)
PUP1=1, PUP0=0
PUP1=1, PUP0=1
V
RVALID
t
WDO
t
t
V
F
R
V2MON, Fall Time 20 mV/µs
CC,
V
V2MON, Rise Time 20 mV/µs
CC,
Reset Valid V
Watchdog Timer Period:
CC
1V
WD1=0, WD0=0
WD1=0, WD0=1
WD1=1, WD0=0
WD1=1, WD0=1 (factory setting)
t
RST1
Watchdog Reset Time Out Delay
100 200 300 ms
WD1=0, WD0=0
WD1=0, WD0=1
t
RST2
t
RSP
Notes: (1) VCC = 5V at 25°C.
Watchdog Reset Time Out Delay WD1=1, WD0=0 12.5 25 37.5 ms
Watchdog timer restart pulse width 1 µs
(2) Values based on characterization data only.
50
200
400
800
1.4
200
25
OFF
(1)
Max. Unit
(2)
(2)
(2)
(2)
(2)
ms
ms
ms
ms
s
ms
ms
19
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
Watchdog Time Out For 2-Wire Interface
Start
SCL
SDA
Clockin (0 or 1)
t
RSP
< t
WDO
Start
t
RST
t
WDOtRST
Set/Reset Conditions
V
TRIPX
t
TSU
WDO
SCL
WDO
Start
Minimum Sequence to Reset WDT
SCL
SDA
(V
)
TRIPX
t
VPS
7
0
0
VCC/V2MON
WDT
Restart
V
P
70 7
t
THD
t
VPH
t
VPO
SDA
Start
A0h
20
01h*
09h*
sets V
TRIP1
sets V
TRIP2
* all others reserved
03h*
0Bh*
resets V
resets V
TRIP1
TRIP2
00h
t
WC
FN8111.0
March 28, 2005
X40010, X40011, X40014, X40015
V
, V
TRIP1
Parameter Description Min. Max. Unit
t
VPS
t
VPH
t
TSU
t
THD
t
WC
t
VPO
V
P
V
TRAN1
V
TRAN2
V
TRAN2A
V
tv
t
VPS
, Programming Specifications: VCC = 2.0-5.5V; Temperature = 25°C
TRIP2
WDO Program Voltage Setup time 10 µs
WDO Program Voltage Hold time 10 µs
V
Level Setup time 10 µs
TRIPX
V
Level Hold (stable) time 10 µs
TRIPX
V
Program Cycle 10 ms
TRIPX
Program Voltage Off time before next cycle 1 ms
Programming Voltage 15 18 V
V
Set Voltage Range 2.0 4.75 V
TRIP1
V
Set Voltage Range – X40010/11 1.7 4.75 V
TRIP2
V
Set to Voltage Range – X40014/15 0.9 3.5 V
TRIP2
V
Set Voltage variation after programming (-40 to +85°C). -25 +25 mV
TRIPX
WDO Program Voltage Setup time 10 µs
21
FN8111.0
March 28, 2005
PACKAGING INFORMATION
X40010, X40011, X40014, X40015
8-Lead Plastic, SOIC, Package Code S8
Pin 1 Index
(4X) 7°
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
Pin 1
X 45°
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
0.150 (3.80)
0.158 (4.00)
0.004 (0.19)
0.010 (0.25)
0.228 (5.80)
0.244 (6.20)
0.053 (1.35)
0.069 (1.75)
0.050" Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.250"
22
0.030"
Typical
8 PlacesFOOTPRINT
0.050"
Typical
FN8111.0
March 28, 2005
PACKAGING INFORMATION
X40010, X40011, X40014, X40015
8-Lead Plastic, TSSOP, Package Code V8
.025 (.65) BSC
0° - 8°
.019 (.50)
.029 (.75)
Detail A (20X)
.114 (2.9)
.122 (3.1)
.0075 (.19)
.0118 (.30)
.010 (.25)
.169 (4.3)
.177 (4.5)
.002 (.05)
.006 (.15)
Gage Plane
Seating Plane
.252 (6.4) BSC
.047 (1.20)
(4.16)
(7.72)
See Detail “A”
(1.78)
.031 (.80)
.041 (1.05)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
(0.42)
All Measurements Are Typical
23
(0.65)
FN8111.0
March 28, 2005
ORDERING INFORMATION
X40010, X40011, X40014, X40015
V
CC
Range V
TRIP1
Range V
Range Package
TRIP2
Operating Temperature Range
Part Number
with RESET
Part Number
with RESET
2.9-5.5 4.6V±50mV 2.9V±50mV 8L SOIC 0oC - 70oC X40010S8-A X40011S8-A
o
-40
C - 85oC X40010S8I-A X40011S8I-A
8L TSSOP 0
2.6-5.5 4.4V±50mV 2.6V±50mV 8L SOIC 0
8L TSSOP 0
1.7-3.6 2.9V±50mV 1.7V±50mV 8L SOIC 0
8L TSSOP 0
1.3-3.6 2.9V±50mV 1.3V±50mV 8L SOIC 0
8L TSSOP 0
1.3-3.6 2.6V±50mV 1.3V±50mV 8L SOIC 0
8L TSSOP 0
1.0-3.6 2.9V±50mV 1.0V±50mV 8L SOIC 0
8L TSSOP 0
o
C - 70oC X40010V8-A X40011V8-A
o
-40
C - 85oC X40010V8I-A X40011V8I-A
o
C - 70oC X40010S8-B X40011S8-B
o
-40
C - 85oC X40010S8I-B X40011S8I-B
o
C - 70oC X40010V8-B X40011V8-B
o
-40
C - 85oC X40010V8I-B X40011V8I-B
o
C - 70oC X40010S8-C X40011S8-C
o
-40
C - 85oC X40010S8I-C X40011S8I-C
o
C - 70oC X40010V8-C X40011V8-C
o
-40
C - 85oC X40010V8I-C X40011V8I-C
o
C - 70oC X40014S8-A X40015S8-A
o
-40
C - 85oC X40014S8I-A X40015S8I-A
o
C - 70oC X40014V8-A X40015V8-A
o
-40
C - 85oC X40014V8I-A X40015V8I-A
o
C - 70oC X40014S8-B X40015S8-B
o
-40
C - 85oC X40014S8I-B X40015S8I-B
o
C - 70oC X40014V8-B X40015V8-B
o
-40
C - 85oC X40014V8I-B X40015V8I-B
o
C - 70oC X40014S8-C X40015S8-C
o
-40
C - 85oC X40014S8I-C X40015S8I-C
o
C - 70oC X40014V8-C X40015V8-C
o
-40
C - 85oC X40014V8I-C X40015V8I-C
PART MARK INFORMATION
8-Lead Package
X4001XX
YYWWXX
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
24
0/1/4/5
Package - S/V
A, B, or C
I – Industrial
Blank – Commercial
WW – Workweek
YY – Year
FN8111.0
March 28, 2005
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