intersil X40410, X40411, X40414, X40415 DATA SHEET

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X40010, X40011, X40014, X40015

Data Sheet March 28, 2005

Dual Voltage Monitor with Integrated CPU Supervisor

FEATURES

• Dual voltage detection and reset assertion —Standard reset threshold settings

See Selection table on page 2.

—Adjust low voltage reset threshold voltages

using special programming sequence —Reset signal valid to V —Monitor three voltages or detect power fail

• Independent Core Voltage Monitor (V2MON)

• Fault detection register

• Selectable power on reset timeout (0.05s,

0.2s, 0.4s, 0.8s)

• Selectable watchdog timer interval (25ms, 200ms,1.4s, off)

• Low power CMOS —25µA typical standby current, watchdog on —6µA typical standby current, watchdog off

• 400kHz 2-wire interface

• 2.7V to 5.5V power supply operation

• Available packages —8-lead SOIC, TSSOP

• Monitor Voltages: 5V to 0.9V

• Independent Core Voltage Monitor

= 1V

FN8111.0

APPLICATIONS

• Communication Equipment —Routers, Hubs, Switches —Disk Arrays, Network Storage

• Industrial Systems —Process Control —Intelligent Instrumentation

• Computer Systems —Computers —Network Servers

DESCRIPTION

The X40010/11/14/15 combines power-on reset control, watchdog timer, supply voltage supervision, and secondary voltage supervision, in one package. This combination lowers system cost, reduces board space requirements, and increases reliability.

Applying voltage to V circuit which holds RESET/RESET

activates the power on reset

active for a period of time. This allows the power supply and system oscillator to stabilize before the processor can execute code.

BLOCK DIAGRAM

SDA

SCL

(V1MON)

V2MON

Data

Command

Decode Test

& Control

Logic

Threshold

Reset Logic

User Programmable

TRIP1

User Programmable

TRIP2

Fault Detection

Status

V2MON V

*X40010/11 = V2MON*

X40014/15 = V

Watchdog Timer

and

Reset Logic

Power on,

Low Voltage

Reset

Generation

WDO

RESET

X40010/14

RESET

X40011/15

V2FAIL

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X40010, X40011, X40014, X40015

Low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V RESET/RESET

falls below the minimum V

is active until VCC returns to proper

TRIP1

point.

operating level and stabilizes. A second voltage monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. Three common low voltage combinations are available, however, Intersil’s unique circuits allows the threshold for either voltage monitor to be repro-

The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the WDO The user selects the interval from th ree preset values. Once selected, the interval does not change, even after cycling the power.

The device features a 2-wire interface and software protocol allowing operation on an I

2C®

grammed to meet special needs or to fine-tune the threshold for applications requiring higher precision.

Dual Voltage Monitors

Table 1:

Device Expected System Voltages Vtrip1(V) Vtrip2(V) POR (system)

X40010/11

-A

-B

-C

X40014/15

-A

-B

-C

5V; 3V or 3.3V

5V; 3V

3V; 3.3V; 1.8V

3V; 3.3V; 1.5V

3V; 1.5V

3V or 3.3V; 1.1 or 1.2V

2.0–4.75*

4.55–4.65*

4.35–4.45*

2.85–2.95*

2.0–4.75*

2.85–2.95*

2.55–2.65*

2.85–2.95*

1.70–4.75

2.85–2.95

2.55–2.65

1.65–1.75

0.90–3.50*

1.25–1.35*

0.95–1.05*

RESET = X40010 RESET

RESET = X40014 RESET

signal.

bus.

= X40011

= X40015

*Voltage monitor requires VCC to operation. Others are independent of VCC.

PIN CONFIGURATION

X40010/14, X40011/15

WDO

V2FAIL

V2MON

3 4

8-Pin TSSOP

SCL

SDA

RESET/RESET

V2FAIL

V2MON

RESET/RESET

X40010/14, X40011/15

8-Pin SOIC

1 2 3 4

8 7 6 5

WDO SCL SDA

PIN DESCRIPTION

Name FunctionSOIC TSSOP

13V2FAILV2 Voltage Fail Output. This open drain output goes LOW when V2MON is less tha n V

goes HIGH when V2MON exceeds V

24V2MONV2 Voltage Monitor Input. When the V2MON input is less than the V

. There is no power up reset delay circuitry on this pin.

TRIP2

voltage, V2FAIL goes

TRIP2

LOW. This input can monitor an unregulated power supply with an external resisto r divider or can monitor a second power supply with no external components. Connect V2MON to V not used.The V2MON comparator is supplied by V2MON (X40010/11) or by V

35RESET

RESET

RESET Output. (X40011/15) This is an active LOW, open drain output which goes active whenever V

falls below V

. It will remain active until VCC rises above V

TRIP1

and for the t

or VCC when

Input (X40014/15).

thereafter.

PURST

RESET Output. (X40010/14) This is an active HIGH CMOS output which goes active whenever V

46V

falls below V Ground

. It will remain active until VCC rises above V

TRIP1

and for the t

TRIP1

PURST

thereafter.

57SDASerial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open

drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated).

Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the watchdog time out period results in WDO

going active.

and

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PIN DESCRIPTION (Continued)

Name FunctionSOIC TSSOP

68SCLSerial Clock. The Serial Clock controls the serial bus timing for data input and output. 71WDO

82V

WDO Output. WDO is an active LOW, open drain output which goes active wh enever the watchdog timer goes active.

Supply Voltage

PRINCIPLES OF OPERATION

Power On Reset

Application of power to the X40010/11/14/15 activates a Power On Reset Circuit that pulls the RESET/RESET pins active. This signal provides several benefits.

– It prevents the system microprocessor from starting to

operate with insufficient voltage.

– It prevents the processor from operating prior to stabili-

zation of the oscillator.

– It allows time for an FPGA to download its configura-

tion prior to initialization of the circuit.

– It prevents communication to the EEPROM, greatly

reducing the likelihood of data corruption on power up.

When V t

PURST

exceeds the device V

threshold value for

TRIP1

(selectable) the circuit releases the RESET (X40011) and RESET (X40010) pin allowing the system to begin operation.

Low Voltage V

(V1 Monitoring)

During operation, the X40010/11/14/15 monitors the V

level and asserts RESET/RESET if supply voltage

falls below a preset minimum V RESET/RESET

signal prevents the microprocessor

TRIP1

. The

from operating in a power fail or brownout condition. The V1FAIL drops below 1V. It also remains active until V and exceeds V

signal remains active until the voltage

returns

TRIP1

for t

PURST

Low Voltage V2 Monitoring

The X40010/11/14/15 also monitors a second voltage level and asserts V2FAIL preset minimum V

TRIP2

if the voltage falls below a

. The V2FAIL signal is either ORed with RESET to prevent the microprocessor from operating in a power fail or brownout condition or used to interrupt the microprocessor with notification of an impending power failure. For the X40010/11 the V2FAIL signal remains active until the VCC drops below 1V (V

falling). It also remains active until V2MON returns and exceeds V

by 0.2V. This voltage sense circuitry

TRIP2

monitors the power supply connected to the V2MON pin. If V

= 0, V2MON can still be monitored.

For the X40014/15 devices, the V2FAIL actice until V

drops below 1Vx and remains active

until V2MON returns and exceeds V circuitry is powered by V

. If VCC = 0, V2MON cannot

signal remains

. This sense

TRIP2

be monitored.

Figure 1. Two Uses of Multiple Voltage Monitoring

V2MON

X40011-A

3.3V Reg

1.2V Reg

Reg

6–10V

Resistors selected so 3V appears on V2MON when unregulated

Unreg. Supply

Notice: No external components required to monitor two voltages.

RESET

V2MON (2.9V)

V2FAIL

supply reaches 6V.

X40014-C

RESET

V2MON

V2FAIL

System Reset

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Figure 2. V

WDO

SCL

SDA

Set/Reset Conditions

TRIPX

A0h

(X = 1, 2)

VCC/V2MON

WATCHDOG TIMER

The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to LOW periodically, while SCL also toggles from HIGH to LOW (this is a start bit) followed by a stop condition prior to the expiration of the watchdog time out period to prevent a WDO signal going active. The state of two nonvolatile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits by writing to the X40010/11/14/15 control register (also refer to page 19).

Figure 3. Watchdog Restart

.6µs

SCL

SDA

1.3µs

Timer Start

V1 AND V2 THRESHOLD PROGRAM PROCEDURE (OPTIONAL)

The X40010/11/14/15is shipped with standard V1 and V2 threshold (V

TRIP1, VTRIP2

) voltages. These values will not change over normal operating and storage conditions. However, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the X40010/11/14/15trip points may be adjusted. The procedure is described below, and uses the application of a high voltage control signal.

70 70

00h

Setting a V

Voltage (x = 1, 2)

TRIPx

There are two procedures used to set the threshold voltages (V

), depending if the threshold voltage to

TRIPx

be stored is higher or lower than the present value. For example, if the present V V

is 3.2 V, the new voltage can be stored directly

TRIPx

into the V

cell. If however, the new setting is to be

TRIPx

is 2.9 V and the new

TRIPx

lower than the present setting, then it is necessary to “reset” the V

Setting a Higher V

To set a V

voltage before setting the new value.

TRIPx

Voltage (x = 1, 2)

TRIPx

threshold to a new voltage which is

TRIPx

higher than the present threshold, the user must apply the desired V

threshold voltage to the corre-

TRIPx

sponding input pin Vcc(V1MON), or V2MON. The Vcc(V1MON) and V2MON must be tied together during this sequence. Then, a programming voltage (Vp) must be applied to the WDO

pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h, followed by the Byte Address 01h for V order to program V

and 09h for V

TRIP1

, and a 00h Data Byte in

TRIP2

. The STOP bit following a

TRIPx

valid write operation initiates the programming sequence. Pin WDO

must then be brought LOW to

complete the operation. Note: This operation does not corrupt the memory

array.

Setting a Lower V

In order to set V present value, then V

Voltage (x = 1, 2)

TRIPx

to a lower voltage than the

TRIPx

must first be “reset” accord-

TRIPx

ing to the procedure described below. Once V has been “reset”, then V

can be set to the desired

TRIPx

voltage using the procedure described in “Setting a Higher V

TRIPx

Voltage”.

TRIPx

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X40010, X40011, X40014, X40015

Resetting the V

To reset a V

TRIPx

age (Vp) to the WDO

Voltage

TRIPx

voltage, apply the programming volt-

pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h followed by the Byte Address 03h for V

and 0Bh for V

TRIP1

Data Byte in order to reset V

, followed by 00h for the

TRIP2

. The STOP bit fol-

TRIPx

lowing a valid write operation initiates the programming sequence. Pin WDO

must then be brought LOW

to complete the operation. After being reset, the value of V

becomes a nomi-

TRIPx

nal value of 1.7V or lesser. Note: This operation does not corrupt the memory

array.

CONTROL REGISTER

The Control Register provides the user a mechanism for changing the Block Lock and Watchdog Timer settings. The Block Lock and Watchdog Timer bits are nonvolatile and do not change when power is removed.

The Control Register is accessed with a special preamble in the slave byte (1011) and is located at address 1FFh. It can only be modified by performing a byte write operation directly to the address of the register and only

one data byte is allowed for each register write operation. Prior to writing to the Control Register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. See "Writing to the Control Registers" on page 7.

The user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores WD1, WD0, PUP1, PUP0, BP1, and BP0. The X40010/11/14/15 will not acknowledge any data bytes written after the first byte is entered.

The state of the Control Register can be read at any time by performing a random read at address 01Fh, using the special preamble. Only one byte is read by each register read operation. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation.

76543210

PUP1 WD1 WD0 BP 0 RWEL WEL PUP0

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit must be set to “1” prior to a write to the Control Register.

Figure 4. Sample V

TRIP1

Adj.

Reset Circuit

TRIP

V2FAIL

TRIP2

Adj.

RESET

4.7K

1 3 2 4

SOIC

X4001x

Adjust

8 7 6 5

Run

µC

SCL SDA

FN8111.0

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X40010, X40011, X40014, X40015

Figure 5. V

Set/Reset Sequence (X = 1, 2)

TRIPX

applied =

New V

Old V

applied + | Error |

TRIPX

Present Value

TRIPX

Set Higher V

Apply V

> Desired V

Decrease

Programming

Desired

TRIPX

YES

Execute

Reset Sequence

Execute

Sequence

TRIPX

Execute

Sequence

and Voltage

TRIPX

Vx = V

Note: X = 1, 2 Let: MDE = Maximum Desired Error

New VX applied =

applied - | Error |

Old V

Execute Reset V

Sequence

, VxMON

MDE

Desired Value

–

MDE

Error = Actual - Desired

TRIPX

Acceptable

Error Range

Output Switches?

Error < MDE

–

Actual

Desired

DONE

WEL: Write Enable Latch (Volatile)

The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeros to the other bits of the control register.

YES

TRIPX -

TRIPX

| Error | < | MDE |

Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeros to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the stop condition.

Error > MDE

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PUP1, PUP0: Power Up Bits (Nonvolatile)

The Power Up bits, PUP1 and PUP0, determine the

time delay. The nominal power up times are

PURST

shown in the following table.

PUP1 PUP0 Power on Reset Delay (

0 0 50ms 0 1 200ms (factory setting) 1 0 400ms 1 1 800ms

PURST

)

WD1, WD0: Watchdog Timer Bits (Nonvolatile)

The bits WD1 and WD0 control the period of the Watchdog Timer. The options are shown below.

WD1 WD0 Watchdog Time Out Period

0 0 1.4 seconds 0 1 200 milliseconds 1 0 25 milliseconds 1 1 disabled (factory setting)

Writing to the Control Registers

Changing any of the nonvolatile bits of the control and trickle registers requires the following steps:

– Write a 02H to the Control Register to set the Write

Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a start and ended with a stop).

– Write a 06H to the Control Register to set the

Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop).

– Write a one byte value to the Control Register that

has all the control bits set to the desired state. The Control register can be represented as qxys 001r in binary, where xy are the WD bits, s isthe BP bit and qr are the power up bits. This operation proceeded by a start and ended with a stop bit. Since this is a nonvolatile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (qxys 011r) then the RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and BP bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK.

– A read operation occurring between any of the

previous operations will not interrupt the register write operation.

– The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block.

To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains se t.

FAULT DETECTION REGISTER

The Fault Detection Register (FDR) provides the user the status of what causes the system reset active. The Manual Reset Fail, Watchdog Timer Fail and three Low Voltage Fail bits are volatile.

76543210

LV1F LV2F 0 WDF 0 0 0 0

The FDR is accessed with a special preamble in the slave byte (1011) and is located at address 0FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation.

There is no need to set the WEL or RWEL in the control register to access this fault detection register.

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Figure 6. Valid Data Changes on the SDA Bus

SCL

SDA

Data Stable Data Change Data Stable

At power-up, the Fault Detection Reg ister is defaulted to all “0”. The system needs to initialize this register to all “1” before the actual monitoring take place. In the event of any one of the monitored sources failed. The corresponding bits in the register will change from a “1” to a “0” to indicate the failure. At this moment, the system should perform a read to the register and noted the cause of the reset. After reading th e regis ter the system should reset the register back to all “1” again. The state of the Fault Detection Register can be read at any time by performing a random read at address 0FFh, using the special preamble.

The FDR can be read by performing a random read at OFFh address of the register at any time. Only one byte of data is read by the register read operation.

WDF, Watchdog Timer Fail Bit (Volatile)

The WDF bit will set to “0” when the WDO

LV1F, Low V

Reset Fail Bit (Volatile)

The LV1F bit will be set to “0” when V falls below V

TRIP1

goes active.

(V1MON)

LV2F, Low V2MON Reset Fail Bit (Volatile)

The LV2F bit will be set to “0” when V2MON falls below V

TRIP2

SERIAL INTERFACE

Interface Conventions

The device supports a bidirectional bus orie nted protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications.

Serial Clock and Data

Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 6.

Serial Start Condition

All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 6.

Serial Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure 6.

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