intersil X28C010, X28HT010 DATA SHEET
®
www.BDTIC.com/Intersil
X28C010, X28HT010
Data Sheet February 12, 2007
5V, Byte Alterable EEPROM
The Intersil X28C010/X28HT010 is a 128K x 8 EEPROM,
fabricated with Intersil's proprietary, high performance,
floating gate CMOS technology. Like all Intersil
programmable non-volatile memories, the
X28C010/X28HT010 is a 5V only device. The
X28C010/X28HT010 features the JEDEC approved pin out
for byte-wide memories, compatible with industry standard
EEPROMs.
The X28C010/X28HT010 supports a 256-byte page write
operation, effectively providing a 19µs/byte write cycle and
enabling the entire memory to be typically written in less
than 2.5 seconds. The X28C010/X28HT010 also features
DATA Polling and Toggle Bit Polling, system software
support schemes used to indicate the early completion of a
write cycle. In addition, the X28C010/X28HT010 supports
Software Data Protection option.
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Data retention is specified to
be greater than 100 years.
FN8105.1
Features
• Access time: 120ns
• Simple byte and page write
- Single 5V supply
cell
control
PP
- No external high voltages or V
circuits
- Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low power CMOS
- Active: 50mA
- Standby: 500µA
• Software data protection
- Protects data against system level inadvertent writes
• High speed page write capability
• Highly reliable Direct Write
™
- Endurance: 100,000 write cycles
- Data retention: 100 years
• Early end of write detection
-DATA
polling
- Toggle bit polling
• X28HT010 is fuly functional @ +175°C
Pinouts
NC
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
CERDIP
Flat Pack
SOIC (R)
1
2
3
4
5
6
7
8
X28C010
9
10
11
12
13
14
15
16
PGA
I/O
I/O
I/O
I/O
0
2
15
17
19
V
32
CC
WE
31
30
NC
29
A
14
28
A
13
27
A
8
26
A
9
25
A
11
24
OE
23
A
10
22
CE
21
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
20
19
18
17
A
I/O
A
0
1
14
13
A
A
3
2
11
12
A
A
5
4
9
10
A
A
7
6
7
8
A
A
12
15
6
5
A
16
4
V
1
SS
16
18
X28C010
(Bottom View)
V
CC
2NC36
3NC1NC35
I/O
3
5
6
21
22
I/O
20
NC
34
WE
CE
I/O
4
7
23
24
OE
A
10
26
25
A
A
9
11
28
27
A
A
13
8
30
29
A
NC
14
31
32
NC
33
EXTENDED LCC
12
A
A
A
5
7
A
6
6
A
7
5
A
8
4
X28C010
A
9
3
(Top View)
A
10
2
A
11
1
A
12
0
13
I/O
0
15 1716 18 19 2014
1
I/O
15
16
A
NC
23243 31
1
2
3
SS
I/O
I/O
V
CC
NC
V
WE
30
A
29
14
A
28
13
A
27
8
A
26
9
A
25
11
OE
24
A
23
10
CE
22
21
I/O
7
4
5
6
I/O
I/O
I/O
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright Intersil Americas Inc. 2005, 2007. All Rights Reserved
Ordering Information
www.BDTIC.com/Intersil
X28C010, X28HT010
ACCESS
PART NUMBER PART MARKING
X28C010D-12 X28C010D-12 120ns 0 to +70 32-Ld Cerdip F32.6
X28C010D-15 X28C010D-15 150ns 0 to +70 32-Ld Cerdip F32.6
X28C010DI X28C010DI - -40 to +85 32-Ld Cerdip F32.6
X28C010DI-12 X28C010DI-12 120ns -40 to +85 32-Ld Cerdip F32.6
X28C010DI-15 X28C010DI-15 150ns -40 to +85 32-Ld Cerdip F32.6
X28C010DM X28C010DM - -55 to +125 32-Ld Cerdip F32.6
X28C010DM-12 X28C010DM-12 120ns -55 to +125 32-Ld Cerdip F32.6
X28C010DM-15 X28C010DM-15 150ns -55 to +125 32-Ld Cerdip F32.6
X28C010DMB-12 C X28C010DMB-12 120ns MIL-STD-883 32-Ld Cerdip F32.6
X28C010DMB-15 C X28C010DMB-15 150ns MIL-STD-883 32-Ld Cerdip F32.6
X28C010DMB-20 C X28C010DMB-20 200ns MIL-STD-883 32-Ld Cerdip
X28C010FI-12 X28C010FI-12 120ns -40 to +85 32-Ld Flat Pack
X28C010FI-15 X28C010FI-15 150ns -40 to +85 32-Ld Flat Pack
X28C010FI-20 X28C010FI-20 200ns -40 to +85 32-Ld Flat Pack
X28C010FM X28C010FM - -55 to +125 32-Ld Flat Pack
X28C010FM-12 X28C010FM-12 120ns -55 to +125 32-Ld Flat Pack
X28C010FMB-12 C X28C010FMB-12 120ns MIL-STD-883 32-Ld Flat Pack
X28C010FMB-15 C X28C010FMB-15 150ns MIL-STD-883 32-Ld Flat Pack
X28C010K-25 X28C010K-25 250ns 0 to +70 36-Ld Pin Grid Array G36.760x760A
X28C010KM-12 X28C010KM-12 120ns -55 to +125 36-Ld Pin Grid Array G36.760x760A
X28C010KM-25 X28C010KM-25 250ns -55 to +125 36-Ld Pin Grid Array G36.760x760A
X28C010KMB-12 C X28C010KMB-12 120ns MIL-STD-883 36-Ld Pin Grid Array G36.760x760A
X28C010KMB-15 C X28C010KMB-15 150ns MIL-STD-883 36-Ld Pin Grid Array G36.760x760A
X28C010NM-12 X28C010NM-12 120ns -55 to +125 32-Ld Extended LCC
X28C010NM-15 X28C010NM-15 150ns -55 to +125 32-Ld Extended LCC
X28C010NMB-12 C X28C010NMB-12 120ns MIL-STD-883 32-Ld Extended LCC
X28C010NMB-15 C X28C010NMB-15 150ns MIL-STD-883 32-Ld Extended LCC
X28C010RI-12 X28C010RI-12 120ns -40 to +85 32-Ld Ceramic SOIC (Gull Wing)
X28C010RI-20 X28C010RI-20 200ns -40 to +85 32-Ld Ceramic SOIC (Gull Wing)
X28C010RI-20T1 X28C010RI-20 200ns -40 to +85 32-Ld Ceramic SOIC (Gull Wing)
X28C010RM-15 X28C010RM-15 150ns -55 to +125 32-Ld Ceramic SOIC (Gull Wing)
X28C010RMB-25 C X28C010RMB-25 250ns MIL-STD-883 32-Ld Ceramic SOIC (Gull Wing)
X28HT010W 200ns -40 to +175 Wafer
TIME
TEMP RANGE
(°C) PACKAGE PKG. DWG #
2
FN8105.1
February 12, 2007
Block Diagram
www.BDTIC.com/Intersil
X28C010, X28HT010
X Buffers
A
8-A16
A0-A
7
V
V
CE
OE
WE
CC
SS
Latches and
Decoder
Y Buffers
Latches and
Decoder
Control
Logic and
Timing
Pin Descriptions
Addresses (A0-A16)
The Address inputs select an 8-bit memory location during a
read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE
reduced.
Output Enable (OE
The Output Enable input controls the d ata output buffers,
and is used to initiate read operations.
Data In/Data Out (I/O0-I/O7)
Data is written to or read from the X28C010/X28HT010
through the I/O pins.
is HIGH, power consumption is
)
1Mbit
EEPROM
Array
I/O Buffers
and Latches
I/O0-I/O
Data Inputs/Outputs
Pin Names
SYMBOL DESCRIPTION
A0-A
16
-I/O
I/O
0
WE
CE Chip Enable
OE
V
CC
V
SS
NC No Connect
*-3V
V
BB
applies to X28HT010 only.
*V
BB
7
Address Inputs
7
Data Input/Output
Write Enable
Output Enable
+5V
Ground
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C010/X28HT010.
Back Bias Voltage (VBB) (X28HT010 only)
It is required to provide -3V on pin 1. This negative voltage
improves higher temperature functionality.
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in
a high impedance state when either OE
Write
Write operations are initiated when both CE and WE are
LOW and OE
both a CE
and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE
whichever occurs last. Similarly, the data is latched internally
by the rising edge of either CE
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
3
or OE returning
or CE is HIGH.
is HIGH. The X28C010/X28HT010 supports
or WE,
or WE, whichever occurs first.
FN8105.1
February 12, 2007
X28C010, X28HT010
www.BDTIC.com/Intersil
Page Write Operation
The page write feature of the X28C010/X28HT010 allows
the entire memory to be written in 5 seconds. Page write
allows two to two hundred fifty-six bytes of data to be
consecutively written to the X28C010/X28HT010 prior to the
commencement of the internal programming cycle. The host
can fetch data from another device within the system during
a page write operation (change the source address), but the
page address (A
write cycle to the part during this operation must be the same
as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to two hundred fifty six bytes in the
same manner as the first byte was written. Each successive
byte load cycle, started by the WE
must begin within 100µs of the falling edge of the preceding
WE
. If a subsequent WE HIGH to LOW transition is not
detected within 100µs, the internal automatic programming
cycle will commence. There is no page write window
limitation. Effectively the page write window is infinitely wide,
so long as the host continues to access the device within the
byte load cycle time of 100µs.
Write Operation Status Bits
The X28C010/X28HT010 provides the user two write
operation status bits. These can be used to optimize a
system write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
through A16) for each subsequent valid
8
HIGH to LOW transition,
5TBDP 43210I/O
Reserved
Toggle Bit
DATA
Polling
FIGURE 1. STATUS BIT ASSIGNMENT
DATA Polling (I/O7)
The X28C010/X28HT010 features DATA Polling as a
method to indicate to the host system that the byte write or
page write cycle has completed. DATA
Polling allows a
simple bit test operation to determine the status of the
X28C010/X28HT010, eliminating additional interrupt inputs
or external hardware. During the internal programming cycle,
any attempt to read the last byte written will produce the
complement of that data on I/O
(i.e., write data = 0xxx xxxx,
7
read data = 1xxx xxxx). Once the programming cycle is
complete, I/O
will reflect true data. Note: If the
7
X28C010/X28HT010 is in the protected state, and an illegal
write operation is attempted, DATA
Polling will not operate.
Toggle Bit (I/O6)
The X28C010/X28HT010 also provides another method for
determining when the internal write cycle is complete. During
the internal programming cycle, I/O
LOW and LOW to HIGH on subsequent attempts to read the
device. When the internal cycle is complete the toggling will
cease and the device will be accessible for additional read or
write operations.
will toggle from HIGH to
6
DATA Polling I/O
WE
CE
OE
I/O
7
A0-A
14
7
Last
Write
V
A
IH
n
HIGH Z
V
OL
A
n
A
n
FIGURE 2. DATA POLLING BUS SEQUENCE
A
n
A
n
A
n
V
OH
X28C010
Ready
A
n
4
FN8105.1
February 12, 2007
Write Data
www.BDTIC.com/Intersil
X28C010, X28HT010
DATA Polling can effectively halve the time for writing to the
X28C010/X28HT010. The timing diagram in Figure 2
illustrates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implementing the routine.
Writes
Complete?
Yes
Save Last Data
and Address
Read Last
Address
IO
7
Compare?
Yes
X28C010
Ready
No
No
FIGURE 3. DATA POLLING SOFTWARE FLOW
The Toggle Bit I/O
Last
Write
WE
CE
OE
I/O
6
6
V
OH
*
V
OL
* Beginning and ending state of I/O6 will vary
HIGH Z
*
X28C010
Ready
FIGURE 4. TOGGLE BIT BUS SEQUENCE
5
FN8105.1
February 12, 2007
Last Write
www.BDTIC.com/Intersil
Load Accum
From Addr N
Compare
Accum with
Addr N
Compare
Ok?
No
X28C010, X28HT010
Software Data Protection
The X28C010/X28HT010 offers a software controlled data
protection feature. The X28C010/X28HT010 is shipped from
Intersil with the software data protection NOT ENABLED:
that is the device will be in the standard operating mode. In
this mode data should be protected during power-up/-down
operations through the use of external circuits. The host
would then have open read and write access of the device
once V
CC
The X28C010/X28HT010 can be automatically protected
during power-up and power-down without the need for
external circuits by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation utilizing the software
algorithm. This circuit is nonvolatile and will remain set for
the life of the device unless the reset command is issued.
was stable.
Yes
Ready
FIGURE 5. TOGGLE BIT SOFTWARE FLOW
The Toggle Bit can eliminate the soft w are housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA
can be especially helpful in an array comprised of multiple
X28C010/X28HT010 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing diagram
in Figure 4 illustrates the sequence of events on the bus.
The software flow diagram in Figure 5 illustrates a method
for polling the Toggle Bit.
Polling. This
Hardware Data Protection
The X28C010/X28HT010 provides three hardware features
that protect nonvolatile data from inadvertent writes.
• Noise Protection—A WE
initiate a write cycle.
pulse less than 10ns will not
Once the software protection is enabled, the
X28C010/X28HT010 is also protected from inadvertent and
accidental writes in the powered-up state. That is, the
software algorithm must be issued prior to writing additional
data to the device.
Software Algorithm
Selecting the software data protection mode requires the
host system to precede data write operations by a series of
three write operations to three specific addresses. Refer to
Figures 6 and 7 for the sequence. The three byte sequence
opens the page write window enabling the host to write from
one to two hundred fifty-six bytes of data. Once the page
load cycle has been completed, the device will automatically
be returned to the data protected state.
• Default V
is ≤ 3.5V.
• Write inhibit—Holding either OE
HIGH will prevent an inadvertent write cycle during powerup and power-down, maintaining data integrity.
Sense—All functions are inhibited when VCC
CC
LOW, WE HIGH, or CE
6
FN8105.1
February 12, 2007
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