®
www.BDTIC.com/Intersil
X28HC64
64K, 8K x 8 Bit
Data Sheet June 7, 2006
5 Volt, Byte Alterable EEPROM
FEATURES
• 70ns access time
• Simple byte and page write
—Single 5V supply
—No external high voltages or V
—Self-timed
—No erase before write
—No complex programming algorithms
—No overerase problem
• Low power CMOS
—40mA active current max.
—200µA standby current max.
• Fast write cycle times
—64-byte page write operation
—Byte or page write cycle: 2ms typical
—Complete memory rewrite: 0.25 sec. typical
—Effective byte write cycle tim e: 32µs typ ic al
• Software data protection
• End of write detection
—DATA polling
—Toggle bit
control circuits
PP
FN8109.1
• High reliability
—Endurance: 1 million cycles
—Data retention: 100 years
• JEDEC approved byte-wide pin out
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X28HC64 is an 8K x 8 EEPROM, fabricated with
Intersil’s proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable nonvolatile memories, the X28HC64 is a 5V only device. It
features the JEDEC approved pinout for byte-wide
memories, compatible with industry standard RAMs.
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle, and
enabling the entire memory to be typically written in 0.25
seconds. The X28HC64 also features DATA
Polling and
Toggle Bit Polling, two methods providing early end of
write detection. In addition, the X28HC64 includes a
user-optional software data protection mode that further
enhances Intersil’s hardware write protect capability .
Intersil EEPROMs are designed and tested for applications requiring extended endurance. Inherent data
retention is greater than 100 years.
PIN CONFIGURATIONS
Plastic DIP
Flat Pack
CERDIP
SOIC
V
1
NC
2
A
12
3
A
7
4
A
6
5
A
5
6
A
4
7
A
A
A
A
I/O
I/O
I/O
V
SS
X28HC64
3
8
2
9
1
10
0
11
0
12
1
13
2
14
28
CC
27
WE
NC
26
A
25
8
A
24
9
A
23
11
22
OE
A
10
CE
I/O
I/O6
I/O
I/O
I/O3
7
5
4
21
20
19
18
17
16
15
7
A
4 3 2 1 32 31 30
5
A
6
A
6
5
7
A
4
A3
8
9
A
2
A
10
1
11
A
0
12
NC
I/O
13
0
14 15 16 17 18 19 20
I/O1
LCC
PLCC
A12NC
NC
X28HC64
(Top View)
2
SS
NC
I/O
V
VCCWE
3
4
I/O
I/O
TSOP
A
1
2
A
2
1
A
NC
29
A8
28
A
9
27
A
11
NC
26
25
OE
A
24
10
23
CE
I/O
22
7
21
I/O
6
5
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
I/O
3
0
4
0
5
1
6
2
NC
7
8
SS
NC
9
10
3
11
4
12
5
13
6
14
7
15
CE
A
16
10
X28HC64
PGA
I/O
I/O
I/O
I/O
12
11
9
7
5
4
I/O
8 A
A
1
A
6 A
3
A
2 A12
5
A
6
2
A0
2
X28HC64
4
(BOTTOM
A
7
15
VSS
14
VIEW)
V
28
NC
1
3
CC
1
13
0
10
3
I/O
5
I/O
CE
OE
A
WE
6
18
I/O
4
7
19
A
10
21
A
11
23
A
9
8
25
NC
26
17
16
20
22
24
27
A3
32
A
31
4
A5
30
A
29
6
A
28
7
A
27
12
NC
26
NC
25
24
23
22
21
20
19
18
17
VCC
NC
WE
NC
A
8
A
9
A
11
OE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Bottom View
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
Ordering Information
www.BDTIC.com/Intersil
X28HC64
PART NUMBER PART MARKING
X28HC64EM-70
X28HC64J-70*
X28HC64JI-70*
X28HC64JIZ-70* (Note)
X28HC64JZ-70* (Note)
X28HC64KM-70
X28HC64P-70
X28HC64PZ-70 (Note)
X28HC64S-70*
X28HC64SI-70*
X28HC64SM-70*
X28HC64SZ-70 (Note)
X28HC64J-90*
X28HC64JI-90*
X28HC64JIZ-90* (Note)
X28HC64KM-90
X28HC64KMB-90
X28HC64P-90
X28HC64PI-90
X28HC64PIZ-90 (Note)
X28HC64PZ-90 (Note)
X28HC64S-90*
X28HC64EM-70 -55 to 125 70 32 Ld LCC (458 mil)
X28HC64J-70 0 to 70 32 Ld PLCC N32.45x55
X28HC64JI-70 -40 to 85 32 Ld PLCC N32.45x55
X28HC64JI-70 Z -40 to 85 32 Ld PLCC (Pb-free) N32.45x55
X28HC64J-70 Z 0 to 70 32 Ld PLCC (Pb-free) N32.45x55
X28HC64KM-70 -55 to 125 28 Ld PGA G28.550x650A
X28HC64P-70 0 to 70 28 Ld PDIP E28.6
X28HC64P-70 Z 0 to 70 28 Ld PDIP** (Pb-free) E28.6
X28HC64S-70 0 to 70 28 Ld SOIC (300 mil) M28.3
X28HC64SI-70 -40 to 85 28 Ld SOIC (300 mil) M28.3
X28HC64SM-70 -55 to 125 28 Ld SOIC (300 mil) M28.3
X28HC64S-70 Z 0 to 70 28 Ld SOIC (300 mil) (Pb-free) M28.3
X28HC64J-90 0 to 70 90 32 Ld PLCC N32.45x55
X28HC64JI-90 -40 to 85 32 Ld PLCC N32.45x55
X28HC64JI-90 Z -40 to 85 32 Ld PLCC (Pb-free) N32.45x55
X28HC64KM-90 -55 to 125 28 Ld PGA G28.550x650A
C X28HC64KMB-90 MIL-STD-883 28 Ld PGA G28.550x650A
X28HC64P-90 0 to 70 28 Ld PDIP E28.6
X28HC64PI-90 -40 to 85 28 Ld PDIP E28.6
X28HC64PI-90 Z -40 to 85 28 Ld PDIP** (Pb-free) E28.6
X28HC64P-90 Z 0 to 70 28 Ld PDIP** (Pb-free) E28.6
X28HC64S-90 0 to 70 28 Ld SOIC (300 mil) M28.3
TEMPERATURE
RANGE (°C)
ACCESS TIME
(ns) PACKAGE PKG. DWG. #
2
FN8109.1
June 7, 2006
Ordering Information (Continued)
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X28HC64
TEMPERATURE
PART NUMBER PART MARKING
X28HC64D-12 X28HC64D-12 0 to 70 120 28 Ld CERDIP
X28HC64DI-12 X28HC64DI-12 -40 to 85 28 Ld CERDIP
X28HC64DM-12 X28HC64DM-12 -55 to 125 28 Ld CERDIP
X28HC64DMB-12 C X28HC64DMB-12 MIL-STD-883 28 Ld CERDIP
X28HC64FM-12 X28HC64FM-12 -55 to 125 28 Ld FLATPACK (440 mil)
X28HC64J-12* X28HC64J-12 0 to 70 32 Ld PLCC N32.45x55
X28HC64JI-12* X28HC64JI-12 -40 to 85 32 Ld PLCC N32.45x55
X28HC64JIZ-12* (Note) X28HC64JI-12 Z -40 to 85 32 Ld PLCC (Pb-free) N32.45x55
X28HC64JZ-12* (Note) X28HC64J-12 Z 0 to 70 32 Ld PLCC (Pb-free) N32.45x55
X28HC64KMB-12 C X28HC64KMB-12 MIL-STD-883 28 Ld PGA G28.550x650A
X28HC64P-12 X28HC64P-12 0 to 70 28 Ld PDIP E28.6
X28HC64PI-12 X28HC64PI-12 -40 to 85 28 Ld PDIP E28.6
X28HC64PIZ-12 (Note) X28HC64PI-12 Z -40 to 85 28 Ld PDIP** (Pb-free) E28.6
X28HC64PZ-12 (Note) X28HC64P-12 Z 0 to 70 28 Ld PDIP** (Pb-free) E28.6
X28HC64S-12* X28HC64S-12 0 to 70 28 Ld SOIC (300 mil) M28.3
X28HC64SI-12* X28HC64SI-12 -40 to 85 28 Ld SOIC (300 mil) M28.3
X28HC64SIZ-12* (Note) X28HC64SI-12 Z -40 to 85 28 Ld SOIC (300 mil) (Pb-free) M28.3
X28HC64SZ-12 (Note) X28HC64S-12 Z 0 to 70 28 Ld SOIC (300 mil) (Pb-free) M28.3
X28HC64DM-15 X28HC64DM-15 -55 to 125 150 28 Ld CERDIP
X28HC64J-15T1 X28HC64J-15 0 to 70 32 Ld PLCC Tape and Reel N32.45x55
X28HC64JI-15 X28HC64JI-15 -40 to 85 32 Ld PLCC N32.45x55
X28HC64JM-15 X28HC64JM-15 -55 to 125 32 Ld PLCC N32.45x55
X28HC64JZ-15* (Note) X28HC64J-15 Z 0 to 70 32 Ld PLCC (Pb-free) N32.45x55
X28HC64KMB-15 C X28HC64KMB-15 MIL-STD-883 28 Ld PGA G28.550x650A
X28HC64P-15 X28HC64P-15 0 to 70 28 Ld PDIP E28.6
X28HC64PIZ-15 (Note) X28HC64PI-15 Z -40 to 85 28 Ld PDIP** (Pb-free) E28.6
X28HC64PZ-15 (Note) X28HC64P-15 Z 0 to 70 28 Ld PDIP** (Pb-free) E28.6
X28HC64S-15 X28HC64S-15 0 to 70 28 Ld SOIC (300 mil) M28.3
X28HC64SI-15 X28HC64SI-15 -40 to 85 28 Ld SOIC (300 mil) M28.3
*Add "T1" suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
RANGE (°C)
ACCESS TIME
(ns) PACKAGE PKG. DWG. #
3
FN8109.1
June 7, 2006
X28HC64
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PIN DESCRIPTIONS
Addresses (A
0-A12
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE
)
The Chip Enable input must be LOW to enable all
read/write operations. When CE
is HIGH, power con-
sumption is reduced.
Output Enable (OE
)
The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (I/O
-I/O7)
0
Data is written to or read from the X28HC64 through
the I/O pins.
Write Enable (WE
)
The Write Enable input controls the writing of data to
the X28HC64.
PIN NAMES
Symbol Description
A0-A
I/O
Address Inputs
Data Input/Output
0
12
-I/O
7
WE Write Enable
CE Chip Enable
OE Output Enable
V
CC
V
SS
+5V
Ground
NC No Connect
BLOCK DIAGRAM
A0–A
12
Address
Inputs
V
V
CE
OE
WE
CC
SS
X Buffers
Latches and
Decoder
Y Buffers
Latches
and
Decoder
Control
Logic and
Timing
65,536-Bit
EEPROM
Array
I/O Buffers
and Latches
I/O0–I/O
Data Inputs/Outputs
7
4
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X28HC64
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DEVICE OPERATION
Read
Read operations are initiated by both OE
and CE
LOW. The read operatio n is terminated by either CE or
returning HIGH. This two line control architecture
OE
eliminates bus contention in a system environment.
The data bus will be in a high impedance state when
either OE
or CE is HIGH.
Write
Write operations are initiated when both CE
and WE
are LOW and OE is HIGH. The X28HC64 supports
both a CE
address is latched by the falling edge of either CE
WE
latched internally by the rising edge of either CE
WE
and WE controlled write cycle. That is, the
or
, whichever occurs last. Similarly, the data is
or
, whichever occurs first. A byte write operation,
once initiated, will automatically continue to completion, typically within 2ms.
Page Write Operation
The page write feature of the X28HC64 allows the
entire memory to be written in 0.25 seconds. Page write
allows two to sixty-four bytes of data to be consecutively
written to the X28HC64 prior to the commencement of
the internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A
through A12) for each subsequent
6
valid write cycle to the part during this operation must
be the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the
host can write an additional one to sixty-three bytes in
the same manner. Each successive byte load cycle,
started by the WE
within 100µs of the falling edge of the preceding WE
a subsequent WE
HIGH to LOW transition, must begin
. If
HIGH to LOW transition is not
detected within 100µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is
infinitely wide, so long as the host continues to acces s
the device within the byte load cycle time of 100µs.
Write Operation Status Bits
The X28HC64 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
5TBDP 43210I/O
Reserved
Toggle Bit
DATA
Polling
Polling (I/O7)
DATA
The X28HC64 features DATA
Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA
Polling allows a simple bit test operation to determine the status of the
X28HC64, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will produce the complement of that data on I/O
(i.e. write
7
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O
Toggle Bit (I/O
)
6
will reflect true data.
7
The X28HC64 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O
will toggle
6
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
5
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X28HC64
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DATA POLLING I/O
7
Figure 2. DATA Polling Bus Sequence
Last
Write
WE
CE
OE
V
I/O
7
A0–A
12
Figure 3. DATA
IH
An An An An An An
Polling Software Flow DATA Polling can effectively reduce the time for writing
Write Data
HIGH Z
V
OH
V
OL
An
X28HC64
Ready
to the X28HC64. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method
of implementing the routine.
Writes
Complete?
Yes
Save Last Data
and Address
Read Last
Address
IO
7
Compare?
Yes
Ready
No
No
6
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X28HC64
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THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
Last
WE
Write
CE
OE
I/O
6
* Beginning and ending state of I/O6 will vary.
*
Figure 5. Toggle Bit Software Flow
Last Write
Yes
Load Accum
From Addr N
V
OH
V
OL
HIGH Z
*
X28HC64
Ready
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA Polling. This can be especially helpful in an array
comprised of multiple X28HC64 memories that is frequently updated. Toggle Bit Polling can also pr ovide a
method for status checking in multiprocessor applications. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the
Toggle Bit.
Compare
Accum with
Addr N
Compare
Ok?
Yes
Ready
No
7
FN8109.1
June 7, 2006
X28HC64
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HARDWARE DATA PROTECTION
The X28HC64 provides two hardware features that
protect nonvolatile data from inadvertent writes.
– Default V
when V
– Write Inhibit—Ho lding either OE
HIGH will prevent an inadvertent write cycle dur-
CE
ing power-up and power-down, maintaining data
integrity.
SOFTWARE DATA PROTECTION
The X28HC64 offers a software controlled data protection feature. The X28HC64 is shipped from Intersil with
the software data protection NOT ENABLED; that is,
the device will be in the standard operating mode. In
this mode data should be protected during power-up/down operations through the use of external circuits.
The host would then have open read and write access
of the device once V
Sense—All write functions are inhibited
CC
is 3V typically.
CC
LOW, WE HIGH, or
was stable.
CC
The X28HC64 can be automatica lly protected during
power-up and power-down without the need for external circuits by employing the software da ta protection
feature. The internal software data protection circuit is
enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will
remain set for the life of the device, unless the reset
command is issued.
Once the software protection is enabled, the X28 HC64
is also protected from inadvertent and accidental
writes in the powered-up state. That is, the software
algorithm must be issued prior to writing additional
data to the device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific
addresses. Refer to Figure 6 and 7 for the sequence.
The three-byte sequence opens the page write window ,
enabling the host to write from one to sixty-four bytes
of data. Once the page load cycle has been completed, the device will automatically be returned to the
data protected state.
8
FN8109.1
June 7, 2006
SOFTWARE DATA PROTECTION
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Figure 6. Timing Sequence—Byte or Page Write
V
CC
0V
X28HC64
(VCC)
Data
ADDR
CE
WE
AAA
1555
55
0AAA
Figure 7. Write Sequence for Software
Data Protection
Write Data AA
to Address
1555
Write Data 55
to Address
0AAA
Write Data A0
to Address
1555
Byte/Page
Load Enabled
Write Data XX
to Any
Address
Optional
Byte/Page
Write Last
Byte to
Last Address
Load Operation
A0
1555
≤t
BLC MAX
Writes
OK
Byte
or
Page
t
WC
Write
Protected
Regardless of whether the device has previo u sly be e n
protected or not, once the software data protection
algorithm is used, the X28HC64 will automatically disable further writes unless another command is issued
to deactivate it. If no further commands are issued the
X28HC64 will be write protected during power-down
and after any subsequent power-up.
Note: Once initiated, the sequence of write operations
should not be interrupted.
After t
Re-Enters Data
Protected State
WC
9
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June 7, 2006
X28HC64
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RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
V
CC
CE
WE
Data
ADDR
AAA
1555
55
0AAA
80
1555
AA
1555
Figure 9. Software Sequence to Deactivate Software
Data Protection
Write Data AA
to Address
1555
Write Data 55
to Address
0AAA
Write Data 80
to Address
1555
55
0AAA
20
1555
≥t
WC
Standard
Operating
Mode
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After t
WC
the X28HC64 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
,
Write Data AA
Address
1555
Write Data 55
to Address
0AAA
Write Data 20
to Address
1555
10
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June 7, 2006
X28HC64
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SYSTEM CONSIDERATIONS
Because the X28HC64 is frequently used in large
memory arrays, it is provided with a two-line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipation, and eliminate the possibility of contention where
multiple I/O pins share the same bus.
To gain the most benefit, it is recommended that CE
be decoded from the address bus, and be used as the
primary device selection input. Both OE
and WE would
then be common among all devices in the array. For a
read operation, this assures that all deselected
devices are in their standby mod e, and that only the
selected device(s) is/are outputting dat a on the bus.
Normalized I
(RD) by Temperature
CC
Over Frequency
1.4
5.5 V
CC
- 55°C
+ 25°C
+ 125°C
RD
CC
I
1.2
1.0
0.8
0.6
Normalized (mA)
0.4
Because the X28HC64 has two power modes,
standby and active, proper decoupling of the memory
array is of prime concern. Enabling CE
will cause transient current spikes. The magnitude of these spikes is
dependent on the output capacitive loading of the I/Os.
Therefore, the larger the array sharing a common bus,
the larger the transient spikes. The voltage peaks
associated with the current transients can be suppressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recommended that a 0.1µF high frequency ceramic capacitor
be used between V
and VSS at each device.
CC
Depending on the size of the array, the value of the
capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between V
and VSS for
CC
each eight devices employed in the array. This bulk
capacitor is employed to overcome the voltage droop
caused by the inductive effects of the PC board traces.
Normalized ICC(RD) @ 25% Over
the V
Range and Frequency
CC
1.4
1.2
1.0
0.8
RD
CC
I
0.6
Normalized (mA)
0.4
5.5 V
5.0 V
4.5 V
CC
CC
CC
0.2
01020
Frequency (MHz)
11
0.2
01020
Frequency (MHz)
FN8109.1
June 7, 2006
X28HC64
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ABSOLUTE MAXIMUM RATINGS
Temperature under bias
X28HC64 ......................................... -10°C to +85°C
X28HC64I, X28HC64M.................. -65°C to +135°C
Storage temperature..........................-65°C to +150°C
Volt age on any pin with
respect to V
......................................... -1V to +7V
SS
D.C. output current...............................................5mA
COMMENT
Stresses above those listed und er “Absolute Maximu m
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those indicated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Lead temperature
(soldering, 10 seconds).................................. 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Supply Voltage Limits
X28HC64 5V ±10%
Industrial -40°C +85°C
Military -55°C +125°C
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol Parameter
I
CC
VCC current (active)
(TTL inputs)
I
SB1
VCC current (standby)
(TTL inputs)
I
SB2
VCC current (standby)
(CMOS inputs)
I
LI
I
LO
V
lL
V
IH
V
OL
V
OH
Input leakage current ±10 µA VIN = VSS to V
Output leakage current ±10 µA V
(2)
Input LOW voltage -1 0.8 V
(2)
Input HIGH voltage 2 VCC + 1 V
Output LOW voltage 0.4 V IOL = 5mA
Output HIGH voltage 2.4 V IOH = -5mA
(1)
Max.
Unit Test ConditionsMin. Typ.
15 40 mA CE = OE = VIL, WE = VIH, All I/O’s = open,
address inputs = TTL levels @ f = 10 MHz
12mACE = VIH, OE = VIL All I/O’s = open,
other inputs = V
IH
100 200 µA CE = VCC - 0.3V, OE = GND, All I/O’s = open,
CC
CC
- 0.3V
IH
other inputs = V
= VSS to VCC, CE = V
OUT
Notes: (1) Typical values are for TA = 25°C and nominal supply voltage
(2) V
min. and VIH max. are for reference only and are not tested.
IL
12
FN8109.1
June 7, 2006
ENDURANCE AND DATA RETENTION
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Parameter Min. Max. Unit
Minimum endurance 100,000 Cycles
Data retention 100 Years
POWER-UP TIMING
X28HC64
Symbol Parameter Typ.
(3)
t
PUR
(3)
t
PUW
CAPACITANCE T
= +25°C, f = 1MHz, VCC = 5V
A
Power-up to read operation 100 µs
Power-up to write operation 5 ms
(1)
Symbol Parameter Max. Unit Test Conditions
(3)
C
I/O
(3)
C
IN
Input/output capacitance 10 pF V
Input capacitance 6 pF VIN = 0V
I/O
= 0V
A.C. CONDITIONS OF TEST MODE SELECTION
Input pulse levels 0V to 3V
Input rise and fall times 5ns
Input and output timing levels 1.5V
CE OE WE Mode I/O Power
L L H Read D
LHL Write D
H X X Standby and
OUT
IN
High Z Standby
write inhibit
X L X Write inhibit — —
X X H Write inhibit — —
Note: (3) This parameter is periodically sampled and not 100% tested.
Unit
Active
Active
EQUIVALENT A.C. LOAD CIRCUITS SYMBOL TABLE
Output
1.37kΩ
5V
1.92kΩ
30pF
WAVEFORM INPUTS OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A Center Line
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
is High
Impedance
13
FN8109.1
June 7, 2006
X28HC64
www.BDTIC.com/Intersil
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Read Cycle Limits
X28HC64-70 X28HC64-90 X28HC64-12
-55°C to +125°C -55°C to +125°C -55°C to +125°C
Symbol Parameter
t
t
OLZ
t
t
OHZ
t
t
t
t
LZ
HZ
t
RC
CE
AA
OE
OH
Read cycle time 70 90 120 ns
Chip enable access time 70 90 120 ns
Address access time 70 90 120 ns
Output enable access time 35 40 50 ns
(4)
CE LOW to active output 0 0 0 ns
(4)
OE LOW to active output 0 0 0 ns
(4)
CE HIGH to high Z output 30 30 30 ns
(4)
OE HIGH to high Z output 30 30 30 ns
Output hold from address change 0 0 0 ns
Read Cycle
t
RC
Min. Max. Min. Max. Min. Max.
Unit
Address
CE
OE
V
IH
WE
when CE
HIGH Z
or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
Data I/O
Note: (4) tLZ min., tHZ, t
min., and t
OLZ
t
CE
t
OE
t
OLZ
t
LZ
Data Valid
are periodically sampled and not 100% tested. tHZ max. and t
OHZ
t
OH
t
AA
t
OHZ
t
HZ
Data Valid
max. are measured from the point
OHZ
14
FN8109.1
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X28HC64
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WRITE CYCLE LIMITS
Symbol Parameter Min. Typ.
(5)
t
WC
t
t
t
t
WPH
t
DV
t
DW
t
t
AS
t
AH
t
CS
t
CH
CW
OES
OEH
t
WP
t
DS
t
DH
BLC
(6)
(6)
(6)
Write cycle time 2 5 ms
Address setup time 0 ns
Address hold time 50 ns
Write setup time 0 ns
Write hold time 0 ns
CE pulse width 50 ns
OE High setup time 0 ns
OE High hold time 0 ns
WE pulse width 50 ns
WE HIGH recovery 50 ns
Data valid 1µs
Data setup 50 ns
Data hold 0 ns
Delay to next write 10 µs
Byte load cycle 0.15 100 µs
(1)
Max. Unit
Controlled Write Cycle
WE
t
WC
Address
t
AS
t
CS
CE
OE
t
OES
WE
t
DV
Data In
Data Out
Notes: (5) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time
the device requires to automatically complete the internal write operation.
(6) t
and tDW are periodically sampled and not 100% tested.
WPH
t
AH
t
CH
t
Data Valid
t
DS
OEH
HIGH Z
t
DH
t
WP
15
FN8109.1
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CE CONTROLLED WRITE CYCLE
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Address
t
AS
CE
t
OES
OE
t
CS
WE
X28HC64
t
WC
t
AH
t
CW
t
OEH
t
CH
t
DV
Data In
Data Out
Page Write Cycle
(7)
OE
CE
WE
Address*
(8)
I/O
Data Valid
t
DS
HIGH Z
t
WP
t
WPH
Byte 0 Byte 1 Byte 2 Byte n Byte n+1 Byte n+2
*For each successive write within the page write operation, A
writes to an unknown address could occur.
t
BLC
t
DH
should be the same or
6–A12
Last Byte
t
WC
Notes: (7) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH
to fetch data from another memory device within the system for the next write; or with WE
polling operation.
(8) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to
either the CE
or WE controlled write cycle timing.
16
HIGH and CE LOW effectively performing a
FN8109.1
June 7, 2006
X28HC64
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DATA Polling Timing Diagram
Address A
CE
WE
OE
I/O
7
Toggle Bit Timing Diagram
CE
n
DIN = X
(9)
(9)
t
OEH
A
n
D
= X
OUT
t
WC
A
n
t
OES
t
DW
D
= X
OUT
WE
t
OEH
OE
I/O*
6
Note: (9) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
HIGH Z
*
t
WC
beginning and ending state will vary, depending upon actual tWC.
* I/O
6
t
OES
t
DW
*
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
FN8109.1
June 7, 2006
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