intersil X28HC64 DATA SHEET
®
www.BDTIC.com/Intersil
X28HC64
64K, 8K x 8 Bit
Data Sheet June 7, 2006
5 Volt, Byte Alterable EEPROM
FEATURES
• 70ns access time
• Simple byte and page write
—Single 5V supply
—No external high voltages or V
—Self-timed
—No erase before write
—No complex programming algorithms
—No overerase problem
• Low power CMOS
—40mA active current max.
—200µA standby current max.
• Fast write cycle times
—64-byte page write operation
—Byte or page write cycle: 2ms typical
—Complete memory rewrite: 0.25 sec. typical
—Effective byte write cycle tim e: 32µs typ ic al
• Software data protection
• End of write detection
—DATA polling
—Toggle bit
control circuits
PP
FN8109.1
• High reliability
—Endurance: 1 million cycles
—Data retention: 100 years
• JEDEC approved byte-wide pin out
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X28HC64 is an 8K x 8 EEPROM, fabricated with
Intersil’s proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable nonvolatile memories, the X28HC64 is a 5V only device. It
features the JEDEC approved pinout for byte-wide
memories, compatible with industry standard RAMs.
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle, and
enabling the entire memory to be typically written in 0.25
seconds. The X28HC64 also features DATA
Polling and
Toggle Bit Polling, two methods providing early end of
write detection. In addition, the X28HC64 includes a
user-optional software data protection mode that further
enhances Intersil’s hardware write protect capability .
Intersil EEPROMs are designed and tested for applications requiring extended endurance. Inherent data
retention is greater than 100 years.
PIN CONFIGURATIONS
Plastic DIP
Flat Pack
CERDIP
SOIC
V
1
NC
2
A
12
3
A
7
4
A
6
5
A
5
6
A
4
7
A
A
A
A
I/O
I/O
I/O
V
SS
X28HC64
3
8
2
9
1
10
0
11
0
12
1
13
2
14
28
CC
27
WE
NC
26
A
25
8
A
24
9
A
23
11
22
OE
A
10
CE
I/O
I/O6
I/O
I/O
I/O3
7
5
4
21
20
19
18
17
16
15
7
A
4 3 2 1 32 31 30
5
A
6
A
6
5
7
A
4
A3
8
9
A
2
A
10
1
11
A
0
12
NC
I/O
13
0
14 15 16 17 18 19 20
I/O1
LCC
PLCC
A12NC
NC
X28HC64
(Top View)
2
SS
NC
I/O
V
VCCWE
3
4
I/O
I/O
TSOP
A
1
2
A
2
1
A
NC
29
A8
28
A
9
27
A
11
NC
26
25
OE
A
24
10
23
CE
I/O
22
7
21
I/O
6
5
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
I/O
3
0
4
0
5
1
6
2
NC
7
8
SS
NC
9
10
3
11
4
12
5
13
6
14
7
15
CE
A
16
10
X28HC64
PGA
I/O
I/O
I/O
I/O
12
11
9
7
5
4
I/O
8 A
A
1
A
6 A
3
A
2 A12
5
A
6
2
A0
2
X28HC64
4
(BOTTOM
A
7
15
VSS
14
VIEW)
V
28
NC
1
3
CC
1
13
0
10
3
I/O
5
I/O
CE
OE
A
WE
6
18
I/O
4
7
19
A
10
21
A
11
23
A
9
8
25
NC
26
17
16
20
22
24
27
A3
32
A
31
4
A5
30
A
29
6
A
28
7
A
27
12
NC
26
NC
25
24
23
22
21
20
19
18
17
VCC
NC
WE
NC
A
8
A
9
A
11
OE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Bottom View
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
Ordering Information
www.BDTIC.com/Intersil
X28HC64
PART NUMBER PART MARKING
X28HC64EM-70
X28HC64J-70*
X28HC64JI-70*
X28HC64JIZ-70* (Note)
X28HC64JZ-70* (Note)
X28HC64KM-70
X28HC64P-70
X28HC64PZ-70 (Note)
X28HC64S-70*
X28HC64SI-70*
X28HC64SM-70*
X28HC64SZ-70 (Note)
X28HC64J-90*
X28HC64JI-90*
X28HC64JIZ-90* (Note)
X28HC64KM-90
X28HC64KMB-90
X28HC64P-90
X28HC64PI-90
X28HC64PIZ-90 (Note)
X28HC64PZ-90 (Note)
X28HC64S-90*
X28HC64EM-70 -55 to 125 70 32 Ld LCC (458 mil)
X28HC64J-70 0 to 70 32 Ld PLCC N32.45x55
X28HC64JI-70 -40 to 85 32 Ld PLCC N32.45x55
X28HC64JI-70 Z -40 to 85 32 Ld PLCC (Pb-free) N32.45x55
X28HC64J-70 Z 0 to 70 32 Ld PLCC (Pb-free) N32.45x55
X28HC64KM-70 -55 to 125 28 Ld PGA G28.550x650A
X28HC64P-70 0 to 70 28 Ld PDIP E28.6
X28HC64P-70 Z 0 to 70 28 Ld PDIP** (Pb-free) E28.6
X28HC64S-70 0 to 70 28 Ld SOIC (300 mil) M28.3
X28HC64SI-70 -40 to 85 28 Ld SOIC (300 mil) M28.3
X28HC64SM-70 -55 to 125 28 Ld SOIC (300 mil) M28.3
X28HC64S-70 Z 0 to 70 28 Ld SOIC (300 mil) (Pb-free) M28.3
X28HC64J-90 0 to 70 90 32 Ld PLCC N32.45x55
X28HC64JI-90 -40 to 85 32 Ld PLCC N32.45x55
X28HC64JI-90 Z -40 to 85 32 Ld PLCC (Pb-free) N32.45x55
X28HC64KM-90 -55 to 125 28 Ld PGA G28.550x650A
C X28HC64KMB-90 MIL-STD-883 28 Ld PGA G28.550x650A
X28HC64P-90 0 to 70 28 Ld PDIP E28.6
X28HC64PI-90 -40 to 85 28 Ld PDIP E28.6
X28HC64PI-90 Z -40 to 85 28 Ld PDIP** (Pb-free) E28.6
X28HC64P-90 Z 0 to 70 28 Ld PDIP** (Pb-free) E28.6
X28HC64S-90 0 to 70 28 Ld SOIC (300 mil) M28.3
TEMPERATURE
RANGE (°C)
ACCESS TIME
(ns) PACKAGE PKG. DWG. #
2
FN8109.1
June 7, 2006
Ordering Information (Continued)
www.BDTIC.com/Intersil
X28HC64
TEMPERATURE
PART NUMBER PART MARKING
X28HC64D-12 X28HC64D-12 0 to 70 120 28 Ld CERDIP
X28HC64DI-12 X28HC64DI-12 -40 to 85 28 Ld CERDIP
X28HC64DM-12 X28HC64DM-12 -55 to 125 28 Ld CERDIP
X28HC64DMB-12 C X28HC64DMB-12 MIL-STD-883 28 Ld CERDIP
X28HC64FM-12 X28HC64FM-12 -55 to 125 28 Ld FLATPACK (440 mil)
X28HC64J-12* X28HC64J-12 0 to 70 32 Ld PLCC N32.45x55
X28HC64JI-12* X28HC64JI-12 -40 to 85 32 Ld PLCC N32.45x55
X28HC64JIZ-12* (Note) X28HC64JI-12 Z -40 to 85 32 Ld PLCC (Pb-free) N32.45x55
X28HC64JZ-12* (Note) X28HC64J-12 Z 0 to 70 32 Ld PLCC (Pb-free) N32.45x55
X28HC64KMB-12 C X28HC64KMB-12 MIL-STD-883 28 Ld PGA G28.550x650A
X28HC64P-12 X28HC64P-12 0 to 70 28 Ld PDIP E28.6
X28HC64PI-12 X28HC64PI-12 -40 to 85 28 Ld PDIP E28.6
X28HC64PIZ-12 (Note) X28HC64PI-12 Z -40 to 85 28 Ld PDIP** (Pb-free) E28.6
X28HC64PZ-12 (Note) X28HC64P-12 Z 0 to 70 28 Ld PDIP** (Pb-free) E28.6
X28HC64S-12* X28HC64S-12 0 to 70 28 Ld SOIC (300 mil) M28.3
X28HC64SI-12* X28HC64SI-12 -40 to 85 28 Ld SOIC (300 mil) M28.3
X28HC64SIZ-12* (Note) X28HC64SI-12 Z -40 to 85 28 Ld SOIC (300 mil) (Pb-free) M28.3
X28HC64SZ-12 (Note) X28HC64S-12 Z 0 to 70 28 Ld SOIC (300 mil) (Pb-free) M28.3
X28HC64DM-15 X28HC64DM-15 -55 to 125 150 28 Ld CERDIP
X28HC64J-15T1 X28HC64J-15 0 to 70 32 Ld PLCC Tape and Reel N32.45x55
X28HC64JI-15 X28HC64JI-15 -40 to 85 32 Ld PLCC N32.45x55
X28HC64JM-15 X28HC64JM-15 -55 to 125 32 Ld PLCC N32.45x55
X28HC64JZ-15* (Note) X28HC64J-15 Z 0 to 70 32 Ld PLCC (Pb-free) N32.45x55
X28HC64KMB-15 C X28HC64KMB-15 MIL-STD-883 28 Ld PGA G28.550x650A
X28HC64P-15 X28HC64P-15 0 to 70 28 Ld PDIP E28.6
X28HC64PIZ-15 (Note) X28HC64PI-15 Z -40 to 85 28 Ld PDIP** (Pb-free) E28.6
X28HC64PZ-15 (Note) X28HC64P-15 Z 0 to 70 28 Ld PDIP** (Pb-free) E28.6
X28HC64S-15 X28HC64S-15 0 to 70 28 Ld SOIC (300 mil) M28.3
X28HC64SI-15 X28HC64SI-15 -40 to 85 28 Ld SOIC (300 mil) M28.3
*Add "T1" suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
RANGE (°C)
ACCESS TIME
(ns) PACKAGE PKG. DWG. #
3
FN8109.1
June 7, 2006
X28HC64
www.BDTIC.com/Intersil
PIN DESCRIPTIONS
Addresses (A
0-A12
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE
)
The Chip Enable input must be LOW to enable all
read/write operations. When CE
is HIGH, power con-
sumption is reduced.
Output Enable (OE
)
The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (I/O
-I/O7)
0
Data is written to or read from the X28HC64 through
the I/O pins.
Write Enable (WE
)
The Write Enable input controls the writing of data to
the X28HC64.
PIN NAMES
Symbol Description
A0-A
I/O
Address Inputs
Data Input/Output
0
12
-I/O
7
WE Write Enable
CE Chip Enable
OE Output Enable
V
CC
V
SS
+5V
Ground
NC No Connect
BLOCK DIAGRAM
A0–A
12
Address
Inputs
V
V
CE
OE
WE
CC
SS
X Buffers
Latches and
Decoder
Y Buffers
Latches
and
Decoder
Control
Logic and
Timing
65,536-Bit
EEPROM
Array
I/O Buffers
and Latches
I/O0–I/O
Data Inputs/Outputs
7
4
FN8109.1
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X28HC64
www.BDTIC.com/Intersil
DEVICE OPERATION
Read
Read operations are initiated by both OE
and CE
LOW. The read operatio n is terminated by either CE or
returning HIGH. This two line control architecture
OE
eliminates bus contention in a system environment.
The data bus will be in a high impedance state when
either OE
or CE is HIGH.
Write
Write operations are initiated when both CE
and WE
are LOW and OE is HIGH. The X28HC64 supports
both a CE
address is latched by the falling edge of either CE
WE
latched internally by the rising edge of either CE
WE
and WE controlled write cycle. That is, the
or
, whichever occurs last. Similarly, the data is
or
, whichever occurs first. A byte write operation,
once initiated, will automatically continue to completion, typically within 2ms.
Page Write Operation
The page write feature of the X28HC64 allows the
entire memory to be written in 0.25 seconds. Page write
allows two to sixty-four bytes of data to be consecutively
written to the X28HC64 prior to the commencement of
the internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A
through A12) for each subsequent
6
valid write cycle to the part during this operation must
be the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the
host can write an additional one to sixty-three bytes in
the same manner. Each successive byte load cycle,
started by the WE
within 100µs of the falling edge of the preceding WE
a subsequent WE
HIGH to LOW transition, must begin
. If
HIGH to LOW transition is not
detected within 100µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is
infinitely wide, so long as the host continues to acces s
the device within the byte load cycle time of 100µs.
Write Operation Status Bits
The X28HC64 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
5TBDP 43210I/O
Reserved
Toggle Bit
DATA
Polling
Polling (I/O7)
DATA
The X28HC64 features DATA
Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA
Polling allows a simple bit test operation to determine the status of the
X28HC64, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will produce the complement of that data on I/O
(i.e. write
7
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O
Toggle Bit (I/O
)
6
will reflect true data.
7
The X28HC64 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O
will toggle
6
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
5
FN8109.1
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X28HC64
www.BDTIC.com/Intersil
DATA POLLING I/O
7
Figure 2. DATA Polling Bus Sequence
Last
Write
WE
CE
OE
V
I/O
7
A0–A
12
Figure 3. DATA
IH
An An An An An An
Polling Software Flow DATA Polling can effectively reduce the time for writing
Write Data
HIGH Z
V
OH
V
OL
An
X28HC64
Ready
to the X28HC64. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method
of implementing the routine.
Writes
Complete?
Yes
Save Last Data
and Address
Read Last
Address
IO
7
Compare?
Yes
Ready
No
No
6
FN8109.1
June 7, 2006
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