intersil X28HC256 DATA SHEET

®

www.BDTIC.com/Intersil

X28HC256

256k, 32k x 8-Bit

Data Sheet May 7, 2007

5V, Byte Alterable EEPROM

The X28HC256 is a second generation high performance
CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s
proprietary, textured poly floating gate technology, providing
a highly reliable 5V only nonvolatile memory.

The X28HC256 supports a 128-byte page write operation,
effectively providing a 24µs/byte write cycle, and enabling
the entire memory to be typically rewritten in less than 0.8
seconds. The X28HC256 also features DATA
Toggle Bit Polling, two methods of providing early end of
write detection. The X28HC256 also supports the JEDEC
standard Software Data Protection feature for protecting
against inadvertent writes during power-up and power-down.

Endurance for the X28HC256 is specified as a minimum
1,000,000 write cycles per byte and an inherent data
retention of 100 years.

Polling and

FN8108.2

Features

• Access time: 70ns

• Simple byte and page write

- Single 5V supply

- No external high voltages or V

- Self-timed

- No erase before write

- No complex programming algorithms

- No overerase problem

• Low power CMOS

- Active: 60mA

- Standby: 500µA

• Software data protection

- Protects data against system level inadvertent writes

• High speed page write capability

• Highly reliable Direct Write

™

- Endurance: 1,000,000 cycles

- Data retention: 100 years

P-P

cell

control circuits

Block Diagram

A0 TO A
ADDRESS

INPUTS

• Early end of write detection

- DATA polling

- Toggle bit polling

• Pb-free plus anneal available (RoHS compliant)

256kBIT

X BUFFERS

LATCHES AND

DECODER

14

Y BUFFERS

LATCHES AND

DECODER

CE

OE
WE

CONTROL

LOGIC AND

TIMING

EEPROM

ARRAY

I/O BUFFERS

AND LATCHES

I/O0 TO I/O

DATA INPUTS/OUTPUTS

7

V

CC

V

SS

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

Ordering Information

www.BDTIC.com/Intersil

X28HC256

ACCESS TIME

PART NUMBER PART MARKING

X28HC256DI-15 X28HC256DI-15 RR 150 -40 to +85 28 Ld CERDIP F28.6
X28HC256DM-15 X28HC256DM-15 RR -55 to +125 28 Ld CERDIP F28.6
X28HC256DMB-15 C X28HC256DMB-15 MIL-STD-883 28 Ld CERDIP F28.6
X28HC256EMB-15 C X28HC256EMB-15 MIL-STD-883 32 Ld LCC (458 mils)
X28HC256FMB-15 C X28HC256FMB-15 MIL-STD-883 28 Ld FLATPACK (440 mils)
X28HC256J-15*, ** X28HC256J-15 RR 0 to +70 32 Ld PLCC N32.45x55
X28HC256JZ-15* (Note) X28HC256J-15 ZRR 0 to +70 32 Ld PLCC (Pb-free) N32.45x55
X28HC256JI-15*, ** X28HC256JI-15 RR -40 to +85 32 Ld PLCC N32.45x55
X28HC256JIZ-15* (Note) X28HC256JI-15 ZRR -40 to +85 32 Ld PLCC (Pb-free) N32.45x55
X28HC256JM-15* X28HC256JM-15 RR -55 to +125 32 Ld PLCC N32.45x55
X28HC256KI-15 X28HC256KI-15 RR -40 to +85 28 Ld PGA G28.550x650A
X28HC256KM-15 X28HC256KM-15 RR -55 to +125 28 Ld PGA G28.550x650A
X28HC256KMB-15 C X28HC256KMB-15 MIL-STD-883 28 Ld PGA G28.550x650A
X28HC256P-15 X28HC256P-15 RR 0 to +70 28 Ld PDIP E28.6
X28HC256PZ-15 (Note) X28HC256P-15 RRZ 0 to +70 28 Ld PDIP (Pb-free)*** E28.6
X28HC256PI-15 X28HC256PI-15 RR -40 to +85 28 Ld PDIP E28.6
X28HC256PIZ-15 (Note) X28HC256PI-15 RRZ -40 to +85 28 Ld PDIP (Pb-free)*** E28.6
X28HC256PM-15 X28HC256PM-15 RR -55 to +125 28 Ld PDIP E28.6
X28HC256SI-15* X28HC256SI-15 RR -40 to +85 28 Ld SOIC (300 mil) MDP0027
X28HC256SIZ-15* (Note) X28HC256SI-15 RRZ -40 to +85 28 Ld SOIC (300 mil) (Pb-free) MDP0027
X28HC256SM-15 X28HC256SM-15 RR -55 to +125 28 Ld SOIC (300 mil) MDP0027
X28HC256D-12 X28HC256D-12 RR 120 0 to +70 28 Ld CERDIP (520 mils) F28.6
X28HC256DI-12 X28HC256DI-12 RR -40 to +85 28 Ld CERDIP (520 mils) F28.6
X28HC256DM-12 X28HC256DM-12 RR -55 to +125 28 Ld CERDIP (520 mils) F28.6
X28HC256DMB-12 C X28HC256DMB-12 MIL-STD-883 28 Ld CERDIP (520 mils) F28.6
X28HC256EI-12 X28HC256EI-12 RR -40 to +85 32 Ld LCC (458 mils)
X28HC256EM-12 X28HC256EM-12 RR -55 to +125 32 Ld LCC (458 mils)
X28HC256EMB-12 C X28HC256EMB-12 MIL-STD-883 32 Ld LCC (458 mils)
X28HC256FMB-12 C X28HC256FMB-12 MIL-STD-883 28 Ld FLATPACK (440 mils)
X28HC256J-12* X28HC256J-12 RR 0 to +70 32 Ld PLCC N32.45x55
X28HC256JZ-12* (Note) X28HC256J-12 ZRR 0 to +70 32 Ld PLCC (Pb-free) N32.45x55
X28HC256JI-12* X28HC256JI-12 RR -40 to +85 32 Ld PLCC N32.45x55
X28HC256JIZ-12* (Note) X28HC256JI-12 ZRR -40 to +85 32 Ld PLCC (Pb-free) N32.45x55
X28HC256KI-12 X28HC256KI-12 RR -40 to +85 28 Ld PGA G28.550x650A
X28HC256KM-12 X28HC256KM-12 RR -55 to +125 28 Ld PGA G28.550x650A
X28HC256KMB-12 C X28HC256KMB-12 MIL-STD-883 28 Ld PGA G28.550x650A
X28HC256P-12 X28HC256P-12 RR 0 to +70 28 Ld PDIP E28.6
X28HC256PZ-12 (Note) X28HC256P-12 RRZ 0 to +70 28 Ld PDIP (Pb-free)*** E28.6
X28HC256PI-12 X28HC256PI-12 RR -40 to +85 28 Ld PDIP E28.6

(ns)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

2

FN8108.2

May 7, 2007

Ordering Information (Continued)

www.BDTIC.com/Intersil

X28HC256

ACCESS TIME

PART NUMBER PART MARKING

X28HC256PIZ-12 (Note) X28HC256PI-12 RRZ -40 to +85 28 Ld PDIP (Pb-free)*** E28.6
X28HC256S-12* X28HC256S-12 RR 120 0 to +70 28 Ld SOIC (300 mils) MDP0027
X28HC256SZ-12 (Note) X28HC256S-12 RRZ 0 to +70 28 Ld SOIC (300 mils) (Pb-free) MDP0027
X28HC256SI-12* X28HC256SI-12 RR -40 to +85 28 Ld SOIC (300 mils) MDP0027
X28HC256SIZ-12 (Note) X28HC256SI-12 RRZ -40 to +85 28 Ld SOIC (300 mils) (Pb-free) MDP0027
X28HC256SM-12*, ** X28HC256SM-12 RR -55 to +125 28 Ld SOIC (300 mils) MDP0027
X28HC256D-90 X28HC256D-90 RR 90 0 to +70 28 Ld CERDIP (520 mils) F28.6
X28HC256DI-90 X28HC256DI-90 RR -40 to +85 28 Ld CERDIP (520 mils) F28.6
X28HC256DM-90 X28HC256DM-90 RR -55 to +125 28 Ld CERDIP (520 mils) F28.6
X28HC256DMB-90 C X28HC256DMB-90 MIL-STD-883 28 Ld CERDIP (520 mils) F28.6
X28HC256EM-90 X28HC256EM-90 RR -55 to +125 32 Ld LCC (458 mils)
X28HC256EMB-90 C X28HC256EMB-90 MIL-STD-883 32 Ld LCC (458 mils)
X28HC256FI-90 X28HC256FI-90 RR -40 to +85 28 Ld FLATPACK (440 mils)
X28HC256FM-90 X28HC256FM-90 RR -55 to +125 28 Ld FLATPACK (440 mils)
X28HC256FMB-90 C X28HC256FMB-90 MIL-STD-883 28 Ld FLATPACK (440 mils)
X28HC256J-90* X28HC256J-90 RR 0 to +70 32 Ld PLCC N32.45x55
X28HC256JZ-90* (Note) X28HC256J-90 ZRR 0 to +70 32 Ld PLCC (Pb-free) N32.45x55
X28HC256JI-90* X28HC256JI-90 RR -40 to +85 32 Ld PLCC N32.45x55
X28HC256JIZ-90* (Note) X28HC256JI-90 ZRR -40 to +85 32 Ld PLCC (Pb-free) N32.45x55
X28HC256JM-90* X28HC256JM-90 RR -55 to +125 32 Ld PLCC N32.45x55
X28HC256KM-90 X28HC256KM-90 RR -55 to +125 28 Ld PGA G28.550x650A
X28HC256KMB-90 C X28HC256KMB-90 MIL-STD-883 28 Ld PGA G28.550x650A
X28HC256P-90 X28HC256P-90 RR 90 0 to +70 28 Ld PDIP E28.6
X28HC256PZ-90 (Note) X28HC256P-90 RRZ 0 to +70 28 Ld PDIP (Pb-free)*** E28.6
X28HC256PI-90 X28HC256PI-90 RR -40 to +85 28 Ld PDIP E28.6
X28HC256PIZ-90 (Note) X28HC256PI-90 RRZ -40 to +85 28 Ld PDIP (Pb-free)** E28.6
X28HC256S-90* X28HC256S-90 RR 0 to +70 28 Ld SOIC (300 mils) MDP0027
X28HC256SI-90* X28HC256SI-90 RR -40 to +85 28 Ld SOIC (300 mils) MDP0027
X28HC256SIZ-90 (Note) X28HC256SI-90 RRZ -40 to +85 28 Ld SOIC (300 mils) (Pb-free) MDP0027
X28HC256SI-20T1 200 -40 to +85 28 Ld SOIC (300 mils) Tape and Reel MDP0027

*Add "T1" suffix for tape and reel.
**Add "T2" suffix for tape and reel.
***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

(ns)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

3

FN8108.2

May 7, 2007

Pinouts

www.BDTIC.com/Intersil

A

A

I/O

I/O

I/O

14

12

A

A

A

A

A

A

A

A

SS

7

6

5

4

3

2

1

0

0

1

2

X28HC256

TOP VIEW

1

2

3

4

5

6

7

X28HC256

8

9

10

11

12

13

14

28

V

CC

27

WE
A

26

13

A8

25

A

24

9

A

23

11

22

OE
A

10

CE
I/O

I/O6

I/O

I/O

I/O3

7

5

4

21

20

19

18

17

16

15

(28 LD CERDIP, FLATPACK, PDIP, SOIC)

V

Pin Descriptions

X28HC256

(32 LD PLCC, LCC)

7

A

4 3 2 1 32 31 30

5

A

6

A

6

5

7

A

4

A3

8
9

A

2

A

10

1

11

A

0

12

NC

13

I/O

0

14 15 16 17 18 19 20

I/O1

X28HC256

TOP VIEW

14

V

NC

A12A

X28HC256

2

SS

I/O

I/O

NC

V

CC

3

WE

4

I/O

X28HC256

(28 LD PGA)

BOTTOM VIEW

13

A

A8

29

A

28

9

27

A

11

NC

26

OE

25

A

24

10

23

CE
I/O

22

7

21

I/O

6

5

I/O

12

11

I/O

I/O

A

9

A

7

A

5

A

4

1

0

8 A

1

6 A

3

2 A12

5

6

I/O

2

13

A0

10

2

X28HC256

4

A

7

3

15

14

28

1

I/O

VSS

V

CC

A

14

I/O

I/O

3

5

I/O4

CE

OE

A

9

WE

6

18

I/O

7

19

A

10

21

A

11

23

A

8

25

A

13

26

17

16

20

22

24

27

Addresses (A0 to A14)

The Address inputs select an 8-bit memory location during a
read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/write
operations. When CE

is HIGH, power consumption is

reduced.

Output Enable (OE)

The Output Enable input controls the d ata output buffers,
and is used to initiate read operations.

Data In/Data Out (I/O0 to I/O7)

Data is written to or read from the X28HC256 through the I/O
pins.

Write Enable (WE)

The Write Enable input controls the writing of data to the
X28HC256.

4

FN8108.2

May 7, 2007

X28HC256

www.BDTIC.com/Intersil

Pin Names

SYMBOL DESCRIPTION

to A

A

0

14

I/O0 to I/O

7

WE

CE
OE Output Enable

V

CC

V

SS

NC No Connect

Address Inputs

Data Input/Output

Write Enable

Chip Enable

+5V

Ground

Device Operation

Read

Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in
a high impedance state when either OE

Write

Write operations are initiated when both CE and WE are
LOW and OE
and WE
by the falling edge of either CE

is HIGH. The X28HC256 supports both a CE

controlled write cycle. That is, the address is latched

or WE, whichever occurs
last. Similarly, the data is latched internally by the rising edge
of either CE

or WE, whichever occurs first. A byte write
operation, once initiated, will automatically continue to
completion, typically within 3ms.

Page Write Operation

The page write feature of the X28HC256 allows the entire
memory to be written in typically 0.8 seconds. Page write
allows up to one hundred twenty-eight bytes of data to be
consecutively written to the X28HC256, prior to the
commencement of the internal programming cycle. The host
can fetch data from another device within the system during
a page write operation (change the source address), but the
page address (A
write cycle to the part during this operation must be the same
as the initial page address.

through A14) for each subsequent valid

7

or OE returning

or CE is HIGH.

The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to one hundred twenty-seven bytes in
the same manner as the first byte was written. Each
successive byte load cycle, started by the WE

HIGH to LOW
transition, must begin within 100µs of the falling edge of the
preceding WE

. If a subsequent WE HIGH to LOW transition
is not detected within 100µs, the internal automatic
programming cycle will commence. There is no page write
window limitation. Effectively the page write window is
infinitely wide, so long as the host continues to access the
device within the byte load cycle time of 100µs.

Write Operation Status Bits

The X28HC256 provides the user two write operation status
bits. These can be used to optimize a system write cycle
time. The status bits are mapped onto the I/O bus as shown
in Figure 1.

5TBDP 43210I/O

RESERVED

TOGGLE BIT

DATA

POLLING

FIGURE 1. STATUS BIT ASSIGNMENT

DATA Polling (I/O7)

The X28HC256 features DA T A Polling as a method to indicate
to the host system that the byte write or page write cycle has
completed. DATA

Polling allows a simple bit test operation to
determine the status of the X28HC256. This eliminates
additional interrupt inputs or external hardware. During the
internal programming cycle, any attempt to read the last byte
written will produce the complement of that data on I/O

(i.e.,

7

write data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O

will reflect true data.

7

Toggle Bit (I/O6)

The X28HC256 also provides another method for
determining when the internal write cycle is complete. During
the internal programming cycle I/O
LOW and LOW to HIGH on subsequent attempts to read the
device. When the internal cycle is complete the toggling will
cease, and the device will be accessible for additional read
and write operations.

will toggle from HIGH to

6

5

FN8108.2

May 7, 2007

X28HC256

www.BDTIC.com/Intersil

DATA Polling I/O

WRITE

WE

CE

OE

I/O

7

A0 TO A

14

WRITE DATA

7

LAST

V

IH

An An An An An An

HIGH Z

V

OL

An

FIGURE 2. DATA POLLING BUS SEQUENCE

DATA Polling can effectively halve the time for writing to the
X28HC256. The timing diagram in Figure 2 illustrates the
sequence of events on the bus. The software flow diagram in
Figure 3 illustrates one method of implementing the routine.

V

OH

X28HC256
READY

WRITES

COMPLETE?

YES

SAVE LAST DATA

AND ADDRESS

READ LAST

ADDRESS

IO

7

COMPARE?

YES

X28HC256

READY

NO

NO

FIGURE 3. DATA POLLING SOFTWARE FLOW

6

FN8108.2

May 7, 2007

X28HC256

www.BDTIC.com/Intersil

The Toggle Bit I/O

LAST
WRITE

WE

CE

OE

I/O

6

¬

LAST WRITE

LOAD ACCUM

FROM ADDR n

6

YES

V

*

OH

V

OL

* I/O6 Beginning and ending state of I/O6 will vary.

FIGURE 4. TOGGLE BIT BUS SEQUENCE

HIGH Z

*

X28C512, X28C513

READY

Hardware Data Protection

The X28HC256 provides two hardware features that protect
nonvolatile data from inadvertent writes.

• Default V

is 3.5V typically.

V

CC

• Write Inhibit—Holding either OE

HIGH will prevent an inadvertent write cycle during power­up and power-down, maintaining data integrity.

Sense—All write functions a re inhi bite d when

CC

LOW, WE HIGH, or CE

COMPARE

ACCUM WITH

ADDR n

COMPARE

OK?

YES

X28C256

READY

FIGURE 5. TOGGLE BIT SOFTWARE FLOW

NO

The Toggle Bit can eliminate the chore of saving and fetching
the last address and data in order to implement DATA

Polling.
This can be especially helpful in an array comprised of
multiple X28HC256 memories that is frequently updated.
The timing diagram in Figure 4 illustrates the sequence of
events on the bus. The software flow diagram in Figure 5
illustrates a method for polling the Toggle Bit.

Software Data Protection

The X28HC256 offers a software-controlled data protection
feature. The X28HC256 is shipped from Intersil with the
software data protection NOT ENABLED; that is, the device
will be in the standard operating mode. In this mode data
should be protected during power-up/down operations
through the use of external circuits. The host would then
have open read and write access of the device once V
was stable.

The X28HC256 can be automatically protected during
power-up and power-down (without the need for external
circuits) by employing the software data protection feature.
The internal software data protection circuit is enabled after
the first write operation, utilizing the software algorithm. This
circuit is nonvolatile, and will remain set for the life of the
device unless the reset command is issued.

Once the software protection is enabled, the X28HC256 is
also protected from inadvertent and accidental writes in the
powered-up state. That is, the software algorithm must be
issued prior to writing additional data to the device.

CC

7

FN8108.2

May 7, 2007

X28HC256

www.BDTIC.com/Intersil

Software Algorithm

Selecting the software data protection mode requires the
host system to precede data write operations by a series of
three write operations to three specific addresses. Refer to
Figure 6 and 7 for the sequence. The three-byte sequence

Software Data Protection

V

CC

0V

DATA
ADDRESS

CE

WE

WRITE DATA AA

TO ADDRESS

5555

WRITE DATA 55

TO ADDRESS

2AAA

WRITE DATA A0

TO ADDRESS

5555

WRITE DATA XX

TO ANY

ADDRESS

WRITE LAST

BYTE TO

LAST ADDRESS

AAA

5555

55

2AAA

FIGURE 6. TIMING SEQUENCE—BYTE OR PAGE WRITE

BYTE/PAGE
LOAD ENABLED

OPTIONAL
BYTE/PAGE
LOAD OPERATION

A0

5555

opens the page write window, enabling the host to write from
one to one hundred twenty-eight bytes of data. Once the
page load cycle has been completed, the device will
automatically be returned to the data protected state.

≤t

BLC MAX

WRITES

OK

BYTE

OR

AGE

t

WC

WRITE
PROTECTED

Regardless of whether the device has previously been
protected or not, once the software data protection algorithm
is used and data has been written, the X28HC256 will
automatically disable further writes unless another command
is issued to cancel it. If no further commands are issued the
X28HC256 will be write protected during power-down and
after any subsequent power-up.

Note: Once initiated, the sequence of write operations
should not be interrupted.

(VCC)

AFTER t

RE-ENTERS DATA

PROTECTED STATE

WC

FIGURE 7. WRITE SEQUENCE FOR SOFTWARE DATA

8

FN8108.2

May 7, 2007

Resetting Software Data Protection

www.BDTIC.com/Intersil

V

CC

X28HC256

DATA

ADDRESS

CE

WE

AAA

5555

55

2AAA

FIGURE 8. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE

80

5555

AA

5555

55

2AAA

20

5555

Note: Once initiated, the sequence of write operations

WRITE DATA AA

TO ADDRESS

5555

should not be interrupted.

SYSTEM CONSIDERATIONS

Because the X28HC256 is frequently used in large memory

WRITE DATA 55

TO ADDRESS

2AAA

arrays, it is provided with a two line control architecture for
both read and write operations. Proper usage can provide
the lowest possible power dissipation, and eliminate the
possibility of contention where multiple I/O pins share the
same bus.

WRITE DATA 80

TO ADDRESS

5555

To gain the most benefit, it is recommended that CE
decoded from the address bus and be used as the primary
device selection input. Both OE
common among all devices in the array. For a read

WRITE DATA AA

TO ADDRESS

5555

operation, this assures that all deselected devices are in
their standby mode, and that only the selected device(s)
is/are outputting data on the bus.

t

WC

and WE would then be

STANDARD
OPERATING
MODE

be

WRITE DATA 55

TO ADDRESS

2AAA

WRITE DATA 20

TO ADDRESS

5555

AFTER tWC,

RE-ENTERS

UNPROTECTED

STATE

FIGURE 9. WRITE SEQUENCE FOR RESETTING SOFTWARE

In the event the user wants to deactivate the software data
protection feature for testing or reprogramming in an
EEPROM programmer, the following six step algorithm will
reset the internal protection circuit. After t

, the X28HC256

WC

will be in standard operating mode.

Because the X28HC256 has two power modes, standby and
active, proper decoupling of the memory array is of prime
concern. Enabling CE

will cause transient current spikes.
The magnitude of these spikes is dependent on the output
capacitive loading of the l/Os. Therefore, the larger the array
sharing a common bus, the larger the transient spikes. The
voltage peaks associated with the current transients can be
suppressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recommended that
a 0.1µF high frequency ceramic capacitor be used between
V

and VSS at each device. Depending on the size of the

CC

array, the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic bulk

capacitor be placed between V

and VSS for each eight

CC

devices employed in the array. This bulk capacitor is
employed to overcome the voltage droop caused by the
inductive effects of the PC board traces.

9

FN8108.2

May 7, 2007

X28HC256

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C

X28HC256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

X28HC256I, X28HC256M . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on any Pin with Respect to V

DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

. . . . . . . . . . . . . -1V to +7V

SS

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Commerical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

DC Electrical Specifications Over Recommended Operating Conditions, Unless Otherwise Specified.

PARAMETER SYMBOL TEST CONDITIONS

VCC Active Current
(TTL Inputs)

V

Standby Current

CC

(TTL Inputs)

Standby Current

V

CC

(CMOS Inputs)
Input Leakage Current I
Output Leakage Current I
Input LOW Voltage V
Input HIGH Voltage V
Output LOW Voltage V
Output HIGH Voltage V

NOTES:

1. Typical values are for T
min. and VIH max. are for reference only and are not tested.

2. V

IL

A

I

CC

I

SB1

I

SB2

(Note 2) -1 0.8 V

lL

(Note 2) 2 VCC + 1 V

IH

CE = OE = VIL, WE = VIH, All I/O’s = open,
address inputs = .4V/2.4V levels @ f = 10MHz

CE = VIH, OE = VIL, All I/O’s = open, other inputs = V

CE = VCC - 0.3V , OE = GND, All I/Os = open, other
inputs = V

VIN = VSS to V

LI

V

LO

OL

OH

OUT

IOL = 6mA 0.4 V
IOH = -4mA 2.4 V

- 0.3V

CC

CC

= VSS to VCC, CE = V

= +25°C and nominal supply voltage.

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.

LIMITS

TYP

(Note 7) MAX

30 60 mA

IH

12mA

200 500 µA

10 µA

IH

10 µA

UNITMIN

Power-up Timing

PARAMETER SYMBOL MAX UNIT

Power-up to read t
Power-up to write t

, Note 3 100 µs

PUR

, Note 3 5 ms

PUW

NOTE:

3. This parameter is periodically sampled and not 100% tested.

10

FN8108.2

May 7, 2007

X28HC256

www.BDTIC.com/Intersil

Capacitance T

SYMBOL TEST CONDITIONS MAX UNIT

C

(Note 9) Input/output capacitance V

I/O

(Note 9) Input capacitance VIN = 0V 6 pF

C

IN

= +25°C, f = 1MHz, VCC = 5V.

A

= 0V 10 pF

I/O

Endurance and Data Retention

PARAMETER MIN MAX UNIT

Endurance 1,000,000 Cycles
Data retention 100 Years

AC Conditions of Test

Input pulse levels 0V to 3V
Input rise and fall times 5ns
Input and output timing levels 1.5V

Mode Selection

CE OE WE MODE I/O POWER

L L H Read D
LHL Write DINactive
H X X St andby and write

inhibit
X L X Write inhibit — —
X X H Write inhibit — —

OUT

High Z standby

active

Symbol Table

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from LOW
to HIGH

May change
from HIGH
to LOW

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from LOW
to HIGH

Will change
from HIGH
to LOW

Changing:
State Not
Known

is High
Impedance

Equivalent AC Load Circuit

5V

1.92kΩ

OUTPUT

1.37kΩ

30pF

11

FN8108.2

May 7, 2007

X28HC256

www.BDTIC.com/Intersil

AC Electrical Specifications Over Recommended Operating Conditions, Unless Otherwise Specified.

X28HC256-70 X28HC256-90 X28HC256-12 X28HC256-15

PARAMETER SYMBOL

Read Cycle Time t
Chip Enable Access Time t
Address Access Time t
Output Enable Access Time t

LOW to Active Output tLZ (Note 4) 0 0 0 0 ns

CE
OE LOW to Active Output t

HIGH to High Z Output tHZ (Note 4) 35 40 50 50 ns

CE

HIGH to High Z Output t

OE
Output Hold from Address Change t

Read Cycle

ADDRESS

(Note 5) 70 90 120 150 ns

RC

(Note 5) 70 90 120 150 ns

CE

(Note 5) 70 90 120 150 ns

AA

OE

(Note 4) 0 0 0 0 ns

OLZ

(Note 4) 35 40 50 50 ns

OHZ

OH

t

RC

000 0ns

35 40 50 50 ns

UNITMIN MAX MIN MAX MIN MAX MIN MAX

t

CE

CE

t

OE

OE

V

IH

WE

DATA I/O

HIGH Z

t

OLZ

t

LZ

DATA VALID

NOTES:

min., tHZ, t

4. t

LZ

, OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.

CE

min. and t

OLZ

are periodically sampled and not 100% tested, tHZ and t

OHZ

5. For faster 256k products, refer to X28VC256 product line.

t

OH

DATA VALID

t

AA

are measured with CL = 5pF, from the point when

OHZ

t

HZ

t

OHZ

12

FN8108.2

May 7, 2007

X28HC256

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Write Cycle Limits

TYP

PARAMETER SYMBOL MIN

Write Cycle Time tWC (Note 7) 3 5 ms
Address Setup Time t
Address Hold Time t
Write Setup Time t
Write Hold Time t

Pulse Width t

CE
OE HIGH Setup Time t

HIGH Hold Time t

OE

Pulse Width t

WE
WE HIGH Recovery (page write only) t

WPH

Data Valid t
Data Setup t
Data Hold t
Delay to Next Write After Polling is True t

DW

Byte Load Cycle t

AS

AH

CS

CH

CW

OES

OEH

WP

(Note 8) 50 ns

DV

DS

DH

(Note 8) 10 µs

BLC

0ns

50 ns

0ns
0ns

50 ns

0ns
0ns

50 ns

50 ns

0ns

0.15 100 µs

NOTES:

6. Typical values are for T
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device

7. t

WC

= +25°C and nominal supply voltage.

A

requires to automatically complete the internal write operation.

and tDW are periodically sampled and not 100% tested.

8. t

WPH

(Note 6) MAX UNIT

1µs

WE Controlled Write Cycl e

ADDRESS

CE

OE

WE

DATA IN

DATA OUT

t

WC

t

AS

t

CS

t

OES

t

AH

t

CH

t

DATA VALID

t

DS

OEH

HIGH Z

t

DH

t

WP

13

FN8108.2

May 7, 2007

CE Controlled Write Cycle

www.BDTIC.com/Intersil

ADDRESS

CE

t

OES

OE

WE

X28HC256

t

WC

t

AS

t

CS

t

AH

t

CW

t

OEH

t

CH

t

DS

DATA VALID

t

DH

DATA IN

DATA OUT

HIGH Z

Page Write Cycle

OE

(NOTE 9)

CE

t

WP

WE

ADDRESS

(NOTE 10)

I/O

*For each successive write within the page write operation, A7 to A

t

WPH

BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n + 1 BYTE n + 2

writes to an unknown address could occur.

NOTES:

9. Between successive byte writes within a page write operation, OE

data from another memory device within the system for the next write; or with WE

10. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the
or WE controlled write cycle timing.

CE

t

BLC

LAST BYTE

t

WC

should be the same or

15

can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch

HIGH and CE LOW effectively performing a polling operation.

14

FN8108.2

May 7, 2007

X28HC256

www.BDTIC.com/Intersil

DATA Polling Timing Diagram

ADDRESS A

CE

WE

OE

I/O

7

Toggle Bit Timing Diagram

CE

n

DIN = X

(Note 11)

(Note 11)

t

OEH

A

n

D

= X D

OUT

t

WC

A

n

t

OES

t

DW

= X

OUT

WE

t

OEH

OE

I/O

6

HIGH Z

*

t

WC

* I/O6 beginning and ending state will vary, depending upon actual tWC.

NOTE:

11. Polling operations are by definition read cycles and are therefore subject to read cycle timings.

t

OES

t

DW

*

15

FN8108.2

May 7, 2007

X28HC256

www.BDTIC.com/Intersil

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

LEAD FINISH

c1

-A-

-B-

bbb C A - B

S

BASE

PLANE

SEATING

PLANE

S1

b2

b

ccc C A - BMD

D

A

A

e

S

S

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat­ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.

5. This dimension allows for off-center lid, meniscus, and glass
overrun.

6. Dimension Q shall be measured from the seating plane to the
base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

-D-

BASE

E

D

S

S

Q

A

-C-

L

METAL

b1

M

(b)

SECTION A-A

α

(c)

M

eA

eA/2

aaa CA - B

M

c

D

S

S

F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)

28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.232 - 5.92 -

b 0.014 0.026 0.36 0.66 2

b1 0.014 0.023 0.36 0.58 3

b2 0.045 0.065 1.14 1.65 -

b3 0.023 0.045 0.58 1.14 4

c 0.008 0.018 0.20 0.46 2

c1 0.008 0.015 0.20 0.38 3

D - 1.490 - 37.85 5

E 0.500 0.610 12.70 15.49 5

e 0.100 BSC 2.54 BSC -

eA 0.600 BSC 15.24 BSC -

eA/2 0.300 BSC 7.62 BSC -

L 0.125 0.200 3.18 5.08 -

Q 0.015 0.060 0.38 1.52 6

S1 0.005 - 0.13 - 7

o

α

90

105

o

90

o

105

aaa - 0.015 - 0.38 -

bbb - 0.030 - 0.76 -

ccc - 0.010 - 0.25 -

M - 0.0015 - 0.038 2, 3

N28 288

NOTESMIN MAX MIN MAX

o

Rev. 0 4/94

-

16

FN8108.2

May 7, 2007

X28HC256

www.BDTIC.com/Intersil

Plastic Leaded Chip Carrier Packages (PLCC)

0.042 (1.07)

0.048 (1.22)

NE

0.020 (0.51) MAX
3 PLCS

PIN (1)
IDENTIFIER

C

L

D1

D

0.050 (1.27)

MIN

0.025 (0.64)
MIN

0.042 (1.07)

0.056 (1.42)

0.050 (1.27) TP

ND

E1

VIEW “A” TYP.

C

L

E

0.026 (0.66)

0.032 (0.81)

0.013 (0.33)

0.021 (0.53)

(0.12)

0.005

0.004 (0.10) C

0.025 (0.64)

0.045 (1.14)

R

N32.45x55 (JEDEC MS-016AE ISSUE A)

32 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

INCHES MILLIMETERS

SYMBOL

NOTESMIN MAX MIN MAX

A 0.125 0.140 3.18 3.55 -

D2/E2

A1 0.060 0.095 1.53 2.41 -

D 0.485 0.495 12.32 12.57 -

D1 0.447 0.453 11.36 11.50 3

D2/E2

VIEW “A”

D2 0.188 0.223 4.78 5.66 4, 5

E 0.585 0.595 14.86 15.11 -

E1 0.547 0.553 13.90 14.04 3

E2 0.238 0.273 6.05 6.93 4, 5

0.015 (0.38)

-C-

MIN

SEATING
PLANE

A1

A

N28 286

ND 7 7 7

NE 9 9 7

Rev. 0 7/98

NOTES:

1. Controlling dimension: INCH. Converted millimeter dimen­sions are not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1 do not include mold protrusions. Al­lowable mold protrusion is 0.010 inch (0.25mm) per side.
Dimensions D1 and E1 include mold mismatch and are mea­sured at the extreme material condition at the body parting

M

DS

- B SAS

line.

4. To be measured at seating plane contact point.

-C-

5. Centerline to be determined where center leads exit plastic
body.

6. “N” is the number of terminal positions.

7. ND denotes the number of leads on the two shorts sides of the
package, one of which contains pin #1. NE denotes the num­ber of leads on the two long sides of the package.

17

FN8108.2

May 7, 2007

X28HC256

www.BDTIC.com/Intersil

Ceramic Pin Grid Array Package (CPGA)

12 13 15 17 18

11 10 14 16 19

9 8 20 21

7 6 22 23

5 2 28 24 25

4 3 1 27 26

Typ. 0.100 (2.54 )

All Leads

Pin 1 Index

0.080 (2.03)

0.070 (1.78)

G28.550x650A
28 LEAD CERAMIC PIN GRID ARRAY PACKAGE

A

A

NOTE: Leads 4, 12, 18, and 26

0.080 (2.03) 4 Corners

0.070 (1.78)

0.008 (0.20)

0.050 (1.27)

0.110 (2.79)

0.090 (2.29)

0.072 (1.83)

0.062 (1.57)

0.660 (16.76)

0.640 (16.26)

A

A

0.561 (14.25)

0.541 (13.75)

NOTE: All dimensions in inches (in parentheses in millimeters).

0.020 (0.51)

0.016 (0.41)

0.185 (4.70)

0.175 (4.44)

Rev. 0 12/05

18

FN8108.2

May 7, 2007

Small Outline Package Family (SO)

www.BDTIC.com/Intersil

A

D

NN

(N/2)+1

X28HC256

h X 45°

PIN #1

E

C

SEATING
PLANE

0.004 C

E1

B

0.010 BM CA

I.D. MARK

1

e

0.010 BM CA

(N/2)

c

SEE DETAIL “X”

L1

H

A2

GAUGE
PLANE

A1

b

DETAIL X

L

4° ±4°

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

INCHES

SO16

SYMBOL

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28)

TOLERANCE NOTESSO-8 SO-14

A

0.010

Rev. M 2/07

19

FN8108.2

May 7, 2007

Dual-In-Line Plastic Packages (PDIP)

www.BDTIC.com/Intersil

X28HC256

N

D1

-C-

E1

-B-

A1

A2

E

A

L

e

C

C

L

e

A

C

e

B

INDEX

AREA

BASE

PLANE

SEATING

PLANE

D1

B1

12 3 N/2

-A­D

e

B

0.010 (0.25) C AM BS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpendic-

7. e

e

A

ular to datum .

and eC are measured at the lead tips with the leads unconstrained.

B

e

must be zero or greater.

C

-C-

8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

E28.6 (JEDEC MS-011-AB ISSUE B)

28 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.250 - 6.35 4

A1 0.015 - 0.39 - 4

A2 0.125 0.195 3.18 4.95 -

B 0.014 0.022 0.356 0.558 -

B1 0.030 0.070 0.77 1.77 8

C 0.008 0.015 0.204 0.381 -

D 1.380 1.565 35.1 39.7 5

D1 0.005 - 0.13 - 5

E 0.600 0.625 15.24 15.87 6

E1 0.485 0.580 12.32 14.73 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

0.600 BSC 15.24 BSC 6

- 0.700 - 17.78 7

L 0.115 0.200 2.93 5.08 4

N28 289

NOTESMIN MAX MIN MAX

Rev. 1 12/00

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

20

FN8108.2

May 7, 2007