intersil X28HC256 DATA SHEET

www.BDTIC.com/Intersil

X28HC256

256k, 32k x 8-Bit

Data Sheet May 7, 2007

5V, Byte Alterable EEPROM

The X28HC256 is a second generation high performance CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s proprietary, textured poly floating gate technology, providing a highly reliable 5V only nonvolatile memory.

The X28HC256 supports a 128-byte page write operation, effectively providing a 24µs/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The X28HC256 also features DATA Toggle Bit Polling, two methods of providing early end of write detection. The X28HC256 also supports the JEDEC standard Software Data Protection feature for protecting against inadvertent writes during power-up and power-down.

Endurance for the X28HC256 is specified as a minimum 1,000,000 write cycles per byte and an inherent data retention of 100 years.

Polling and

FN8108.2

Features

• Access time: 70ns

• Simple byte and page write

- Single 5V supply

- No external high voltages or V

- Self-timed

- No erase before write

- No complex programming algorithms

- No overerase problem

• Low power CMOS

- Active: 60mA

- Standby: 500µA

• Software data protection

- Protects data against system level inadvertent writes

• High speed page write capability

• Highly reliable Direct Write

™

- Endurance: 1,000,000 cycles

- Data retention: 100 years

P-P

cell

control circuits

Block Diagram

A0 TO A ADDRESS

INPUTS

• Early end of write detection

- DATA polling

- Toggle bit polling

• Pb-free plus anneal available (RoHS compliant)

256kBIT

X BUFFERS

LATCHES AND

DECODER

Y BUFFERS

LATCHES AND

DECODER

OE WE

CONTROL

LOGIC AND

TIMING

EEPROM

ARRAY

I/O BUFFERS

AND LATCHES

I/O0 TO I/O

DATA INPUTS/OUTPUTS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Ordering Information

www.BDTIC.com/Intersil

X28HC256

ACCESS TIME

PART NUMBER PART MARKING

X28HC256DI-15 X28HC256DI-15 RR 150 -40 to +85 28 Ld CERDIP F28.6 X28HC256DM-15 X28HC256DM-15 RR -55 to +125 28 Ld CERDIP F28.6 X28HC256DMB-15 C X28HC256DMB-15 MIL-STD-883 28 Ld CERDIP F28.6 X28HC256EMB-15 C X28HC256EMB-15 MIL-STD-883 32 Ld LCC (458 mils) X28HC256FMB-15 C X28HC256FMB-15 MIL-STD-883 28 Ld FLATPACK (440 mils) X28HC256J-15*, ** X28HC256J-15 RR 0 to +70 32 Ld PLCC N32.45x55 X28HC256JZ-15* (Note) X28HC256J-15 ZRR 0 to +70 32 Ld PLCC (Pb-free) N32.45x55 X28HC256JI-15*, ** X28HC256JI-15 RR -40 to +85 32 Ld PLCC N32.45x55 X28HC256JIZ-15* (Note) X28HC256JI-15 ZRR -40 to +85 32 Ld PLCC (Pb-free) N32.45x55 X28HC256JM-15* X28HC256JM-15 RR -55 to +125 32 Ld PLCC N32.45x55 X28HC256KI-15 X28HC256KI-15 RR -40 to +85 28 Ld PGA G28.550x650A X28HC256KM-15 X28HC256KM-15 RR -55 to +125 28 Ld PGA G28.550x650A X28HC256KMB-15 C X28HC256KMB-15 MIL-STD-883 28 Ld PGA G28.550x650A X28HC256P-15 X28HC256P-15 RR 0 to +70 28 Ld PDIP E28.6 X28HC256PZ-15 (Note) X28HC256P-15 RRZ 0 to +70 28 Ld PDIP (Pb-free)*** E28.6 X28HC256PI-15 X28HC256PI-15 RR -40 to +85 28 Ld PDIP E28.6 X28HC256PIZ-15 (Note) X28HC256PI-15 RRZ -40 to +85 28 Ld PDIP (Pb-free)*** E28.6 X28HC256PM-15 X28HC256PM-15 RR -55 to +125 28 Ld PDIP E28.6 X28HC256SI-15* X28HC256SI-15 RR -40 to +85 28 Ld SOIC (300 mil) MDP0027 X28HC256SIZ-15* (Note) X28HC256SI-15 RRZ -40 to +85 28 Ld SOIC (300 mil) (Pb-free) MDP0027 X28HC256SM-15 X28HC256SM-15 RR -55 to +125 28 Ld SOIC (300 mil) MDP0027 X28HC256D-12 X28HC256D-12 RR 120 0 to +70 28 Ld CERDIP (520 mils) F28.6 X28HC256DI-12 X28HC256DI-12 RR -40 to +85 28 Ld CERDIP (520 mils) F28.6 X28HC256DM-12 X28HC256DM-12 RR -55 to +125 28 Ld CERDIP (520 mils) F28.6 X28HC256DMB-12 C X28HC256DMB-12 MIL-STD-883 28 Ld CERDIP (520 mils) F28.6 X28HC256EI-12 X28HC256EI-12 RR -40 to +85 32 Ld LCC (458 mils) X28HC256EM-12 X28HC256EM-12 RR -55 to +125 32 Ld LCC (458 mils) X28HC256EMB-12 C X28HC256EMB-12 MIL-STD-883 32 Ld LCC (458 mils) X28HC256FMB-12 C X28HC256FMB-12 MIL-STD-883 28 Ld FLATPACK (440 mils) X28HC256J-12* X28HC256J-12 RR 0 to +70 32 Ld PLCC N32.45x55 X28HC256JZ-12* (Note) X28HC256J-12 ZRR 0 to +70 32 Ld PLCC (Pb-free) N32.45x55 X28HC256JI-12* X28HC256JI-12 RR -40 to +85 32 Ld PLCC N32.45x55 X28HC256JIZ-12* (Note) X28HC256JI-12 ZRR -40 to +85 32 Ld PLCC (Pb-free) N32.45x55 X28HC256KI-12 X28HC256KI-12 RR -40 to +85 28 Ld PGA G28.550x650A X28HC256KM-12 X28HC256KM-12 RR -55 to +125 28 Ld PGA G28.550x650A X28HC256KMB-12 C X28HC256KMB-12 MIL-STD-883 28 Ld PGA G28.550x650A X28HC256P-12 X28HC256P-12 RR 0 to +70 28 Ld PDIP E28.6 X28HC256PZ-12 (Note) X28HC256P-12 RRZ 0 to +70 28 Ld PDIP (Pb-free)*** E28.6 X28HC256PI-12 X28HC256PI-12 RR -40 to +85 28 Ld PDIP E28.6

(ns)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

FN8108.2

May 7, 2007

Ordering Information (Continued)

www.BDTIC.com/Intersil

X28HC256

ACCESS TIME

PART NUMBER PART MARKING

X28HC256PIZ-12 (Note) X28HC256PI-12 RRZ -40 to +85 28 Ld PDIP (Pb-free)*** E28.6 X28HC256S-12* X28HC256S-12 RR 120 0 to +70 28 Ld SOIC (300 mils) MDP0027 X28HC256SZ-12 (Note) X28HC256S-12 RRZ 0 to +70 28 Ld SOIC (300 mils) (Pb-free) MDP0027 X28HC256SI-12* X28HC256SI-12 RR -40 to +85 28 Ld SOIC (300 mils) MDP0027 X28HC256SIZ-12 (Note) X28HC256SI-12 RRZ -40 to +85 28 Ld SOIC (300 mils) (Pb-free) MDP0027 X28HC256SM-12*, ** X28HC256SM-12 RR -55 to +125 28 Ld SOIC (300 mils) MDP0027 X28HC256D-90 X28HC256D-90 RR 90 0 to +70 28 Ld CERDIP (520 mils) F28.6 X28HC256DI-90 X28HC256DI-90 RR -40 to +85 28 Ld CERDIP (520 mils) F28.6 X28HC256DM-90 X28HC256DM-90 RR -55 to +125 28 Ld CERDIP (520 mils) F28.6 X28HC256DMB-90 C X28HC256DMB-90 MIL-STD-883 28 Ld CERDIP (520 mils) F28.6 X28HC256EM-90 X28HC256EM-90 RR -55 to +125 32 Ld LCC (458 mils) X28HC256EMB-90 C X28HC256EMB-90 MIL-STD-883 32 Ld LCC (458 mils) X28HC256FI-90 X28HC256FI-90 RR -40 to +85 28 Ld FLATPACK (440 mils) X28HC256FM-90 X28HC256FM-90 RR -55 to +125 28 Ld FLATPACK (440 mils) X28HC256FMB-90 C X28HC256FMB-90 MIL-STD-883 28 Ld FLATPACK (440 mils) X28HC256J-90* X28HC256J-90 RR 0 to +70 32 Ld PLCC N32.45x55 X28HC256JZ-90* (Note) X28HC256J-90 ZRR 0 to +70 32 Ld PLCC (Pb-free) N32.45x55 X28HC256JI-90* X28HC256JI-90 RR -40 to +85 32 Ld PLCC N32.45x55 X28HC256JIZ-90* (Note) X28HC256JI-90 ZRR -40 to +85 32 Ld PLCC (Pb-free) N32.45x55 X28HC256JM-90* X28HC256JM-90 RR -55 to +125 32 Ld PLCC N32.45x55 X28HC256KM-90 X28HC256KM-90 RR -55 to +125 28 Ld PGA G28.550x650A X28HC256KMB-90 C X28HC256KMB-90 MIL-STD-883 28 Ld PGA G28.550x650A X28HC256P-90 X28HC256P-90 RR 90 0 to +70 28 Ld PDIP E28.6 X28HC256PZ-90 (Note) X28HC256P-90 RRZ 0 to +70 28 Ld PDIP (Pb-free)*** E28.6 X28HC256PI-90 X28HC256PI-90 RR -40 to +85 28 Ld PDIP E28.6 X28HC256PIZ-90 (Note) X28HC256PI-90 RRZ -40 to +85 28 Ld PDIP (Pb-free)** E28.6 X28HC256S-90* X28HC256S-90 RR 0 to +70 28 Ld SOIC (300 mils) MDP0027 X28HC256SI-90* X28HC256SI-90 RR -40 to +85 28 Ld SOIC (300 mils) MDP0027 X28HC256SIZ-90 (Note) X28HC256SI-90 RRZ -40 to +85 28 Ld SOIC (300 mils) (Pb-free) MDP0027 X28HC256SI-20T1 200 -40 to +85 28 Ld SOIC (300 mils) Tape and Reel MDP0027

*Add "T1" suffix for tape and reel. **Add "T2" suffix for tape and reel. ***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

(ns)

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

FN8108.2

May 7, 2007

Pinouts

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I/O

X28HC256

TOP VIEW

X28HC256

WE A

OE A

CE I/O

I/O6

I/O

I/O3

(28 LD CERDIP, FLATPACK, PDIP, SOIC)

Pin Descriptions

X28HC256

(32 LD PLCC, LCC)

4 3 2 1 32 31 30

8 9

I/O

14 15 16 17 18 19 20

I/O1

X28HC256

TOP VIEW

A12A

X28HC256

I/O

X28HC256

(28 LD PGA)

BOTTOM VIEW

CE I/O

I/O

8 A

6 A

2 A12

I/O

X28HC256

I/O

VSS

I/O

I/O4

I/O

Addresses (A0 to A14)

The Address inputs select an 8-bit memory location during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/write operations. When CE

is HIGH, power consumption is

reduced.

Output Enable (OE)

The Output Enable input controls the d ata output buffers, and is used to initiate read operations.

Data In/Data Out (I/O0 to I/O7)

Data is written to or read from the X28HC256 through the I/O pins.

Write Enable (WE)

The Write Enable input controls the writing of data to the X28HC256.

FN8108.2

May 7, 2007

X28HC256

www.BDTIC.com/Intersil

Pin Names

SYMBOL DESCRIPTION

to A

I/O0 to I/O

CE OE Output Enable

NC No Connect

Address Inputs

Data Input/Output

Write Enable

Chip Enable

+5V

Ground

Device Operation

Read

Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE

Write

Write operations are initiated when both CE and WE are LOW and OE and WE by the falling edge of either CE

is HIGH. The X28HC256 supports both a CE

controlled write cycle. That is, the address is latched

or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE

or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 3ms.

Page Write Operation

The page write feature of the X28HC256 allows the entire memory to be written in typically 0.8 seconds. Page write allows up to one hundred twenty-eight bytes of data to be consecutively written to the X28HC256, prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A write cycle to the part during this operation must be the same as the initial page address.

through A14) for each subsequent valid

or OE returning

or CE is HIGH.

The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twenty-seven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE

HIGH to LOW transition, must begin within 100µs of the falling edge of the preceding WE

. If a subsequent WE HIGH to LOW transition is not detected within 100µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100µs.

Write Operation Status Bits

The X28HC256 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1.

5TBDP 43210I/O

RESERVED

TOGGLE BIT

DATA

POLLING

FIGURE 1. STATUS BIT ASSIGNMENT

DATA Polling (I/O7)

The X28HC256 features DA T A Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA

Polling allows a simple bit test operation to determine the status of the X28HC256. This eliminates additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O

(i.e.,

write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O

will reflect true data.

Toggle Bit (I/O6)

The X28HC256 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease, and the device will be accessible for additional read and write operations.

will toggle from HIGH to

FN8108.2

May 7, 2007

X28HC256

www.BDTIC.com/Intersil

DATA Polling I/O

WRITE

I/O

A0 TO A

WRITE DATA

LAST

An An An An An An

HIGH Z

FIGURE 2. DATA POLLING BUS SEQUENCE

DATA Polling can effectively halve the time for writing to the X28HC256. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine.

X28HC256 READY

WRITES

COMPLETE?

YES

SAVE LAST DATA

AND ADDRESS

READ LAST

ADDRESS

COMPARE?

YES

X28HC256

READY

FIGURE 3. DATA POLLING SOFTWARE FLOW

FN8108.2

May 7, 2007

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