intersil X28C512, X28C513 DATA SHEET
®
www.BDTIC.com/Intersil
X28C512, X28C513
Data Sheet June 7, 2006
5V, Byte Alterable EEPROM
The X28C512, X28C513 are 64K x 8 EEPROM, fabricated
with Intersil’s proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable nonvolatile
memories, the X28C512, X28C513 are 5V only devices. The
X28C512, X28C513 feature the JEDEC approved pin out for
byte wide memories, compatible with industry standard
EPROMS.
The X28C512, X28C513 support a 128-byte page write
operation, effectively providing a 39µs/byte write cycle and
enabling the entire memory to be written in less than 2.5
seconds. The X28C512, X28C513 also feature DAT A
and Toggle Bit Polling, system software support schemes
used to indicate the early completion of a write cycle. In
addition, the X28C512, X28C513 support the software data
protection option.
Polling
FN8106.2
Features
• Access Time: 90ns
• Simple Byte and Page Write
- Single 5V supply
• No external high voltages or VPP control circuits
- Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low Power CMOS
- Active: 50mA
- Standby: 500µA
• Software Data Protection
- Protects data against system level inadvertent writes
• High Speed Page Write Capability
™
• Highly Reliable Direct Write
- Endurance: 100,000 write cycles
- Data retention: 100 years
- Early end of write detection
-DATA
- Toggle bit polling
polling
Cell
• Two PLCC and LCC Pinouts
- X28C512
• X28C010 EPROM pin compatible
- X28C513
• Compatible with lower density EEPROMs
• Pb-Free Plus Anneal Available (RoHS Compliant)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
Block Diagram
www.BDTIC.com/Intersil
A7-A
X28C512, X28C513
512Kbit
X Buffers
15
Latches and
Decoder
EEPROM
Array
I/O Buffers
and Latches
I/O0-I/O
7
Data Inputs/Outputs
A0-A
6
V
V
CE
OE
WE
CC
SS
Y Buffers
Latches and
Decoder
Control
Logic and
Timing
Ordering Information
PART NUMBER PART MARKING
X28C512D X28C512D - 0 to +70 32 Ld CERDIP
X28C512DM X28C512DM -55 to +125 32 Ld CERDIP
X28C512J X28C512J 0 to +70 32 Ld PLCC
X28C513EM X28C513EM -55 to +125 32 Ld LCC
X28C512D-12 X28C512D-12 120 0 to +70 32 Ld CERDIP
X28C512DI-12 X28C512DI-12 -40 to +85 32 Ld CERDIP
X28C512DMB-12 X28C512DMB-12 Mil-STD-883 32 Ld CERDIP
X28C512FMB-12 X28C512FMB-12 Mil-STD-883 32 Ld Flat Pack
X28C512J-12* X28C512J-12 0 to +70 32 Ld PLCC
X28C512JZ-12* (See Note) X28C512J-12 Z 0 to +70 32 Ld PLCC (Pb-free)
X28C512JI-12 X28C512JI-12 -40 to +85 32 Ld PLCC
X28C512JIZ-12* (See Note) X28C512JI-12 Z -40 to +85 32 Ld PLCC (Pb-free)
X28C512JM-12 X28C512JM-12 -55 to +125 32 Ld PLCC
X28C512KM-12 X28C512KM-12 -55 to +125 36 Ld CPGA
X28C512PI-12 X28C512PI-12 -40 to +85 32 Ld PDIP
X28C512RMB-12 X28C512RMB-12 Mil-STD-883 32 Ld Flat Pack
X28C513EM-12 X28C513EM-12 -55 to +125 32 Ld LCC
X28C513EMB-12 X28C513EMB-12 Mil-STD-883 32 Ld LCC
X28C513J-12* X28C513J-12 0 to +70 32 Ld PLCC
X28C513JZ-12* (Note) X28C513J-12 Z 0 to +70 32 Ld PLCC (Pb-free)
X28C513JI-12* X28C513JI-12 -40 to +85 32 Ld PLCC
X28C513JIZ-12* (Note) X28C513JI-12 Z -40 to +85 32 Ld PLCC (Pb-free)
X28C513JM-12 X28C513JM-12 -55 to +125 32 Ld PLCC
ACCESS TIME
(ns) TEMP RANGE (°C) PACKAGE
2
FN8106.2
June 7, 2006
X28C512, X28C513
www.BDTIC.com/Intersil
Ordering Information (Continued)
ACCESS TIME
PART NUMBER PART MARKING
X28C512D-15 X28C512D-15 150 0 to +70 32 Ld CERDIP
X28C512DI-15 X28C512DI-15 -40 to +85 32 Ld CERDIP
X28C512DMB-15 X28C512DMB-15 Mil-STD-883 32 Ld CERDIP
X28C512J-15* X28C512J-15 0 to +70 32 Ld PLCC
X28C512JZ-15* (See Note) X28C512J-15 Z 0 to +70 32 Ld PLCC (Pb-free)
X28C512JI-15* X28C512JI-15 -40 to +85 32 Ld PLCC
X28C512JIZ-15* (See Note) X28C512JI-15 Z -40 to +85 32 Ld PLCC (Pb-free)
X28C512JM-15 X28C512JM-15 -55 to +125 32 Ld PLCC
X28C513EM-15 X28C513EM-15 -55 to +125 32 Ld LCC
X28C513EMB-15 X28C513EMB-15 Mil-STD-883 32 Ld LCC
X28C513J-15* X28C513J-15 0 to +70 32 Ld PLCC
X28C513JZ-15* (Note) X28C513J-15 Z 0 to +70 32 Ld PLCC (Pb-free)
X28C513JI-15 X28C513JI-15 -40 to +85 32 Ld PLCC
X28C513JIZ-15* (Note) X28C513JI-15 Z -40 to +85 32 Ld PLCC (Pb-free)
X28C513JM-15 X28C513JM-15 -55 to +125 32 Ld PLCC
X28C512DMB-20 X28C512DMB-20 200 Mil-STD-883 32 Ld CERDIP
X28C512JM-20 X28C512JM-20 -55 to +125 32 Ld PLCC
X28C512KI-20 X28C512KI-20 -40 to +85 36 Ld CPGA
X28C512KM-20 X28C512KM-20 -55 to +125 36 Ld CPGA
X28C513EI-20 X28C513EI-20 -40 to +85 32 Ld LCC
X28C513EM-20 X28C513EM-20 -55 to +125 32 Ld LCC
X28C513EMB-20 X28C513EMB-20 Mil-STD-883 32 Ld LCC
X28C513J-20T1 X28C513J-20 0 to +70 32 Ld PLCC Tape and Reel
X28C512EM-25 X28C512EM-25 250 -55 to +125 32 Ld LCC
X28C512JM-25 X28C512JM-25 -55 to +125 32 Ld PLCC
X28C512KM-25 X28C512KM-25 -55 to +125 36 Ld CPGA
X28C512KMB-25 X28C512KMB-25 Mil-STD-883 36 Ld CPGA
X28C513EM-25 X28C513EM-25 -55 to +125 32 Ld LCC
X28C513EMB-25 X28C513EMB-25 Mil-STD-883 32 Ld LCC
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal p roducts e mploy special Pb-free mate rial sets; mold ing compounds/die att ach materials and 10 0% matte tin pla te termination fi nish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering ope rations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
(ns) TEMP RANGE (°C) PACKAGE
3
FN8106.2
June 7, 2006
Pinouts
www.BDTIC.com/Intersil
NC
NC
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
Plastic DIP
CERDIP
FLAT Pack
SOIC (R)
1
2
3
4
5
6
7
8
X28C512
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
WE
NC
A
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
CC
14
13
8
9
11
10
X28C512, X28C513
PLCC/LCC
12
A
A
NC
4 3
5
A7
A
6
PGA
I/O0
I/O2
I/O3
I/O
I/O6
15
17
A
A1
13
A
2
12
A
4
10
A
6
8
A
12
6
I/O
0
1
14
16
A
3
11
A
5
9
A
7
7
2 NC
A
15
5
NC 3 NC 1 NC
4
Bottom
5
4
3
2
1
19
VSS
18
View
VCC
36
5
21
I/O
4
20
NC
34
35 WE33
22
CE
I/O7
23
24
OE
A10
25
26
A
A
11
9
27
28
A8
A
13
29
30
NC
A14
32
31
NC
6
A
5
A
4
A3
A
2
A
1
A0
I/O
0
A6
A
5
A
4
A
3
A2
A
1
A
0
NC
I/O
0
7
8
X28C512
9
(Top View)
10
11
12
13
15 17 16 18 19 20
14
I/O1
I/O2VSSI/O3I/O4I/O5I/O
7
A
A
4 3
5
6
7
8
X28C513
9
(Top View)
10
11
12
13
15 17 16 18 19 20
14
I/O1
I/O2V
15
NC
VCC WE
2 32
1
12
VCC WE
A14A15A
2 32
1
SS
NC
I/O
3
31
31
29
28
27
26
25
24
23
22
29
28
27
26
25
24
23
22
I/O4I/O
NC
30
A14
A
13
A
8
A9
A
11
OE
A
10
CE
I/O
7
21
6
13
30
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
21
5
Pin Descriptions
Addresses (A0-A15)
The Address inputs select an 8-bit memory location during a
read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is
reduced.
Output Enable (OE
The Output Enable input controls the data output buffers and
is used to initiate read operations.
Data In/Data Out (I/O
Data is written to or read from the X28C512, X28C513
through the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C512, X28C513.
)
-I/O7)
0
Pin Names
SYMBOL DESCRIPTION
A
0-A15
I/O0-I/O
7
WE
CE
OE
V
CC
V
SS
NC No Connect
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
4
FN8106.2
June 7, 2006
X28C512, X28C513
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Device Operation
Read
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in
a high impedance state when either OE
Write
Write operations are initiated when both CE and WE are
LOW and OE
both a CE
address is latched by the falling edge of either CE
whichever occurs last. Similarly, the data is latched internally
by the rising edge of either CE
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
is HIGH. The X28C512, X28C513 support
and WE controlled write cycle. That is, the
or WE, whichever occurs first.
Page Write Operation
The page write feature of the X28C512, X28C513 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to one hundred twenty-eight bytes of data to be
consecutively written to the X28C512, X28C513, prior to the
commencement of the internal programming cycle. The host
can fetch data from another device within the system during
a page write operation (change the source address), but the
page address (A
write cycle to the part during this operation must be the same
as the initial page address.
through A15) for each subsequent valid
7
or OE returning
or CE is HIGH.
or WE,
DATA Polling (I/O7)
The X28C512, X28C513 feature DATA polling as a method
to indicate to the host system that the byte write or page
write cycle has completed. DATA
test operation to determine the status of the X28C512,
X28C513, eliminating additional interrupt inputs or external
hardware. During the internal programming cycle, any
attempt to read the last byte written will produce the
complement of that data on I/O
read data = 1xxx xxxx). Once the programming cycle is
complete, I/O
will reflect true data.
7
Polling allows a simple bit
(i.e. write data = 0xxx xxxx,
7
Toggle Bit (I/O6)
The X28C512, X28C513 also provide another method for
determining when the internal write cycle is complete. During
the internal programming cycle, I/O
LOW and LOW to HIGH on subsequent attempts to read the
device. When the internal cycle is complete, the toggling will
cease, and the device will be accessible for additional read
or write operations.
will toggle from HIGH to
6
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to one hundred twenty-seven bytes in
the same manner as the first byte was written. Each
successive byte load cycle, started by the WE
transition, must begin within 100µs of the falling edge of the
preceding WE
is not detected within 100µs, the internal automatic
programming cycle will commence. There is no page write
window limitation. Effectively, the page write window is
infinitely wide, so long as the host continues to access the
device within the byte load cycle time of 100µs.
. If a subsequent WE HIGH to LOW transition
HIGH to LOW
Write Operation Status Bits
The X28C512, X28C513 provide the user two write
operation status bits. These can be used to optimize a
system write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
5TBDP 43210I/O
Reserved
Toggle Bit
DATA
Polling
FIGURE 1. STATUS BIT ASSIGNMENT
5
FN8106.2
June 7, 2006
X28C512, X28C513
www.BDTIC.com/Intersil
DATA Polling I/O
Last
Write
WE
CE
OE
V
IH
I/O
7
A0-A
A
15
n
Write Data
7
V
HIGH Z
V
OL
A
n
A
n
A
n
A
n
A
n
A
FIGURE 2A. DATA POLLING BUS SEQUENCE
DATA Polling can effectively halve the time for writing to the
X28C512, X28C513. The timing diagram in Figure 2A
illustrates the sequence of events on the bus. The software
flow diagram in Figure 2B illustrates one method of
implementing the routine.
OH
X28C512, X28C513
Ready
n
Writes
Complete?
Yes
Save Last Data
and Address
Read Last
Address
IO
7
Compare?
Yes
Ready
No
No
FIGURE 2B. DATA POLLING SOFTWARE FLOW
6
FN8106.2
June 7, 2006
X28C512, X28C513
www.BDTIC.com/Intersil
The Toggle Bit I/O
Last
WE
Write
CE
OE
I/O
6
Load Accum
From Addr N
FIGURE 3B. TOGGLE BIT SOFTWARE FLOW
6
Last Write
Compare
Accum with
Addr N
Compare
Ok?
Yes
X28C512
Ready
V
No
OH
V
OL
* Beginning and ending state of I/O6 will vary.
FIGURE 3A. TOGGLE BIT BUS SEQUENCE
*
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA
Polling. This can be especially helpful in an array
comprised of multiple X28C512, X28C513 memories that
are frequently updated. Toggle Bit Polling can also provide a
method for status checking in multiprocessor applications.
The timing diagram in Figure 3A illustrates the sequence of
events on the bus. The software flow diagram in Figure 3B
illustrates a method for polling the Toggle Bit.
HIGH Z
*
X28C512, X28C513
Ready
Hardware Data Protection
The X28C512, X28C513 provide three hardware features
that protect nonvolatile data from inadvertent writes.
- Noise Protection—A WE
pulse typically less than 10ns
will not initiate a write cycle.
- Default V
when V
Sense—All write functions are inhibited
CC
is 3.6V.
CC
- Write Inhibit—Holding either OE LOW, WE HIGH, or CE
HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
Write cycle timing specifications must be observed
concurrently.
Software Data Protection
The X28C512, X28C513 offer a software controlled data
protection feature. The X28C512, X28C513 are shipped
from Intersil with the software data protection NOT
ENABLED; that is, the device will be in the standard
operating mode. In this mode data should be protected
during power-up/-down operations through the use of
external circuits. The host would then have open read and
write access of the device once V
The X28C512, X28C513 can be automatically protected
during power-up and power-down without the need for
external circuits by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation utilizing the software
algorithm. This circuit is nonvolatile and will remain set for
the life of the device unless the reset command is issued.
Once the software protection is enabled, the X28C512,
X28C513 are also protected from inadvertent and accidental
writes in the powered-up state. That is, the software
algorithm must be issued prior to writing additional data to
the device. Note: The data in the three-byte enable
sequence is not written to the memory array.
was stable.
CC
7
FN8106.2
June 7, 2006
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