intersil X28C010 DATA SHEET

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X28C010

Data Sheet May 11, 2005

5 Volt, Byte Alterable EEPROM

The Intersil X28C010 is a 128K x 8 EEPROM, fabricated with Intersil's proprietary, high performance, floating gate CMOS technology. Like all Intersil programmable nonvolatile memories, the X28C010 is a 5V only device. The X28C010 features the JEDEC approved pin out for bytewide memories, compatible with industry standard EEPROMs.

The X28C010 supports a 256-byte page write operation, effectively providing a 19µs/byte write cycle and enabling the entire memory to be typically written in less than 2.5 seconds. The X28C010 also features DATA Polling and Toggle Bit Polling, system software support schemes used to indicate the early completion of a write cycle. In addition, the X28C010 supports Software Data Protection option.

Intersil EEPROMs are designed and tested for applications requiring extended endurance. Data retention is specified to be greater than 100 years.

FN8105.0

Features

• Access time: 120ns

• Simple byte and page write

- Single 5V supply

cell

control

PP

- No external high voltages or V circuits

- Self-timed

• No erase before write

• No complex programming algorithms

• No overerase problem

• Low power CMOS

- Active: 50mA

- Standby: 500µA

• Software data protection

- Protects data against system level inadvertent writes

• High speed page write capability

• Highly reliable Direct Write

™

- Endurance: 100,000 write cycles

- Data retention: 100 years

Pinouts

NC

A

16

A

15

A

12

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

I/O

0

I/O

1

I/O

2

V

SS

CERDIP

Flat Pack

SOIC (R)

1 2

3 4

5 6

7 8

X28C010

9 10 11 12

13 14 15 16

• Early end of write detection

-DATA polling

- Toggle bit polling

PLCC

PGA

I/O

0

V

32

CC

WE

31 30

NC

29

A

28

A

27

A

26

A

25

A

24

OE

23

A

22

CE

21

I/O

20

I/O

19

I/O

18

I/O

17

I/O

A

1

13

A

14 13 8 9 11

2

12

A

4

10

A

6

8

A

12

6

10

7 6 5

4 3

15

17

A

0

14

16

A

3

11

A

5

9

(Bottom View)

A

7

A

15

5

A

16

4

2

19

I/O

V

1

SS

18

X28C010

V

CC

2NC36

3NC1NC35

I/O

3

5

6

21

22

I/O

4

20

NC

34

WE

CE

I/O

7

23

24

OE

A

10

26

25

A

9

11

28

27

A

13

8

30

29

A

NC

14

31

32

NC

33

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

I/O

0

12

A

5 6 7

8 9

(Top View)

10 11 12

13

15 1716 18 1920

14

1

I/O

A11

A9

A8 A13 A14

NC

WE

VCC

NC

NC A16 A15 A12

A7

A6

A5

A4

LCC

15

16

A

NC

23243 31

1

X28C010

2

3

SS

I/O

V

I/O

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

CC

V

WE

NC

30

A

29

14

A

28

13

A

27

8

A

26

9

A

25

11

24

OE A

23

10

22

CE I/O

7

21

4

5

6

I/O

TSOP

X28C010

EXTENDED LCC

12 A

A

5

7

A

6

A

7

5

A

8

4

X28C010

A

9

3

(Top View)

A

10

2

A

11

1

A

12

0

13

I/O

0

15 1716 18 19 20

14

1

I/O

15

16 A

NC

23243 31

1

2

3

SS

I/O

V

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

CC

V

WE

NC

30

A

29

14

A

28

13

A

27

8

A

26

9

A

25

11

OE

24

A

23

10

CE

22 21

I/O

7

4

5

6

I/O

OE A10

CE I/O7 I/O6 I/O5 I/O4 I/O3 NC NC VSS NC NC I/O2 I/O1 I/O0 A0 A1 A2 A3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X28C010

Ordering Information

ACCESS

PART NUMBER

X28C010D - 32-Ld Cerdip 0 to 70

X28C010D-12 120ns 32-Ld Cerdip 0 to 70

X28C010D-15 150ns 32-Ld Cerdip 0 to 70

X28C010DI - 32-Ld Cerdip -40 to +85

X28C010DI-12 120ns 32-Ld Cerdip -40 to +85

X28C010DI-15 150ns 32-Ld Cerdip -40 to +85

X28C010DI15C7681

X28C010DM - 32-Ld Cerdip -55 to +125

X28C010DM-12 120ns 32-Ld Cerdip -55 to +125

X28C010DMB-12 120ns 32-Ld Cerdip MIL-STD-883

X28C010DMB12C7309

X28C010DMB12C7729

X28C010DMB-15 150ns 32-Ld Cerdip MIL-STD-883

X28C010DMB15C7762

X28C010DMB-20 200ns 32-Ld Cerdip MIL-STD-883

X28C010DMC7237 - 32-Ld Cerdip

X28C010FI-12 120ns 32-Ld Flat Pack -40 to +85

X28C010FI-15 150ns 32-Ld Flat Pack -40 to +85

X28C010FI15C1009

X28C010FI-20 200ns 32-Ld Flat Pack -40 to +85

X28C010FI-25 250ns 32-Ld Flat Pack -40 to +85

X28C010FM - 32-Ld Flat Pack -55 to +125

X28C010FM-12 120ns 32-Ld Flat Pack -55 to +125

X28C010FMB-15 150ns 32-Ld Flat Pack MIL-STD-883

X28C010FMB15C7619

X28C010FMB15C7808

X28C010K-25 250ns 36-Ld Pin Grid

X28C010KM-12 120ns 36-Ld Pin Grid

X28C010KM-25 250ns 36-Ld Pin Grid

X28C010KM25C7237

X28C010KMB-15 150ns 36-Ld Pin Grid

TIME PACKAGE

150ns 32-Ld Cerdip -40 to +85

120ns 32-Ld Cerdip MIL-STD-883

150ns 32-Ld Cerdip MIL-STD-883

150ns 32-Ld Flat Pack -40 to +85

150ns 32-Ld Flat Pack MIL-STD-883

Array

250ns 36-Ld Pin Grid

Array

TEMP

RANGE (°C)

0 to 70

-55 to +125

MIL-STD-883

Ordering Information (Continued)

ACCESS

PART NUMBER

X28C010NM-12 120ns 32-Ld Extended

X28C010NM-15 150ns 32-Ld Extended

X28C010NMB-12 120ns 32-Ld Extended

X28C010NMB-15 150ns 32-Ld Extended

X28C010NMB15C7309

X28C010RI-12 120ns 32-Ld Ceramic

X28C010RI-20 200ns 32-Ld Ceramic

X28C010RI20C7168

X28C010RI20C7975

X28C010RI-20T1 200ns 32-Ld Ceramic

X28C010RI20T1C7168

X28C010RM-15 150ns 32-Ld Ceramic

X28C010RMB-25 250ns 32-Ld Ceramic

TIME PACKAGE

LCC

150ns 32-Ld Extended

LCC

SOIC (Gull Wing)

200ns 32-Ld Ceramic

SOIC (Gull Wing)

200ns 32-Ld Ceramic

SOIC (Gull Wing)

200ns 32-Ld Ceramic

SOIC (Gull Wing)

TEMP

RANGE (°C)

-55 to +125

MIL-STD-883

-40 to +85

-55 to +125

MIL-STD-883

2

FN8105.0

May 11, 2005

Block Diagram

X28C010

X Buffers

A

8-A16

A0-A

7

WE

V V

CE OE

CC SS

Latches and

Decoder

Y Buffers

Latches and

Decoder

Control

Logic and

Timing

Pin Descriptions

Addresses (A0-A16)

The Address inputs select an 8-bit memory location during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced.

Output Enable (OE

The Output Enable input controls the data output buffers, and is used to initiate read operations.

Data In/Data Out (I/O

Data is written to or read from the X28C010 through the I/O pins.

Write Enable (WE

The Write Enable input controls the writing of data to the X28C010.

)

-I/O7)

0

)

1Mbit

EEPROM

Array

I/O Buffers and Latches

I/O0-I/O

Data Inputs/Outputs

7

Pin Names

SYMBOL DESCRIPTION

A

0-A16

I/O

-I/O

0

7

WE Write Enable

CE

OE

V

CC

V

SS

NC No Connect

Address Inputs

Data Input/Output

Chip Enable

Output Enable

+5V

Ground

Device Operation

Read

Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE

or OE returning

or CE is HIGH.

Write

Write operations are initiated when both CE and WE are LOW and OE and WE by the falling edge of either CE last. Similarly, the data is latched internally by the rising edge of either CE operation, once initiated, will automatically continue to completion, typically within 5ms.

3

is HIGH. The X28C010 supports both a CE

controlled write cycle. That is, the address is latched

or WE, whichever occurs

or WE, whichever occurs first. A byte write

FN8105.0

May 11, 2005

Page Write Operation

The page write feature of the X28C010 allows the entire memory to be written in 5 seconds. Page write allows two to two hundred fifty-six bytes of data to be consecutively written to the X28C010 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A through A

) for each subsequent valid write cycle to the part

16

8

during this operation must be the same as the initial page address.

The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to two hundred fifty six bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE

HIGH to LOW transition, must begin within 100µs of the falling edge of the preceding WE

. If a subsequent WE HIGH to LOW transition is not detected within 100µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100µs.

Write Operation Status Bits

The X28C010 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1.

X28C010

5TBDP 43210I/O

Reserved

Toggle Bit

Polling

DATA

FIGURE 1. STATUS BIT ASSIGNMENT

DATA Polling (I/O7)

The X28C010 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA

Polling allows a simple bit test operation to determine the status of the X28C010, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O

(i.e., write

7

data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O

will reflect true data.

7

Note: If the X28C010 is in the protected state, and an illegal write operation is attempted, DATA

Polling will not operate.

Toggle Bit (I/O6)

The X28C010 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle, I/O LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.

will toggle from HIGH to LOW and

6

DATA Polling I/O

WE

CE

OE

I/O

7

A0-A

14

7

Last

Write

V

A

IH

n

HIGH Z

V

OL

A

n

A

n

FIGURE 2. DATA POLLING BUS SEQUENCE

A

n

A

n

A

n

V

OH

X28C010 Ready

A

n

4

FN8105.0

May 11, 2005

Write Data

X28C010

DATA Polling can effectively halve the time for writing to the X28C010. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine.

Writes

Complete?

Yes

Save Last Data

and Address

Read Last

Address

IO

7

Compare?

Yes

X28C010

Ready

No

FIGURE 3. DATA POLLING SOFTWARE FLOW

The Toggle Bit I/O

Last

Write

WE

CE

OE

I/O

6

V

OH

*

V

OL

* Beginning and ending state of I/O6 will vary

HIGH Z

*

X28C010 Ready

FIGURE 4. TOGGLE BIT BUS SEQUENCE

5

FN8105.0

May 11, 2005

X28C010

Last Write

Load Accum From Addr N

Compare

Accum with

Addr N

Compare

Ok?

Yes

Ready

FIGURE 5. TOGGLE BIT SOFTWARE FLOW

No

The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA

Polling. This can be especially helpful in an array comprised of multiple X28C010 memories that is frequently updated. Toggle Bit Polling can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit.

Hardware Data Protection

The X28C010 provides three hardware features that protect nonvolatile data from inadvertent writes.

• Noise Protection—A WE

pulse less than 10ns will not

initiate a write cycle.

• Default V

Sense—All functions are inhibited when VCC

CC

is ≤ 3.5V.

• Write inhibit—Holding either OE

LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during powerup and power-down, maintaining data integrity.

Software Data Protection

The X28C010 offers a software controlled data protection feature. The X28C010 is shipped from Intersil with the software data protection NOT ENABLED: that is the device will be in the standard operating mode. In this mode data should be protected during power-up/-down operations through the use of external circuits. The host would then have open read and write access of the device once V

CC

was stable.

The X28C010 can be automatically protected during powerup and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued.

Once the software protection is enabled, the X28C010 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device.

Software Algorithm

Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figures 6 and 7 for the sequence. The three byte sequence opens the page write window enabling the host to write from one to two hundred fifty-six bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state.

Software Data Protection

V

CC

0V

Data Addr

CE

WE

6

AA

5555

55

2AAA

FIGURE 6. TIMING SEQUENCE—BYTE OR PAGE WRITE

A0

5555

≤ t

BLC MAX

Writes

Ok

Byte

or

Page

t

WC

Write Protected

(VCC)

FN8105.0

May 11, 2005

Write Data AA

to Address

5555

Write Data 55

to Address

2AAA

Write Data A0

to Address

5555

Write Data XX

to Any

Address

Write Last

Byte

Last Address

Optional Byte/Page Load Operation

X28C010

Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the X28C010 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28C010 will be write protected during power-down and after any subsequent power-up. The state of A

and A16

15

while executing the algorithm is don’t care.

Note: Once initiated, the sequence of write operations should not be interrupted.

After t

Re-Enters Data

Protected State

WC

FIGURE 7. WRITE SEQUENCE FOR SOFTWARE DATA

PROTECTION

Resetting Software Data Protection

V

CC

CE

WE

Data AddrAA5555

FIGURE 8. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE

55

2AAA

80

5555

AA

5555

55

2AAA

20

5555

≥ t

WC

Standard Operating Mode

7

FN8105.0

May 11, 2005