Intersil RFW2N06RLE Datasheet

RFW2N06RLE

Data Sheet July 1999

2A, 60V, 0.160 Ohm, Logic Level,
N-Channel Power MOSFET

The RFW2N06RLE N-Channel, logic level, ESD protected,
power MOSFET is manufactured using the MegaFET
process. This process, which uses feature sizes
approaching those of LSI integrated circuits, gives optimum
utilization of silicon, resulting in outstanding performance.
The RFW2N06RLE was designed for use with logic level
(5V) driving sources in applications such as programmable
controllers, automotive switching, switching regulators,
switching converters, motor and relay drivers and emitter
switches for bipolar transistors. This performance is
accomplished through a special gate oxide design which
provides full rated conductance at gate biases in the 3V to
5V range, thereby facilitating true on-off power control
directly from logic circuit supply voltages.

Formerly developmental type TA9861.

Ordering Information

PART NUMBER PACKAGE BRAND

RFW2N06RLE HEXDIP RFW2N06RLE

NOTE: When ordering, use the entire part number.

File Number

Features

• 2A, 60V
(on) = 0.160Ω

•r

DS

• UIS Rating Curve (Single Pulse)

• Design Optimized For 5 Volt Gate Drive

• Can be Driven Directly from CMOS, NMOS, TTL

Circuits

• Compatible with Automotive Drive Requirements

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Majority Carrier Device

• Electrostatic Discharge Protected

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

2838.3

Packaging

G

S

4 PIN HEXDIP

DRAIN

GATE

SOURCE

6-283

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFW2N06RLE

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFW2N06RLE UNITS

Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

DGR

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DS

D

DM

GS

D

60 V
60 V

2

14

-5 to 10 V

1.09 W

A
A

Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.009 W/oC

Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

AS

Refer to UIS Curve

Electrostatic Discharge Rating, MIL-STD-883, Catagory B(2). . . . . . . . . . . . . . . . . . . . . . . .ESD 2 KV

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ,T

STG

-55 to 150

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 125oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V
Zero Gate Voltage Drain Current I

DSSID

GS(TH)VGS

DSS

=250µA, VGS = 0V 60 - - V

= VDS, ID = 250µA1-2V
VDS = Rated BV
VDS = 0.8 x Rated BV

, VGS = 0V - - 1 µA

DSS

DSS

, VGS = 0V

--25µA

TC = 125oC

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

GSS

DS(ON)ID

VGS =-5V to 10V - - ±100 nA

= 2A, VGS = 5V (Figure 8) - - 160 mΩ

ID = 2A, VGS = 4.3V (Figure 8) - - 200 mΩ

Turn-On Time t
Turn-On Delay Time t

(ON)

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

(OFF)
g(TOT)VGS

Gate Charge at 5V Qg(5) VGS = 0 to 5V - 11 16 nC
Threshold Gate Charge Qg(TH) VGS = 0 to 1V - 0.6 1.0 nC

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance, Junction to Ambient R

OSS
RSS

θJA

VDD = 30V, ID = 2A, RL = 15Ω, VGS = 5V,
RG = 25Ω (Figures 12, 13, 14)

r

f

= 0 to 10V VDD = 48V, ID = 2A,

I

G(REF)

RL = 24Ω
(Figures 12, 15, 16)

VDS = 25V, VGS = 0V, f = 1MHz

ISS

(Figure 11)

- - 100 ns

-13- ns

-42- ns

-95- ns

-45- ns

- 200 ns

-2030nC

=0.5mA,

- 535 - pF

- 175 - pF

-32-pF

- - 115oC/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) V

SD

Reverse Recovery Time t

NOTES:

2. Pulse test: width ≤ 300µs duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by maximum junction temperature.

6-284

ISD = 2A - - 1.2 V
ISD = 2A, dlSD/dt = 100A/µs - - 200 ns

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