Intersil RFG40N10LE, RFP40N10LE Datasheet

RFG40N10LE, RFP40N10LE, RF1S40N10LESM

Data Sheet October 1999 File Number 4061.5

40A, 100V, 0.040 Ohm, Logic Level
N-Channel Power MOSFETs

These N-Channel enhancement mode power MOSFETs are
manufactured using the latest manufacturing process
technology. This process, which uses feature sizes
approaching those of LSI integrated circuits gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switchingregulators,switching converters, motor drivers and
relaydrivers.These transistorscan be operated directly from
integrated circuits.

Formerly developmental type TA49163.

Ordering Information

PART NUMBER PACKAGE BRAND

RFG40N10LE TO-247 FG40N10L
RFP40N10LE TO-220AB FP40N10L
RF1S40N10LESM TO-263AB F40N10LE

NOTE: When ordering, use the entire partnumber.Addthe suffix, 9A, to
obtain the TO-263AB variant in tape and reel, i.e. RF1S40N10LESM9A.

Features

• 40A, 100V

•r

DS(ON)

• Temperature Compensating PSPICE

= 0.040Ω

®

Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

C Operating Temperature

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

S

Packaging

DRAIN

(FLANGE)

JEDEC STYLE TO-247 JEDEC TO-220AB

SOURCE

DRAIN

GATE

DRAIN (FLANGE)

JEDEC TO-263AB

DRAIN

GATE

SOURCE

(FLANGE)

SOURCE

DRAIN

GATE

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFG40N10LE, RFP40N10LE, RF1S40N10LESM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFG40N10LE, RFP40N10LE,

RF1S40N10LESM UNITS

Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E

Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DSS

DGR

GS

DM

AS

D

Refer to Peak Current Curve

D

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

100 V
100 V
±10 V

40

Refer to UIS Curve

150

1.00

-55 to 175

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)VGS

Gate Charge at 5V Q
Threshold Gate Charge Q

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction-to-Case R
Thermal Resistance Junction-to-Ambient R

DSSID

DSS

GSS

ON

r

f

OFF

g(5)

g(TH)

ISS
OSS
RSS

θJC

θJA

= 250µA, VGS = 0V (Figure 13) 100 - - V

= VDS, ID = 250µA (Figure 12) 1 - 3 V

VDS = 95V, VGS = 0V - - 1 µA

= 90V, VGS = 0V, TC = 150oC - - 250 µA

V

DS

VGS = ±10V - - 10 µA

= 40A, VGS = 5V - - 0.040 Ω

VDD = 50V, ID = 40A, RL = 1.25Ω,
VGS = 5V, RGS = 2.5Ω
(Figures 10, 18, 19)

- - 200 ns

-22-ns

- 140 - ns

-70-ns

-65-ns

- - 165 ns

= 0V to 10V VDD = 80V,
VGS = 0V to 5V - 85 105 nC
VGS = 0V to 1V - 3 4 nC

ID = 40A,
RL = 2.0Ω
(Figures 20, 21)

VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 14)

- 145 180 nC

- 3000 - pF

- 500 - pF

- 200 - pF
All Packages - - 1.0
TO-247 - - 30
TO-220AB and TO-263AB - - 80

o
o
o

C/W
C/W
C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V

SD

Diode Reverse Recovery Time t

NOTES:

2. Pulse test: pulse width ≤ 80µs, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).

2

ISD = 40A - - 1.5 V
ISD = 40A, dISD/dt = 100A/µs - - 205 ns

rr

RFG40N10LE, RFP40N10LE, RF1S40N10LESM

Typical Performance Curves Unless Otherwise Specified

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

125

150

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWERDISSIPATION vs CASE

TEMPERATURE

2

1

0.5

0.2

0.1

THERMAL IMPEDANCE

0.01
10

0.1

0.05

0.02

0.01

-5

SINGLE PULSE

10

-4

-3

10

t, RECTANGULAR PULSE DURATION (s)

, NORMALIZED

θJC

Z

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

25 50 75 100 125 150

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

P

DM

t

1

t

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-2

10

-1

10

2

1/t2

x R

θJC

0

10

θJC

+ T

175

C

1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

500

100

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

1

1 10 100

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

TC = 25oC

T

= 175oC

J

100µs

1ms

10ms

200

500

100

THERMAL IMPEDANCE
MAY LIMIT CURRENT
IN THIS REGION

, PEAK CURRENT CAPABILITY (A)

DM

I

10

-5

10

TC = 25oC

-4

10

VGS = 10V
VGS = 5V

-3

10

t, PULSE WIDTH (s)

FOR TEMPERATURES
ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

175 T



II

=

-----------------------



25



-2

10

-1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

3

150

–

C

0

10

1

10

RFG40N10LE, RFP40N10LE, RF1S40N10LESM

Typical Performance Curves Unless Otherwise Specified (Continued)

500

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

100

10

, AVALANCHE CURRENT (A)

AS

I

1

0.001 0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)

STARTING TJ = 150oC

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

80

VDD= 15V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

60

40

20

, DRAIN TO SOURCE CURRENT (A)

DS(ON)

I

0

0 3.0 4.5 6.01.5

VGS, GATE TO SOURCE VOLTAGE (V)

-55oC

25oC

175oC

80

60

40

, DRAIN CURRENT (A)

20

D

I

0

0 1.5 3.0 4.5 6.0

VDS, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T

C

V
V

VGS = 4V

= 25oC

GS
GS

= 10V
= 5V

VGS = 2.5V

FIGURE 7. SATURATION CHARACTERISTICS

100

75

50

, DRAIN TO SOURCE

25

ON RESISTANCE (mΩ)

DS(ON)

r

0

ID = 10A

ID = 20A

PULSE DURATION = 80µs, VDD= 15V
DUTY CYCLE = 0.5% MAX.

2.0

3.0

, GATE TO SOURCE VOLTAGE (V)

V

GS

ID = 40A

3.5 4.5 5.0

ID = 80A

4.02.5

VGS = 3V

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

700

VDD = 50V, ID = 40A, RL= 1.25Ω

600

500

400

300

200

SWITCHING TIME (ns)

100

0

10

RGS, GATE TO SOURCE RESISTANCE (Ω)

t

d(OFF)

t

r

t

f

t

d(ON)

20 30 40 500

2.50
PULSE DURATION = 80µs,
DUTY CYCLE = 0.5% MAX.

2.00

1.50

1.00

ON RESISTANCE

0.50

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160

ID = 40AVGS = 5V,

TJ, JUNCTION TEMPERATURE (oC)

FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

4

200

RFG40N10LE, RFP40N10LE, RF1S40N10LESM

Typical Performance Curves Unless Otherwise Specified (Continued)

1.50
VGS = VDS,

1.25

1.00

NORMALIZED GATE

0.75

THRESHOLD VOLTAGE

0.50

-80 -40 0 40 80 120 160

= 250µA

I

D

TJ, JUNCTION TEMPERATURE (oC)

200

FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

3500

C

C
C

ISS

OSS

RSS

2800

VGS = 0V, f = 1MHz

= CGS + C

C

2100

1400

C, CAPACITANCE (pF)

700

0

0 5 10 15 20 25

VDS, DRAIN TO SOURCE VOLTAGE (V)

C
C

ISS
RSS
OSS

= C

≈ CDS + C

GD

GD

GD

FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

1.50
ID = 250µA

1.25

1.00

0.75

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.50

-80

-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)

160

FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

100

75

50

25

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

V

= BV

DD

I

GREF()

--------------------- -

20

I

G ACT()

DSS

RL = 2.5Ω
I

= 1.7mA

G(REF)

V

= 5V

GS

PLATEAU VOLTAGES IN
DESCENDING ORDER:

= BV

V

DD

VDD = 0.75 BV
VDD = 0.50 BV
VDD = 0.25 BV

DSS

DSS
DSS
DSS

t, TIME (µs)

VDD = BV

I

GREF()

--------------------- -

80

I

G ACT()

5.00

DSS

3.75

2.50

1.25

0

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE15. SWITCHING WAVEFORMSFORCONSTANTGATE

CURRENT

200

, GATE TO SOURCE VOLTAGE (V)

GS

V

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

t

0V

P

AS

R

G

DUT

I

AS

0.01Ω

+

V

DD

-

0

FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS

5

t

P

I

AS

t

AV

V

DS

V

DD

RFG40N10LE, RFP40N10LE, RF1S40N10LESM

Test Circuits and Waveforms (Continued)

t

ON

t

DS

GS

10%

d(ON)

90%

50%

10%

t

r

PULSE WIDTH

V

DS

V

R

DUT

L

+

V

DD

-

0

V

0

V

GS

R

GS

V

GS

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

V

I

g(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

VGS= 2V

0

Q

g(TOT)

V

DS

Q

OR Q

g(10)

V

GS

VGS= 1V FOR

g(5)

V

GS

VGS= 5V FOR

2

L

DEVICES

L2 DEVICES

Q

g(TH)

t

d(OFF)

90%

= 10V

t

OFF

t

f

10%

50%

VGS= 20V

V

= 10V FOR

GS

L2 DEVICES

90%

I

g(REF)

0

FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS

6

RFG40N10LE, RFP40N10LE, RF1S40N10LESM

PSPICE Electrical Model

SUBCKT 40N10LE 2 1 3 ; rev 8/15/95

CA 12 8 3.50e-9
CB 15 14 3.50e-9
CIN 6 8 1.70e-9

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 120.7
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

IT 8 17 1
LDRAIN 2 5 1.00e-9

LGATE 1 9 5.17e-9
LSOURCE 3 7 2.13e-9

GATE

1

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.04e-2
RGATE 9 20 2.15
RLDRAIN 2 5 10
RLGATE 1 9 51.7
RLSOURCE 3 7 21.3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 4.85e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD

LGATE

RLGATE

RGATE

9

CA

ESG

EVTEMP
+

18
22

20

S1A

12

13

8

S1B

EGS EDS

DPLCAP

10

RSLC2

-

6
8

EVTHRES

+

+

6

-

S2A

14
13

S2B

13

+

+

6
8

-

-

5

RSLC1

51

+

5

ESLC

51

-

50
RDRAIN

16

21

-

19

8

MMED

MSTRO

CIN

15

CB

8

14

+

5
8

-

DBREAK

11

+

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

17
18

-

7

-

+

22

S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*79),3.5))}
.MODEL DBODYMOD D (IS = 1.96e-12 RS = 3.87e-3 TRS1 = 9.93e-4 TRS2 = 4.97e-6 CJO = 1.53e-9 TT = 7.41e-8 M = 0.50)

.MODEL DBREAKMOD D (RS = 3.12e-1 TRS1 = 1.07e-3 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 1.97e-9 IS = 1e-30 M = 0.87)
.MODEL MMEDMOD NMOS (VTO = 1.73 KP = 2.80 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.15)
.MODEL MSTROMOD NMOS (VTO = 2.04 KP = 80 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.50 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 21.5 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.74e-4 TC2 = -3.71e-7)
.MODEL RDRAINMOD RES (TC1 = 9.71e-3 TC2 = 2.90e-5)
.MODEL RSLCMOD RES (TC1 = 2.17e-3 TC2 = 1.27e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.08e-3 TC2 = -6.82e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.52e-3 TC2 = -1.21e-7)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.00 VOFF= -1.50)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.50 VOFF= -6.00)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.50 VOFF= 0.0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.0 VOFF= -0.50)

.ENDS

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

RVTEMP
19

VBAT

DRAIN

2

SOURCE

3

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

7

RFG40N10LE, RFP40N10LE, RF1S40N10LESM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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8

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