Intersil RFL1N10L, RFL1N08L Datasheet

1

Features

• 1A, 100V

•r

DS(ON)

= 1.200Ω

Description

This is an N-Channel enhancement mode silicon gate power
field effect transistor specifically designed for use with logic
level (5V) driving sources in applications such as program­mable controllers, automotive switching, and solenoid driv­ers. This performance is accomplished through a special
gate oxide design which provides full rated conduction at
gate biases in the 3V to 5V range, thereby facilitating true
on-off power control directly from logic circuit supply volt­ages.

Formerly developmental type TA09524.

Symbol

Packaging

JEDEC TO-205AF

Ordering Information

PART NUMBER PACKAGE BRAND

RFL1N10L TO-205AF RFL1N10L

NOTE: When ordering, use the entire part number.

G

D

S

DRAIN
(CASE)

SOURCE

GATE

September 1998

File Number

1510.3

RFL1N10L

1A, 100V, 1.200 Ohm, Logic Level, N-Channel

Power MOSFET

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

2

Absolute Maximum Ratings T

C

= 25oC, Unless Otherwise Specified

RFL1N10L UNITS

Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DS

100 V

Drain to Gate Voltage (RGS = 1MΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . .V

DGR

100 V

Continuous Drain Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

D

1A

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

DM

5A

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

GS

±10 V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

D

8.33 W

Above TC = 25oC, Derate Linearly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.0667 W/oC

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

-55 to 150

o

C

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . .T

L

260

o

C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. TJ= 25oC to 125oC.

Electrical Specifications T

C

= 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV

DSS

ID = 250µA, VGS = 0 100 - - V

Gate Threshold Voltage V

GS(TH)

VGS = VDS, ID = 250µA1-2V

Zero Gate Voltage Drain Current I

DSS

VDS = Rated BV

DSS

--1µA

VDS = 0.8 x Rated BV

DSS

, VDS = 80V,

TC = 125oC

--25µA

Gate to Source Leakage Current I

GSS

VGS = ±10V, VDS = 0 - - ±100 nA

Drain to Source On Resistance (Note 2) r

DS(ON)

ID = 1A, VGS = 5V (Figures 6, 7) - - 1.200 Ω

Drain to Source On Voltage (Note 2) V

DS(ON)

ID = 1A, VGS = 5V - - 1.2 V

Turn-On Delay Time t

d(ON)

I

D

≈ 1A, V

DD

= 50V, RG= 6.25Ω,
VGS = 5V, RL= 50Ω
(Figures 10, 11, 12)

-1025ns

Rise Time t

r

-1545ns

Turn-Off Delay Time t

d(OFF)

-2545ns

Fall Time t

f

-3050ns

Input Capacitance C

ISS

VGS = 0V, VDS = 25V, f = 1MHz
(Figure 9)

- - 200 pF

Output Capacitance C

OSS

- - 80 pF

Reverse Transfer Capacitance C

RSS

- - 35 pF

Thermal Resistance Junction to Case R

θ

JC

--15oC/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) V

SD

ISD = 1A - - 1.4 V

Diode Reverse Recovery Time t

rr

ISD = 2A, dISD/dt = 50A/µs - 100 - ns

NOTES:

2. Pulse test: width ≤ 300µs duty cycle ≤ 2%.

3. Repetitive rating: pulse witdh limited by maximum junction temperature.

RFL1N10L

3

Typical Performance Curves

Unless Otherwise Specified

FIGURE 1. NORMALIZED POWER DISSIP ATION vs CASE

TEMPERA TURE

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. SATURATION CHARACTERISTICS

FIGURE 5. TRANSFER CHARACTERISTICS FIGURE 6. DRAIN TO SOURCE ON RESISTANCE vs DRAIN

CURRENT

1.2

1.0

0.8

0.6

0.4

0.2

0

0 25 50 75 100 125 150

T

C

, CASE TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

1.2

0.8

0.4

0

25 50 75 100 125 150

T

C

, CASE TEMPERATURE (oC)

I

D

, DRAIN CURRENT (A)

0.6

0.2

1.0

10

1

0.1

0.01
1 10 100 1000

I

D

, DRAIN CURRENT (A)

OPERATION IN THIS AREA
MAY BE LIMITED BY r

DS(ON)

VDS, DRAIN TO SOURCE (V)

TC = 25oC

3

2

1

0 345678 10

I

DS,

DRAIN TO SOURCE CURRENT (A)

V

DS,

DRAIN TO SOURCE VOLTAGE (V)

VGS = 3V

V

GS

= 2V

4

PULSE DURATION = 80µs
DUTY CYCLE ≤ 2%
T

C

= 25oC

VGS = 5V

VGS = 10V

921

VGS = 4V

0

5

6

8

7

I

D(ON),

DRAIN CURRENT (A)

3

2

1

0

1234

6

V

GS,

GATE TO SOURCE VOLTAGE (V)

4

5

-40oC

125oC

-40oC

25oC

125oC

6

5

VDS= 10V

DUTY CYCLE ≤ 2%

PULSE DURATION = 80µs

125oC

25

o

C

-40

o

C

VGS = 5V
PULSE DURATION = 80µs
DUTY CYCLE ≤ 2%

r

DS(ON),

DRAIN TO SOURCE ON

ID,DRAIN CURRENT (A)

2

1

0

012345

RESISTANCE (Ω)

6

0.5

1.5

7

RFL1N10L

4

FIGURE 7. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

FIGURE 8. NORMALIZED GATE THRESHOLD V OLTAGE vs

JUNCTION TEMPERATURE

FIGURE 9. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 10. NORMALIZED SWITCHING WA VEFORMS FOR

CONSTANT GATE CURRENT

Typical Performance Curves

Unless Otherwise Specified (Continued)

1.5

1

0.5

-50 0 50 100 150
TJ,JUNCTION TEMPERATURE (oC)

VGS = 5V

I

D

= 1A

NORMALIZED DRAIN TO SOURCE

2

ON RESISTANCE

2.5

1.5

1

0.5

-50 0 50 100 150
T

J,

JUNCTION TEMPERATURE (oC)

ID = 250µA

V

GS=VDS

NORMALIZED GATE

THRESHOLD VOLTAGE

2

0102030405060

C, CAPACITANCE (pF)

V

DS,

DRAIN TO SOURCE VOLTAGE (V)

240

200

160

120

80

40

f = 1MHz

C

OSS

C

ISS

C

RSS

0.75V

DSS

0.75V

DSS

0.50V

DSS

0.50V

DSS

0.25V

DSS

0.25V

DSS

GATE

SOURCE

VOLTAGE

V

DD

= V

DSS

VDD= V

DSS

BV

DSS

I

G(REF)

I

G(ACT)

20 80

DRAIN SOURCE VOLT AGE

I

G(REF)

I

G(ACT)

RL = 50
I

G(REF)

= 0.094mA

VGS = 5V

V

DS

, DRAIN TO SOURCE VOLTAGE (V)

t, TIME (µs)

V

GS

, GATE TO SOURCE VOLTAGE (V)

100

75

50

25

0

10

8

6

4

0

2

Test Circuits and Waveforms

FIGURE 11. SWITCHING TIME TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS

V

GS

R

L

R

G

DUT

+

-

V

DD

t

ON

t

d(ON)

t

r

90%

10%

V

DS

90%

10%

t

f

t

d(OFF)

t

OFF

90%

50%

50%

10%

PULSE WIDTH

V

GS

0

0

RFL1N10L

5

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

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RFL1N10L