Datasheet JANSR2N7407 Datasheet (Intersil)

JANSR2N7407
Data Sheet December 1998 File Number
Formerly Available As FSF254R4, Radiation Hardened, SEGR Resistant, N-Channel Power MOSFETs
The Discrete Products Operation of Intersil has developeda series of Radiation Hardened MOSFETs specifically designed for commercial and military space applications. Enhanced Power MOSFET immunity toSingleEvent Effects (SEE), Single Event Gate Rupture (SEGR) in particular, is combined with 100K RADS of total dose hardness to provide devices which are ideally suited to harsh space environments. The dose rate and neutron tolerance necessary for military applications have not been sacrificed.
The Intersil portfolio of SEGR resistant radiation hardened MOSFETs includes N-Channel and P-Channel devices in a variety of voltage, current and on-resistance ratings. Numerous packaging options are also available.
This MOSFET is an enhancement-mode silicon-gate power field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and drivers for high-power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits.
Features
• 18A, 250V, r
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 36MeV/mg/cm to 80% of Rated Breakdown and V
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
- Typically Survives 2E12 if Current Limited to I
• Photo Current
- 15nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications for 1E13 Neutrons/cm
• Usable to 1E14 Neutrons/cm
DS(ON)
= 0.170
2
2
with VDS up
of 10V Off-Bias
GS
2
Symbol
4636
DSS
DM
Also availableat other radiation and screening levels.See us on the web, Intersil’ home page:www.semi.intersil.com. Contact your local Intersil Sales Office for additional information.
Ordering Information
PART NUMBER PACKAGE BRAND
JANSR2N7407 TO-254AA JANSR2N7407
Die Family TA17658. MIL-PRF-19500/634.
Packaging
CAUTION: Beryllia Warning per MIL-S-19500
TO-254AA
G
S
D
refer to package specifications.
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
JANSR2N7407
Absolute Maximum Ratings T
= 25oC, Unless Otherwise Specified
C
JANSR2N7407 UNITS
Drain to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Drain to Gate Voltage (RGS = 20k). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DS
DGR
250 V 250 V
Continuous Drain Current
TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
D D
DM
GS
18 A 12 A 54 A
±20 V
Maximum Power Dissipation
TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T T
125 W
50 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.00 W/oC
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . .I
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Operating and Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T
STG
Lead Temperature (During Soldering). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
AS
S
SM
L
54 A 18 A 54 A
-55 to 150 300
o
C
o
C
(Distance >0.063in (1.6mm) from Case, 10s Max)
Weight (Typical). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
9.3
g
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV Gate Threshold Voltage V
DSSID
GS(TH)VGS
= 1mA, VGS = 0V 250 - - V
= VDS,
ID = 1mA
TC = -55oC - - 5.0 V TC = 25oC 1.5 - 4.0 V TC = 125oC 0.5 - - V
Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I
DSS
GSS
VDS = 200V, VGS = 0V
TC = 25oC--25µA TC = 125oC - - 250 µA
VGS = ±20V TC = 25oC - - 100 nA
TC = 125oC - - 200 nA Drain to Source On-State Voltage V Drain to Source On Resistance r
Turn-On Delay Time t
DS(ON)VGS
DS(ON)12ID
d(ON)
Rise Time t Turn-Off Delay Time t
d(OFF)
Fall Time t Total Gate Charge (Not on slash sheet) Q
g(TOT)VGS
Gate Charge at 12V Q Threshold Gate Charge (Not on slash sheet) Q Gate Charge Source Q Gate Charge Drain Q Thermal Resistance Junction to Case R Thermal Resistance Junction to Ambient R
r
f
g(12)
g(TH)
gs
gd
JC
θ
JA
θ
= 12V, ID = 18A - - 3.21 V
= 12A,
VGS = 12V
VDD = 125V, ID = 18A, RL = 6.94, VGS = 12V, RGS = 2.35
TC = 25oC - 0.120 0.170
TC = 125oC - - 0.306
- - 130 ns
- - 160 ns
- - 160 ns
- - 65 ns
= 0V to 20V VDD = 125V,
VGS = 0V to 12V - 120 150 nC
ID = 18A
- - 230 nC
VGS = 0V to 2V - - 7.6 nC
-2228nC
-5671nC
- - 1.00
o
C/W
--48oC/W
4-2
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Forward Voltage V Reverse Recovery Time t
SD
rr
JANSR2N7407
ISD = 18A 0.6 - 1.8 V ISD = 18A, dISD/dt = 100A/µs - - 690 ns
Electrical Specifications up to 100K RAD T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS
Drain to Source Breakdown Volts (Note 3) BV Gate to Source Threshold Volts (Note 3) V Gate to Body Leakage (Notes 2, 3) I Zero Gate Leakage (Note 3) I Drain to Source On-State Volts (Notes 1, 3) V Drain to Source On Resistance (Notes 1, 3) r
DS(ON)12VGS
DSS
GS(TH)VGS
GSS DSS
DS(ON)VGS
VGS = 0, ID = 1mA 250 - V
= VDS, ID = 1mA 1.5 4.0 V VGS = ±20V, VDS = 0V - 100 nA VGS = 0, VDS = 200V - 25 µA
= 12V, ID = 18A - 3.21 V
= 12V, ID = 12A - 0.170
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V, VDS = 80% BV
DSS
.
Single Event Effects (SEB, SEGR) Note 4
ENVIRONMENT (NOTE 5)
TEST SYMBOL
ION
SPECIES
TYPICAL LET
(MeV/mg/cm)
TYPICAL
RANGE (µ)
Single Event Effects Safe Operating Area SEESOA Ni 26 43 -20 250
Br 37 36 -5 250 Br 37 36 -10 200 Br 37 36 -15 125 Br 37 36 -20 50
NOTES:
4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.
5. Fluence = 1E5 ions/cm2 (typical), TC = 25oC.
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
APPLIED
V
BIAS
GS
(V)
(NOTE 6)
MAXIMUM
VDSBIAS (V)
Typical Performance Curves
LET = 26MeV/mg/cm
300
200
(V)
DS
V
100
0
0 -10 -15 -20 -25
LET = 37MeV/mg/cm2, RANGE = 36µ
FLUENCE = 1E5 IONS/cm2 (TYPICAL)
TEMP = 25oC
-5 (V)
V
GS
Unless Otherwise Specified
2
, RANGE = 43µ
LIMITING INDUCTANCE (HENRY)
1E-3
1E-4
1E-5
1E-6
1E-7
30
DRAIN SUPPLY (V)
ILM = 10A
30A
100A
300A
30010010
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT
GAMMA DOT CURRENT TO I
AS
4-3
1000
JANSR2N7407
Typical Performance Curves
24
20
16
12
, DRAIN (A)
D
I
8
4
0
-50 TC, CASE TEMPERATURE (oC)
500
Unless Otherwise Specified (Continued)
100
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
150
100
TC = 25oC
10
1
, DRAIN CURRENT (A) I
OPERATION IN THIS
D
AREA MAY BE LIMITED BY r
0.1 1 10 100
DS(ON)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
2.5
PULSE DURATION = 250µs, VGS = 12V, ID = 12A
2.0
100µs
1ms
10ms
100ms
700
12V
V
Q
GS
G
Q
G
Q
GD
CHARGE
DS(ON)
1.5
1.0
NORMALIZED r
0.5
0.0
-80 -40 0 40 80 120 160
FIGURE 5. BASIC GATE CHARGE WAVEFORM FIGURE 6. NORMALIZED r
10
)
1
θJC
NORMALIZED
THERMAL RESPONSE (Z
0.001
0.1
0.01
0.5
0.2
0.1
0.05
0.02
0.01 SINGLE PULSE
NOTES: DUTY FACTOR: D = t1/t
PEAK TJ = PDM x Z
-5
10
-4
10
-3
10
t, RECTANGULAR PULSE DURATION (s)
-2
10
T
, JUNCTION TEMPERATURE (oC)
J
vs JUNCTION TEMPERA TURE
DS(ON)
P
DM
2
+ T
θJC
C
-1
10
t t
0
10
1 2
1
10
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
4-4
JANSR2N7407
Typical Performance Curves
100
10
, AVALANCHE CURRENT (A)
AS
I
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I
V
DS
Unless Otherwise Specified (Continued)
STARTING TJ = +25oC
STARTING TJ = +150oC
IF R = 0
tAV = (L) (IAS) / (1.3 RATED BV
IF R 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BV
1
0.01
0.1 1 10
, TIME IN AVALANCHE (ms)
t
AV
DSS
- VDD)
DSS
- VDD) + 1]
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
IS REACHED
AS
L
BV
DSS
P
t
AV
VARY t
TO OBTAIN
P
REQUIRED PEAK I
VGS≤ 20V
t
0V
P
CURRENT
TRANSFORMER
50
AS
+
I
AS
-
+
V
DD
-
DUT
50
50V-150V
t
I
AS
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
t
t
d(ON)
90%
ON
10%
t
r
PULSE WIDTH
0V
VGS = 12V
V
DD
R
L
V
DS
DUT
R
GS
V
DS
V
GS
10%
V
DS
t
d(OFF)
90%
t
OFF
50%50%
V
t
f
10%
DD
90%
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
4-5
JANSR2N7407
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANS) T
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
= 25oC, Unless Otherwise Specified
C
Gate to Source Leakage Current I Zero Gate Voltage Drain Current I Drain to Source On Resistance r Gate Threshold Voltage V
NOTES:
7. Or 100% of Initial Reading (whichever is greater).
8. Of Initial Reading.
DS(ON)
GS(TH)
GSS
DSS
VGS = ±20V ±20 (Note 7) nA VDS = 80% Rated Value ±25 (Note 7) µA TC = 125oC at Rated I ID = 1.0mA ±20% (Note 8) V
D
±20% (Note 8)
Screening Information
TEST JANS
Gate Stress VGS = 30V, t = 250µs Pind Required Pre Burn-In Tests (Note 9) MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25oC)
Steady State Gate Bias (Gate Stress)
Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests and Limits Table Steady State Reverse
Bias (Drain Stress)
MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours
MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value,
TA = 150oC, Time = 240 hours PDA 5% Final Electrical Tests (Note 9) MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
9. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
Safe Operating Area SOA VDS = 200V, t = 10ms 1.35 A Unclamped Inductive Switching I Thermal Response V Thermal Impedance V
AS
SD
SD
V
GS(PEAK)
tH = 100ms; VH = 25V; IH = 4A 136 mV tH = 500ms; VH = 25V; IH = 4A 187 mV
= 15V, L = 0.1mH 54 A
4-6
JANSR2N7407
Rad Hard Data Packages - Intersil Power Transistors
1. JANS Rad Hard - Standard Data Package
A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data
F. Group A - Attributes Data Sheet G. Group B - Attributes Data Sheet H. Group C - Attributes Data Sheet
I. Group D - Attributes Data Sheet
2. JANS Rad Hard - Optional Data Package
A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data
- X-Ray and X-Ray Report
F. Group A - Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups A2, A3, A4, A5 and A7 Data
G. Group B - Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups B1, B3, B4, B5 and B6 Data
H. Group C - Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups C1, C2, C3 and C6 Data
I. Group D - Attributes Data Sheet
- Hi-Rel Lot Traveler
- Pre and Post Radiation Data
4-7
TO-254AA
3 LEAD JEDEC TO-254AA HERMETIC METAL PACKAGE
JANSR2N7407
A
A
1
J
1
SYMBOL
A 0.249 0.260 6.33 6.60 -
A
1
Øb 0.035 0.045 0.89 1.14 2, 3
D 0.790 0.800 20.07 20.32 ­E 0.535 0.545 13.59 13.84 -
e 0.150 TYP 3.81 TYP 4
e
1
H
1
J
1
L 0.520 0.560 13.21 14.22 -
ØP 0.139 0.149 3.54 3.78 -
Q 0.110 0.130 2.80 3.30 -
NOTES:
1. These dimensions are within allowabledimensions of Rev.A of JEDEC outline TO-254AA dated 11-86.
2. Add typically 0.002 inches (0.05mm) for solder coating.
3. Lead dimension (without solder).
4. Positionof leadtobe measured 0.250inches(6.35mm) frombottom of dimension D.
5. Die to base BeO isolated, terminals to case ceramic isolated.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
TYP.
b
Ø
ØP
H
1
E
Q
D
0.065 R MAX.
L
12 3
e
e
1
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
0.040 0.050 1.02 1.27 -
0.300 BSC 7.62 BSC 4
0.245 0.265 6.23 6.73 -
0.140 0.160 3.56 4.06 4
WARNING!
BERYLLIA WARNING PER MIL-S-19500
Packagescontaining beryllium oxide (BeO) shall not be ground, machined, sandblasted, or subject to any mechanical operation which will produce dust containing any beryllium compound. Packages containing any beryllium compound shall not be subjected to any chemical process (etching, etc.) which will produce fumes containing beryllium or its’ compounds.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly , the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240
EUROPE
Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
4-8
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