JANSR2N7400
Formerly FSS230R4
June 1998
Features
• 8A, 200V, r
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 36MeV/mg/cm
V
up to 80% of Rated Breakdown and
DS
V
of 10V Off-Bias
GS
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
- Typically Survives 2E12 if Current Limited to I
• Photo Current
- 3.0nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 1E13 Neutrons/cm
- Usable to 1E14 Neutrons/cm
Ordering Information
PART NUMBER PACKAGE BRAND
JANSR2N7400 TO-257AA JANSR2N7400
DS(ON)
= 0.440Ω
2
2
2
with
DSS
DM
8A, 200V, 0.440 Ohm, Rad Hard,
N-Channel Power MOSFET
Description
The Discrete Products Operation of Intersil Corporation has
developed a series of Radiation Hardened MOSFETs specifically designed for commercial and military space applications. Enhanced Power MOSFET immunity to Single Event
Effects (SEE), Single Event Gate Rupture (SEGR) in particular, is combined with 100K RADS of total dose hardness to
provide devices which are ideally suited to harsh space environments. The dose rate and neutron tolerance necessary
for military applications have not been sacrificed.
The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation
tolerant. The MOSFET is well suited for applications
exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and
drivers for high-power bipolar switching transistors requiring
high speed and low gate drive power. This type can be
operated directly from integrated circuits.
Also available at other r adiation and screening le v els . See us
on the web, Intersil’s home page: http://www.intersil.com.
Contact your local Intersil Sales Office for additional
information.
Die Family TA17637.
MIL-PRF-19500/632.
Symbol
Package
TO-257AA
S
D
G
CAUTION: Beryllia Warning per MIL-S-19500
refer to package specifications.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
2-58
File Number 4373.1
JANSR2N7400
Absolute Maximum Ratings T
= 25oC, Unless Otherwise Specified
C
JANSR2N7400 UNITS
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
DGR
200 V
200 V
Continuous Drain Current
TC = 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
TC = 100oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
D
D
DM
GS
8A
5A
24 A
±20 V
Maximum Power Dissipation
TC = 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
TC = 100oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
T
T
50 W
20 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.40 W/oC
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . I
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, T
STG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
AS
S
SM
L
24 A
8A
24 A
-55 to 150
300
o
C
o
C
(Distance >0.063in (1.6mm) from Case, 10s Max)
Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
4.4
g
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V
DSSID
GS(TH)VGS
= 1mA, VGS = 0V 200 - - V
= VDS,
ID = 1mA
TC = -55oC - - 5.0 V
TC = 25oC 1.5 - 4.0 V
TC = 125oC 0.5 - - V
Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I
DSS
GSS
VDS = 160V,
VGS = 0V
TC = 25oC--25µA
TC = 125oC - - 250 µA
VGS = ±20V TC = 25oC - - 100 nA
TC = 125oC - - 200 nA
Drain to Source On-State Voltage V
Drain to Source On Resistance r
Turn-On Delay Time t
DS(ON)VGS
DS(ON)12ID
d(ON)
Rise Time t
Turn-Off Delay Time t
d(OFF)
Fall Time t
Total Gate Charge (Not on Slash Sheet) Q
g(TOT)VGS
Gate Charge at 12V Q
Threshold Gate Charge (Not on Slash Sheet) Q
Gate Charge Source Q
Gate Charge Drain Q
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R
r
f
g(12)VGS
g(TH)VGS
gs
gd
JC
θ
JA
θ
= 12V, ID = 8A - - 3.70 V
= 5A,
VGS = 12V
VDD = 100V, ID = 8A,
RL = 12.5Ω, VGS = 12V,
RGS = 7.5Ω
TC = 25oC - 0.320 0.440 Ω
TC = 125oC - - 0.744 Ω
- - 65 ns
- - 160 ns
- - 120 ns
- - 90 ns
= 0V to 20V VDD = 100V,
= 0V to 12V - 33 42 nC
ID = 8A,
- - 64 nC
= 0V to 2V - - 3.1 nC
- 7.8 12 nC
-1722nC
- - 2.5
--60oC/W
o
C/W
2-59
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Forward Voltage V
Reverse Recovery Time t
SD
rr
JANSR2N7400
ISD = 8A 0.6 - 1.8 V
ISD = 8A, dISD/dt = 100A/µs - - 340 ns
Electrical Specifications up to 100K RAD T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS
Drain to Source Breakdown Volts (Note 3) BV
Gate to Source Threshold Volts (Note 3) V
GS(TH)
Gate to Body Leakage (Notes 2, 3) I
Zero Gate Leakage (Note 3) I
Drain to Source On-State Volts (Notes 1, 3) V
Drain to Source On Resistance (Notes 1, 3) r
DS(ON)
DS(ON)12VGS
DSS
GSS
DSS
VGS = 0, ID = 1mA 200 - V
VGS = VDS, ID = 1mA 1.5 4.0 V
VGS = ±20V, VDS = 0V - 100 nA
VGS = 0, VDS = 160V - 25 µA
VGS = 12V, ID = 8A - 3.70 V
= 12V, ID = 5A - 0.440 Ω
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V, VDS = 80% BV
DSS
.
Single Event Effects (SEB, SEGR) (Note 4)
ENVIRONMENT (NOTE 5)
APPLIED
VGS BIAS
TEST SYMBOL
Single Event Effects Safe Operating
Area
ION
SPECIES
SEESOA Ni 26 43 -20 200
Br 37 36 -5 200
TYPICAL LET
(MeV/mg/cm)
TYPICAL
RANGE (µ)
Br 37 36 -10 160
Br 37 36 -15 100
Br 37 36 -20 40
NOTES:
4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.
5. Fluence = 1E5 ions/cm2 (typical), T = 25oC.
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
(V)
(NOTE 6)
MAXIMUM
VDS BIAS
(V)
Typical Performance Curves
LET = 26MeV/mg/cm
240
200
160
(V)
120
DS
V
80
40
TEMP = 25oC
0
0 -10
LET = 37MeV/mg/cm2, RANGE = 36µ
FLUENCE = 1E5 IONS/cm2 (TYPICAL)
-5
(V)
V
GS
Unless Otherwise Specified
2
, RANGE = 43µ
-15
-20 -25
LIMITING INDUCTANCE (HENRY)
1E-3
1E-4
1E-5
1E-6
1E-7
30
DRAIN SUPPLY (V)
ILM = 10A
30A
100A
300A
30010010
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT
GAMMA DOT CURRENT TO I
AS
2-60
1000
JANSR2N7400
Typical Performance Curves
10
8
6
, DRAIN (A)
4
D
I
2
0
-50
0
TC, CASE TEMPERATURE (oC)
50
Unless Otherwise Specified (Continued)
100
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
150
50
10
1
, DRAIN CURRENT (A)
D
I
0.1
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
1
VDS, DRAIN TO SOURCE VOLTAGE (V)
DS(ON)
10 100
TC = 25oC
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
2.5
2.0
PULSE DURATION = 250ms, VGS = 12V, ID = 5A
100µs
1ms
10ms
100ms
600
12V
V
Q
GS
G
Q
Q
CHARGE
G
GD
DS(ON)
1.5
1.0
NORMALIZED r
0.5
0.0
-80 -40 0
FIGURE 5. BASIC GATE CHARGE WAVEFORM FIGURE 6. NORMALIZED r
10
)
JC
θ
1
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
NORMALIZED THERMAL RESPONSE (Z
0.001
-5
10
SINGLE PULSE
-4
10
-3
10
t, RECTANGULAR PULSE DURATION (s)
-2
10
T
, JUNCTION TEMPERATURE (oC)
J
DS(ON)
NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z
-1
10
40
80 120 160
vs JUNCTION TEMPERA TURE
P
DM
1/t2
+ T
JC
C
θ
t
1
t
2
0
10
1
10
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
2-61
JANSR2N7400
Typical Performance Curves
50
10
, AVALANCHE CURRENT (A)
AS
I
1
0.01 0.1 1 10
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
Test Circuits and Waveforms
Unless Otherwise Specified (Continued)
STARTING TJ = 25oC
STARTING TJ = 150oC
IF R = 0
tAV = (L) (IAS) /
(1.3 RATED BV
IF R ≠ 0
tAV = (L/R) ln [(IAS*R) /
(1.3 RATED BV
V
DS
- VDD)
DSS
- VDD) + 1]
DSS
, TIME IN AVALANCHE (ms)
t
AV
L
BV
t
DSS
AV
VARY t
TO OBTAIN
P
REQUIRED PEAK I
V
GS
t
0V
P
AS
R
G
DUT
I
AS
0.01Ω
+
V
DD
-
t
P
I
AS
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
t
t
d(ON)
90%
ON
10%
t
r
PULSE WIDTH
0V
VGS = 12V
V
DD
R
L
V
DS
DUT
R
GS
V
DS
V
GS
10%
V
DS
t
d(OFF)
90%
t
OFF
50%50%
V
t
f
10%
DD
90%
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
2-62
JANSR2N7400
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANS) T
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
= 25oC, Unless Otherwise Specified
C
Gate to Source Leakage Current I
Zero Gate Voltage Drain Current I
Drain to Source On Resistance r
Gate Threshold Voltage V
NOTES:
7. Or 100% of Initial Reading (whichever is greater).
8. Of Initial Reading.
GSS
DSS
DS(ON)
GS(TH)
VGS = ±20V ±20 (Note 7) nA
VDS = 80% Rated Value ±25 (Note 7) µA
TC = 25oC at Rated I
ID = 1.0mA ±20% (Note 8) V
D
±20% (Note 8) Ω
Screening Information
TEST JANS
Gate Stress VGS = 30V, t = 250µs
Pind Required
Pre Burn-In Tests (Note 9) MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25oC)
Steady State Gate
Bias (Gate Stress)
Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse
Bias (Drain Stress)
MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours
MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,
TA = 150oC, Time = 240 hours
PDA 5%
Final Electrical Tests (Note 9) MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
9. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
Safe Operating Area SOA VDS = 160V, t = 10ms 0.65 A
Unclamped Inductive Switching I
Thermal Response ∆V
Thermal Impedance ∆V
AS
SD
SD
V
GS(PEAK)
tH = 10ms; VH = 25V; IH = 1A 90 mV
tH = 500ms; VH = 25V; IH = 1A 125 mV
= 15V, L = 0.1mH 24 A
2-63
JANSR2N7400
Rad Hard Data Packages - Intersil Power Transistors
1. JANS Rad Hard - Standard Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning
F. Group A - Attributes Data Sheet
G. Group B - Attributes Data Sheet
H. Group C - Attributes Data Sheet
I. Group D - Attributes Data Sheet
2. JANS Rad Hard - Optional Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
F. Group A - Attributes Data Sheet
G. Group B - Attributes Data Sheet
H. Group C - Attributes Data Sheet
I. Group D - Attributes Data Sheet
Attributes Data Sheet
Hi-Rel Lot Traveler
HTRB - Hi Temp Gate Stress Post Reverse
Bias Data and Delta Data
HTRB - Hi T emp Drain Stress Post Reverse
Bias Delta Data
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
- X-Ray and X-Ray Report
- Hi-Rel Lot Traveler
- Subgroups A2, A3, A4, A5 and A7 Data
- Hi-Rel Lot Traveler
- Subgroups B1, B3, B4, B5 and B6 Data
- Hi-Rel Lot Traveler
- Subgroups C1, C2, C3 and C6 Data
- Hi-Rel Lot Traveler
- Pre and Post Radiation Data
2-64
JANSR2N7400
TO-257AA
3 LEAD JEDEC TO-257AA HERMETIC METAL PACKAGE
E
Q
ØP
H
1
A
A
1
SYMBOL
A 0.190 0.200 4.83 5.08 -
A
1
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
0.035 0.045 0.89 1.14 -
Øb 0.025 0.035 0.64 0.88 2, 3
D
Øb
0.060 0.090 1.53 2.28 -
1
D 0.645 0.665 16.39 16.89 E 0.410 0.420 10.42 10.66 e 0.100 TYP 2.54 TYP 4
L
1
L
0.065 R TYP.
Øb
1
b
123
e
e
1
J
1
e
1
H
1
J
1
L 0.600 0.650 15.24 16.51 -
L
1
ØP 0.140 0.150 3.56 3.81 -
Q 0.113 0.133 2.88 3.37 -
NOTES:
0.200 BSC 5.08 BSC 4
0.230 0.250 5.85 6.35 -
0.110 0.130 2.80 3.30 4
- 0.035 - 0.88 -
1. These dimensions are within allowable dimensions of Rev . B of
JEDEC TO-257AA dated 9-88.
2. Add typically 0.002 inches (0.05mm) for solder coating.
3. Lead dimension (without solder).
4. Position of lead to be measured 0.150 inches (3.81mm) from bottom
of dimension D.
5. Die to base BeO isolated, terminals to case ceramic isolated.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
WARNING!
BERYLLIA WARNING PER MIL-S-19500
Packages containing beryllium oxide (BeO) shall not be ground, machined, sandblasted, or subject to any mechanical
operation which will produce dust containing any beryllium compound. Packages containing any beryllium compound
shall not be subjected to any chemical process (etching, etc.) which will produce fumes containing beryllium or its’
compounds.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
2-65
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