intersil ISL97635 DATA SHEET

®

ISL97635

Data Sheet December 22, 2008

SMBus 8-Channel LED Driver

The ISL97635 is a digitally controlled LED driver that
controls 8 channels of LED current for LCD backlight
applications. The ISL97635 is capable of driving typically 72
(8x9) pieces of 3.5V/30mA or 80 (8x10) pieces of

3.2V/20mA LEDs. The ISL97635’s 8 channels of voltage
controlled current sources with typical currents matching of
±1%, which compensate for the non-uniformity effect of
forward voltages variance in the LED stacks. T o minimize the
voltage headroom and power loss in the typical multi-strings
operation, the ISL97635 features a dynamic headroom
control that monitors the highest LED forward voltage string
and uses its feedback signal for output regulation.

The LED dimming control can be achieved through a
SMBus, an external PWM, or a variable DC (analog light
sensor) input. SMBus controlled dimming allows 256 levels
each of PWM and DC current adjustments. The SMBus
PWM dimming frequency can be adjusted from 100Hz to
5kHz by an external capacitor. External PWM input allows up
to 20kHz audio noise free PWM dimming. The SMBus PWM
setting and an external PWMI signal can also be combined
to provide a dynamic PWM dimming that complies with
Intel’s DPST (Display Power Saving Technology)
requirement.

One or more channels can be selected sequentially in any
order, allowing scrolling in RGB LED backlighting
applications.

The ISL97635 features extensi v e protection functions that
include string open and short circuit detections, OVP, OTP,
thermal shutdown and an optional input overcurrent
protection with master fault disconnect switch. The fault
conditions will be recorded in the Fault/Status register. There
are selectable short-circuit thresholds and the switching
frequency can be programmed between 600kHz and

1.2MHz.
Available in the 24 Ld 4mmx4mm QFN, the ISL97635

operates from -40°C to +85°C with input voltage ranging
from 6V to 24V.

FN6434.2

Features

• 8 Channels

• 6V to 24V Input

• 34.5V Output Max

• Drive Maximally 72 (3.5V/30mA each) or 80 (3.2V/20mA
each) LEDs

• Current Matching ±1% Typ

• Dynamic Headroom Control

• Dimming Controls

- SMBus 8-Bit PWM Current Control

- SMBus 8-Bit DC Current Control

- External PWM Input up to 20kHz Dimming

- SMBus and External PWM DPST Dimming Control

- DC-to-PWM Dimming Control

• Protections

- String Open Circuit Detection

- String Short Circuit Detection with Select able Thresho lds

- Over-Temperature Protection

- Overvoltage Protection

- Input Overcurrent Protection with Disconnect Switch

• 600kHz/1.2MHz Selectable f

SW

• Selectable Channels Allows Scrolling Backlight

• 24 Ld (4mmx4mm) QFN Package

• Pb-Free (RoHS compliant)

Applications

• Notebook Displays WLED or RGB LED Backlighting

• LCD Monitor LED Backlighting

• Automotive Displays LED Backlighting

• Automotive or Traffic Lighting

Ordering Information

PART NUMBER

(Note)

ISL97635IRZ* 976 35IRZ 24 Ld 4x4 QFN L24.4x4D
*Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for

details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

PACKAGE

(Pb-free)

PKG.

DWG. #

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2008. All Rights Reserved

Typical Application Circuit

VBL+ = 6V TO 24V

21

23
24

ISL97635

FAULT

VIN
VDC

LX
LX

OVP
PGND
PGND 18

ISL97635

V

OUT

19
20
16
17

= 34.5V, 30mA PER STRING

22

1
2

6
4

11

3
5

COMP

SMBCLK
SMBDAT
PWMI/EN

PWMO
RSET

FPWM
GND

IIN0
IIN1
IIN2
IIN3
IIN4
IIN5
IIN6
IIN7

15
14
13
12
10

9
8
7

2

FN6434.2

December 22, 2008

Block Diagram

VBL+ = 6V TO 24V

ISL97635

34.5V, 30mA PER STRING

(8x9 = 72 WHITE LEDS)

SMBCLK
SMBDAT

PWMI

PWMO

VDC

f

PWM

COMP

RSET

GND

VIN

VIN

REG

OSC AND

RAMP

COMP

LED PWM

CONTROL

SMBUS

INTERFACE

FAULT

FAULT/STATUS

REGISTER

Σ = 0

IMAX

GM

AMP

REFERENCE
GENERAT OR

+

+

-

-

REGISTERS

PWM BRIGHTNESS CONTROL

DEVICE CONTROL

FAULT/STATUS

IDENTIFICATION

DC BRIGHTNESS CONTROL

CONFIGURATION

ILIMIT

LOGIC

HIGHEST VF

STRING

DETECT

+

+

-

-

PWM/OC/SC

AM

ISL97635

FET

DRIVER

OC, SC

DETECT

OC, SC

DETECT

FAULT/STATUS

REGISTER

+

+

-

-

LX

LX

OVP

IIN0

IIN0

IIN7

TEMP

SENSOR

FAUL T/STATUS

REGISTER

PGND

FIGURE 1. ISL97635 BLOCK DIAGRAM

3

FN6434.2

December 22, 2008

ISL97635

Absolute Maximum Ratings (T

VIN, FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 24V

VDC, COMP, RSET . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V

SMBCLK, SMBDAT, FPWM, PWMO, EN/PWM . . . . . -0.3V to 6.5V

OVP, IIN0 - IIN7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 28V

LX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 36V

PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V

Above voltage ratings are all with respect to GND pin

= +25°C) Thermal Information

A

Thermal Resistance (Typical, Notes 1, 2) θ

24 Ld QFN . . . . . . . . . . . . . . . . . . . . . . 39 2

Thermal Characterization (Typical, Note 3) PSI

24 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~0.7

Maximum Continuous Junction Temperature . . . . . . . . . . . . +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below

(°C/W) θJC (°C/W)

JA

(°C/W)

JT

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See T ech

1. θ

JA

Brief TB379.

2. For θ

3. PSI

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the

JT

die junction temperature can be estimated more accurately than the θ

4. Limits established by characterization and are not production tested.

Electrical Specifications All specifications below are tested at T

unless otherwise noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested.

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

GENERAL

V

IN

I

VIN_STBY

V

OUT

V

UVLO

V

UVLO_HYS

REGULATOR

V

DC

I

VDC_STBY

I

VDC

V

LDO

SS Soft-Start 1ms
ENmin Minimum Enable Signal 40 µs

BOOST

SWILimit Boost FET Current Limit T

r

DS(ON)

Backlight Supply Voltage ≤ 9 LEDs per channel

VIN Shutdown Current 5µA
Output Voltage 34.5 V
Undervoltage Lockout Threshold 2.45 2.8 V
Undervoltage Lockout Hysteresis 300 mV

LDO Output Voltage VIN > 6V 5.0 5.5 V
Standby Current EN/PWM = 0V 20 µA
Active Current EN/PWM = 5V 10 mA
VDC LDO Dropout Voltage VIN > 5.5V, 30mA 30 200 mV

Internal Boost Switch ON-Resistance 130 260 mΩ

= TC = T

J

A

and θJC thermal resistance ratings.

JC

= -40°C to +85°C; VIN = 12V, EN = 5V, R

A

= 36.6kΩ,

SET

624V

(3.5V/30mA type)

= +25°C 2.3 3.2 A

A

= -40°C to +85°C 2.2 A

T

A

4

FN6434.2

December 22, 2008

ISL97635

Electrical Specifications All specifications below are tested at T

unless otherwise noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise

= -40°C to +85°C; VIN = 12V, EN = 5V, R

A

= 36.6kΩ,

SET

specified. Temperature limits established by characterization and are not production tested. (Continued)

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

Eff_peak Peak Efficiency VIN = 18V, 54 LEDs, 20mA

91 %
each, L = 8.2µH with DCR
106mΩ, T

VIN = 12V, 54 LEDs, 20mA

= +25°C

A

88 %
each, L = 8.2µH with DCR
106mΩ, T

VIN = 6V, 54 LEDs, 20mA

= +25°C

A

86 %
each, L = 8.2µH with DCR

ΔI

OUT

D

MAX

D

MIN

f

OSC_hi

f

OSC_lo

/ΔV

106mΩ, T

IN

Line Regulation 0.1 %
Boost Maximum Duty Cycle 82 %
Boost Minimum Duty Cycle 7%
Lx Frequency Register 0x08, fSW = 1 1.0 1.2 1.3 MHz
Lx Frequency Register 0x08, fSW = 0 550 600 650 kHz

= +25°C

A

ILX_leakage Lx Leakage Current VLX = 36V, EN = 0 10 µA

REFERENCE

I

MATCH

I

ACC

Channel-to-Channel Current Matching I

= 30mA, BRT = 255 -3.5 ±1 +3.5 %

OUT

Current Accuracy ±3 %

FAULT DETECTION

V

SC

Short Circuit Threshold Accuracy Reg0x08 = 0x0F or 0x0B

7.8 8 8.8 V

Reg0x00 = 0xFF
Reg0x08 = 0x0E or 0x0A

2.8 3.1 3.8 V

Reg0x00 = 0xFF

V

temp_acc

V

OVPlo

OVP
OVP

hys

fault

Over-Temperature Threshold Accuracy 5 °C
Overvoltage Limit on OVP Pin 1.17 1.2 1.23 V
OVP Hysteresis 20 mV
OVP Short Detection Fault Level 300 mV

SMBus INTERFACE

VIL Guaranteed Range for Data, Clock Input Low Voltage 0.8 V
VIH Guaranteed Range for Data, Clock Input High Voltage 2.1 VDD V
VOL SMBus Data Line Logic Low Voltage with 1.1kΩ series

resistor from data bus to SMBDAT pin
SMBus Data Line Logic Low Voltage without series resistor

from data bus to SMBDAT pin

I

LEAK

V

DD

Input Leakage On SMBData/SMBClk -1 1 µA
Nominal Bus Voltage 3V to 5V ±10% 2.7 5.5 V

I

= 350µA 0.4 V

PULLUP

= 4mA 0.17 V

I

PULLUP

SMBus TIMING SPECIFICATIONS (Note 4)
f

SMB

t

BUF

t

HD:STA

SMBus Clock Frequency 10 100 kHz
Bus Free Time Between Stop and Start Condition 4.7 µs
Hold Time After (Repeated) START Condition. After this

4.0 µs

Period, the First Clock is Generated

t

SU:STA

t

SU:STO

Repeated Start Condition Setup Time 4.7 µs
Stop Condition Setup Time 4.0 µs

5

FN6434.2

December 22, 2008

ISL97635

Electrical Specifications All specifications below are tested at T

unless otherwise noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise

= -40°C to +85°C; VIN = 12V, EN = 5V, R

A

= 36.6kΩ,

SET

specified. Temperature limits established by characterization and are not production tested. (Continued)

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

t

HD:DAT

t

SU:DAT

t

LOW

t

HIGH

t

F

t

R

Data Hold Time 300 ns
Data Setup Time 250 ns
Clock Low Period 4.7 µs
Clock High Period 4.0 50 µs
Clock/data Fall Time 300 ns
Clock/data Rise Time 1000 ns

GENERAL TIMING SPECIFICATIONS (Note 4)

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

Minimum Setup Time Between VIN Rising above VUVLO
with EN = 1 and SMBus Communications

Minimum Setup Time Between EN Going High with VIN
above VUVLO and SMBus Communications

Minimum Time Between VIN Rising above VUVLO with
EN = 1 to SMBus BL CTRL On

Minimum Time Between EN Going High with VIN above
VUVLO to SMBus BL CTRL On

Minimum Time for LED Output to Respond to SMBus Data at
any Levels

Response Time Between Backlight CTRL Off with Boost
Not Switching to Backlight CTRL On with Boost Switching

Response Time Between Backlight CTRL On with Boost
Switching to Backlight CTRL Off with Boost Not Switching

LED Channel Short Circuit Fault Detection to Status
Register Data Ready

V

Short Circuit Detection During Operation to

OUT-GND

Status Register Data Ready
Time Between VIN Rising Above VUVLO with EN = 1 and

V

Short being Reported in Status Register

OUT-GND

Time Between EN Going High with VIN Above VUVLO and
a V

OUT-GND

Short being Reported in Status Register

EN = 1, TA = +25°C, VDC

80 µs
capacitor < 10µF

VIN > VUVLO, TA= +25°C,

80 µs
VDC capacitor < 10µF

EN = 1, TA = +25°C 4.5 ms

VIN > VUVLO, TA = +25°C 4.5 ms

VIN > VUVLO, EN = 1,
T

= +25°C

A

VIN > VUVLO, EN = 1,
T

= +25°C

A

VIN > VUVLO, EN = 1,
T

= +25°C

A

VIN > VUVLO, EN = 1,
T

= +25°C, LEDs Active

A

VIN > VUVLO, EN = 1,
T

= +25°C, Fault FET used

A

EN = 1, VDC capacitor < 10µF,

5µs

5µs

5µs

6ms

5µs

30 ms
TA = +25°C, Fault FET used.

> VUVLO, VDC capacitor <

V

IN

10µF, T
used.

= +25°C, Fault FET

A

30 ms

CURRENT SOURCES

V

headroom

V

RSET

ILEDmax Maximum LED Current per Channel R

Dominant Channel Current Source Headroom at IIN Pin I
Voltage at RSET Pin R

= 20mA, TA = +25°C 100 mV

LED

= 36.6kΩ 680 700 720 mV

SET

= 20.9kΩ 35 mA

SET

PWM GENERATOR

FPWM Generated PWM Frequency C

DPWM Duty Cycle Of Generated PWM (DC-to-PWM) V

= 27nF

FPWM

C

= 220nF

PWMO

= 0.3V

PWMO

CFPWM = 27nF

= 1.1V

V

PWMO

CFPWM = 27nF

200 Hz

90 %

10 %

tMAX_PWM_OFF Maximum P WMI Off Time B efore Sh u tdown EN/PWMI toggles 28 ms

6

FN6434.2

December 22, 2008

ISL97635

Electrical Specifications All specifications below are tested at T

unless otherwise noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise

= -40°C to +85°C; VIN = 12V, EN = 5V, R

A

= 36.6kΩ,

SET

specified. Temperature limits established by characterization and are not production tested. (Continued)

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

FAULT PIN

I

FAULT

V

FAULT

Fault Pull-down Current VIN = 12V 10 18 30 µA
Fault Clamp Voltage with Respect to V

IN

VIN = 12, VIN-V

FAULT

7.5 V

IlxStart-up Lx Start-up Current VDC = 5.2V 1 2.7 7 mA

Typical Performance Curves

92

7S6P - 18V

90
88
86
84
82
80
78
76

EFFICIENCY (%)

74
72
70
68
66

0 20 40 60 80 100 120 140 160 180

9S6P - 6V

9S8P - 6V

7S8P - 6V

7S8P - 6V

9S6P - 12V

7S6P - 6V

9S8P - 12V

7S8P - 12V

7S6P - 12V

(mA)

I

O

9S8P - 18V

7S8P - 18V

9S6P - 18V

L = 8.2µH
IHLP-2525BD-01
DCR = 106mΩ
I

= 3A

SAT

FIGURE 2. EFFICIENCY, L = 8.2µH WITH DCR = 106mΩ,

C

= 4x4.7µF/50V

O

92
90

7S6P - 18V

88
86
84
82
80
78
76
74

EFFICIENCY (%)

72
70
68

9S8P - 6V

66

0 20 40 60 80 100 120 140 160 180

7S6P - 6V

7S8P - 6V

7S8P - 6V

9S6P - 6V

9S8P - 12V

9S6P - 18V

9S6P - 12V

IO (mA)

9S8P - 18V

7S6P - 12V

7S8P - 12V

7S8P - 18V

L = 10µH
IHLP-2525BD-01
DCR = 129mΩ
I

= 2.5A

SAT

FIGURE 3. EFFICIENCY, L = 10µH WITH DCR = 129mΩ,

CO= 4x4.7µF/50V

92

7S8P - 12V

90

7S6P - 12V

88
86
84
82
80
78
76
74

EFFICIENCY (%)

72
70
68
66

9S8P - 12V

9S8P - 6V

0 20 40 60 80 100 120 140 160 180

7S6P - 18V

9S8P - 18V

7S8P - 6V

7S8P - 6V

9S6P - 6V

9S6P - 18V

9S6P - 12V

7S6P - 6V

(mA)

I

O

7S8P - 18V

L = 10µH
DCR = ~500mΩ

<1mm HEIGHT

FIGURE 4. 3 EFFICIENCY, L = 10µH WITH DCR = 500mΩ,

1mm, C

= 4µFx4.7µF/50V

O

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

CURRENT VARIATION (%)

-0.8

-1.0

-1.2
4 6 8 10 12 14 16 18 20 22 24 26

20mA

(V)

V

IN

FIGURE 5. CURRENT REGULATION

7

FN6434.2

December 22, 2008

Typical Performance Curves (Continued)

2.0

1.5

1.0

0.5

0.0

-0.5

-1.0

CURRENT MATCHING (%)

-1.5

-2.0
CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7

6V/1mA

FIGURE 6. CHANNEL-TO-CHANNEL CURRENT MATCHING

180

8 CHANNELS
9 LEDS PER CHANNEL

160
140
120
100

80
60
40

TOTAL OUTPUT CURRENT (mA)

20

0

0 102030405060708090100

FIGURE 8. PWM DIMMING LINEARITY FIGURE 9. LX, VIIN, IL AND I

12V/1mA

12V/20mA

6V/20mA

CHANNELS

VIN = 6V

VIN = 12V

VIN = 18V

PWM DUTY CYCLE (%)

ISL97635

1.0

0.9

0.8

0.7

0.6

CURRENT MATCHING (%)

0.5
0 102030405060708090100

1kHz

100kHz

20kHz

200kHz

10kHz

PWM DUTY CYCLE (%)

VIN = 12V

FIGURE 7. CURRENT MATCHING vs DUTY CYCLE vs

DIMMING FREQUENCY

AT PWM DIMMING

O

FIGURE 10. I

AT 50% PWM DIMMING

L

8

FIGURE 11. I

ZOOM IN AT PWM DIMMING ZOOM IN

L

December 22, 2008

FN6434.2

Typical Performance Curves (Continued)

ISL97635

FIGURE 12. LX AT 50% PWM DIMMING

FIGURE 14. RIPPLE VOLTAGE

FIGURE 13. LX ZOOM IN AT 50% DIMMING

FIGURE 15. I

AT 50% PWM DIMMING

LED

FIGURE 16. RIPPLE VOLTAGE ZOOM IN

9

FN6434.2

December 22, 2008