intersil ISL96017 DATA SHEET

®

www.BDTIC.com/Intersil

ISL96017

Data Sheet April 17, 2006

128-Tap DCP, 16kbit EEPROM, and I2C
Serial Interface

This device integrates a 128-tap digitally controlled
potentiometer, 16kbit of EEPROM, and a 2-wire I
interface. The device is powered by a single 3.3V supply.
The potentiometer is available with total resistance of either
10kΩ or 50kΩ.

The memory is organized in 128 pages of 16 bytes each, to
reduce total programming time. All programming signals are
generated on-chip.

The potentiometer is implemented with a combination of
CMOS switches and resistor elements. The position of the
wiper can be stored in non-volatile memory an d th en be
recalled upon a subsequent power-up. The three terminals
of the potentiometer are available for use as either a variable
resistor or a resistor divider.

2

C serial

Pinout

ISL96017

(8 LD TDFN)

TOP VIEW

FN8243.1

Features

• Integrated Digitally Controlled Potentiometer

- 128-Tap Positions

-10kΩ, 50kΩ Total Resistance

- Monotonic Over Temperature

- Non-Volatile Wiper Position Storage

- 0 to VDD Terminal Voltage

2

C Serial Interface

•I

• 16kbit EEPROM

- 50 Years Retention @ ≤ 55°C

- 1,000,000 Cycles Endurance

• Single 3.3

• 3mm x 3mm Thin DFN Package – 0.8mm Max Thickness,

0.65mm Pitch

• Pb-Free Plus Anneal Available (RoHS Compliant)

±0.3V Supply

RH

RW

RL

VDD

1
2
3
4

8

WP
SCL

7

SDA

6

GND

5

Ordering Information

TEMP.

PART NUMBER PART MARKING R

ISL96017WIRT8Z* (Note) 96017WIZ 10 -40 to 85 8 Ld 3x3 TDFN (Pb-free) L8.3x3A
ISL96017UIRT8Z* (Note) 96017UIZ 50 -40 to 85 8 Ld 3x3 TDFN (Pb-free) L8.3x3A

*Add "-TK" suffix for 1000 units tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

TOTAL

(kΩ)

RANGE (°C) PACKAGE

PKG.

DWG. #

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2005. All Rights Reserved

Block Diagram

www.BDTIC.com/Intersil

ISL96017

SDA

SCL

WP

POWER-UP,

INTERFACE,

AND

CONTROL

LOGIC

Pin Descriptions

PIN SYMBOL DESCRIPTION

1 RH “High” terminal of the DCP
2 RW “Wiper” terminal of the DCP
3 RL “Low” terminal of the DCP
4 VDD Power supply
5 GND Ground
6 SDA Open drain serial interface data input/output
7 SCL Open drain serial interface clock input
8WP

Hardware write protection pin. Active low. Prevents any “Write” operation to the device.

16kbit

EEPROM

RH

RW

RL

2

FN8243.1

April 17, 2006

ISL96017

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Storage Temperature: . . . . . . . . . . . . . . . . . . . . . . . .-65°C to 150°C

Note: All Voltages with Respect to GND

Voltage at SCL, SDA, WP

Voltage at RH, RW, RL: . . . . . . . . . . . . . . . . . . . . . . . GND to VDD

VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V

Lead Temperature (Soldering, 10s): . . . . . . . . . . . . . . . . . . . .300°C

Wiper Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

ESD (MIL-STD-883B, Method 3014). . . . . . . . . . . . . . . . . . .>2000V

ESD (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>150V

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional
operation of the device, at these or any other conditions above those listed in the op erational se ctions of th is specification, is not implied. Exposure to abso lute maximum
rating conditions for extended periods may affect device reliability.

Note:

θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1.

JA

Tech Brief TB379 for details.

: . . . . . . . . . . . . . . . . . . . . .-0.3V to 4V

Thermal Resistance (Typical, Note 1)

8 Ld TDFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90(°C/W)

Moisture Sensitivity (see Technical Brief TB363). . . . . . . . . .Level 2

Maximum Junction Temperature (Plastic Package). . . . . . . . . .150°C

Recommended Operating Conditions

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C

VDD Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 3.0V to 3.6V

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA

Power Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Electrical Specifications Over recommended operating conditions unless otherwise stated. All voltages with respect to GND.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

IccdSby Standby Current at VDD Serial interface in standby 10 µA

IccdRd Read Current at VDD Reading with 400kHz at SCL 1 mA
IccdWr Write Current at VDD Writing to EEPROM 5 mA
I

LkgDig

I

LkgDCP

VDDRamp VDD Power-Up Ramp Rate 0.2 V/ms

t

DCP

(Note 13)

t

D

CH/CW/CL

(Note 13)

R

Total

R

Wiper

DCP IN VOLTAGE DIVIDER MODE (0V at RL, VCC at RH; measured at RW unloaded)

FSerror

(Note 2, 3)

ZSerror

(Note 2, 4)

TC

(Note 7, 13)

DNL (Note 2, 5) Differential Non-Linearity Monotonic over all tap positions -0.75 0.75 LSB

INL (Note 2, 6) Integral Non-Linearity -1 1 LSB

Leakage Current at Pins SDA, SCL,
and WP

Leakage Current at RH, RW, RL Pin voltage from GND to VDD -1 1 µA

DCP Wiper Response Time SCL falling edge of last bit of DCP Data Byte to

Power-Up Delay VDD above 2.6V, to DCP Initial Value Register

RH, RW, RL Pin Capacitance 10 pF

Total Resistance W and U versions, respectively. TA =25°C.

R

Tolerance TA = 25°C. Measured between RH and RL pins. -20 20 %

Total

Wiper Resistance VDD = 3.3V @ 25°C. Wiper current = VDD/R
DCP Resolution 7Bits

Full-Scale Error U option -2 -1 0 LSB

Zero-Scale Error U option 0 1 2 LSB

Ratiometric Temperature

V

Coefficient

Pin voltage from GND to VDD -10 10 µA

wiper change

2

recall completed, and I
state

Measured between R

W option -5 -1 0 LSB

W option 0 1 5 LSB
DCP Register between 10 hex and 6F hex ±4 ppm/°C

C Interface in standby

and RL pins.

H

Total

(Note 1) MAX UNIT

1.5 µs

3ms

10, 50 kΩ

100 300 Ω

JA

θ

3

FN8243.1

April 17, 2006

ISL96017

www.BDTIC.com/Intersil

Electrical Specifications Over recommended operating conditions unless otherwise stated. All voltages with respect to GND. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN

DCP IN RESISTOR MODE (Measurements between RH and RW with RL not connected)

(Note 8) Resistance Offset. U version - DCP Register set to 7F hex.

R

127

TC

(Note 11,13)

RDNL

(Note 8,9)

RINL

(Note 8,10)

EEPROM SPECS

(Note 12) Non-Volatile Write Cycle Time 6 12 ms

t

WC

SERIAL INTERFACE SPECS

V

IL

V

IH

Hysteresis SDA and SCL Input Buffer

V

OL

Cpin WP
f

SCL

t

IN

t

AA

t

BUF

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

Resistance Temperature Coefficient ±100 ppm/°C

R

Resistance Differential Non­Linearity

Resistance Integral Non-Linearity -1 1 MI

EEPROM Endurance 1,000,000 Cycles
EEPROM Retention At 55°C 50 Years

WP, SDA, and SCL Input Buffer
LOW Voltage

WP, SDA and SCL Input Buffer
HIGH Voltage

Hysteresis
SDA Output Buffer LOW Voltage,

Sinking 4mA

, SDA, and SCL Pin Capacitance 10 pF
SCL Frequency 400 kHz
Pulse Width Suppression Time at

SDA and SCL Inputs.
SCL Falling Edge to SDA Output

Data Valid
Time the Bus Must be Free Before

the Start of a New Transmission

Clock LOW Time Measured at the 30% of VDD crossing 1300 ns
Clock HIGH Time Measured at the 70% of VDD crossing 600 ns
START Condition Setup Time SCL rising edge to SDA falling edge. Both

STAR T Condition Hold Time From SDA falling edge crossing 30% of VDD to

Input Data Setup Time From SDA exiting the 30% to 70% of VDD

Input Data Hold Time From SCL rising edge crossing 70% of VDD to

STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to

Measured between R
W version - DCP Register set to 7F hex.

Measured between R

Any pulse narrower than the max spec is
suppressed

SCL falling edge crossing 30% of VDD, until
SDA exits the 30% to 70% of VDD window

SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VDD during
the following START condition

crossing 70% of VDD

SCL falling edge crossing 70% of VDD

window, to SCL rising edge crossing 30% of
VDD

SDA entering the 30% to 70% of VDD window

SDA rising edge crossing 30% of VDD

and RW pins.

H

and RW pins.

H

00.52MI

-0.75 0.75 MI

-0.3 0.3*

0.7*

VDD

0.05*
VDD

00.4V

1300 ns

600 ns

600 ns

100 ns

0ns

600 ns

TYP

(Note 1) MAX UNIT

15MI

(Note 1)

(Note 1)

V

VDD
VDD

+0.3

50 ns

900 ns

V

V

4

FN8243.1

April 17, 2006