Intersil ISL95859C Datasheet
DATASHEET
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0 5 10 15 20 25
VIN = 12V
VIN = 6V
VIN = 21V
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0.91
0 5 10 15 20 25 30 35 40
VIN = 12V
VIN = 6V
VIN = 21V
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0.86
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0.88
0.89
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0.91
0123456
VIN = 12V
VIN = 6V
VIN = 21V
ISL95859C
1+2+1 Voltage Regulator With Expanded Iccmax Register Range Supporting
Intel IMVP8 CFL/CNL CPUs
The ISL95859C provides a complete power solution for
Intel microprocessors supporting core, graphics, and
system agent rails and is compliant with Intel IMVP8™.
The controller provides control and protection for three
Voltage Regulator (VR) outputs. The VR A and VR C
outputs support 1-phase operation only, while VR B is
configurable for 2- or 1-phase operation. The
programmable address options for these three outputs
allow for maximum flexibility in support of the IMVP8
CPU. All three VRs share a common serial control bus to
communicate with the CPU and achieve lower cost and
smaller board area compared with a two-chip approach.
Based on Intersil’s Robust Ripple Regulator (R3™)
technology, the R3 modulator has many advantages
compared to traditional modulators, including faster
transient settling time, variable switching frequency in
response to load transients, and improved light-load
efficiency due to Diode Emulation Mode (DEM) with
load-dependent low switching frequency.
The controller provides PWM outputs, which support Intel
CONFIDENTIAL
DrMOS power stages (or similar) and discrete power
stages using the Intersil ISL95808 high voltage
synchronous rectified buck MOSFET driver. The
controller complies with IMVP8 PS4 power requirements
and supports power stages and drivers, which are
compatible. The ISL95859C supports the system input
power monitor (PSYS) option. The controller supports
either DCR current sensing with a single NTC thermistor
for DCR temperature compensation or more precision
through resistor current sensing, if desired. All three
outputs feature remote voltage sense, programmable
I
, adjustable switching frequency, OC protection, and
MAX
a single VR_READY power-good indicator.
Features
• Supports the Intel serial data bus interface
• Fully supports PS4 Power Domain entry/exit
• Supports system input power monitor (PSYS)
• Three output controller
• VR A supports 1-phase VR design
• VR B configurable for 2- or 1-phase VR design
• VR C supports 1-phase VR design
• 0.5% system accuracy over temperature
• Low supply current in PS4 state
• Supports multiple current sensing methods
• Lossless inductor DCR current sensing
• Precision resistor current sensing
• Differential remote voltage sensing
• Programmable SVID address
• Programmable V
voltage at start-up
BOOT
• Resistor programmable address selection, I
switching frequency
• Adaptive body diode conduction time reduction
Applications
• IMVP8 compliant notebooks, desktops, Ultrabooks,
and tablets
FN8973
Rev.0.00
Oct 6, 2017
, and
MAX
Figure 1. V
Line = 2.4mΩ
CORE
/VR A Load
FN8973 Rev.0.00 Page 1 of 74
Oct 6, 2017
Figure 2. VGT/VR B Load Line = 2mΩ
Figure 3. VSA/VR C Load Line = 10.3mΩ
ISL95859C
Contents
1. Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Simplified Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.5 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2. Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. Typical Performance Curves for VR A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4. Typical Performance Curves for VR B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5. Typical Performance Curves for VR C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CONFIDENTIAL
6. Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 R3 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 Multiphase Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3 Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4 Adaptive Body Diode Conduction Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.6 Programming Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.7 PSYS System Power Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7. General Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1 Power Stages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2 Output Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3 Input Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.4 Inductor Current Sensing and Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5 Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.6 Current Sense Circuit Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.7 Voltage Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8. Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.1 VR_HOT#/ALERT# Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
FN8973 Rev.0.00 Page 2 of 74
Oct 6, 2017
ISL95859C
9. Serial VID (SVID) Supported Data and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . 67
10. Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12. Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
13. About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
CONFIDENTIAL
FN8973 Rev.0.00 Page 3 of 74
Oct 6, 2017
ISL95859C 1. Overview
- V
DROOP
+
FROM
CPU
COMP_A
PWM_A
VR A
R3
TM
MODULATOR
RTN_A
DIGITAL
BLOCK
SVID
START-UP
PROTECTION
TALRT
VTT
VIN
VRHOT#
NTC_A
VCC
FB_A
AGND
SCLK
SDA
ALRT#
PROG1
PSYS
VR_READY
IMON_A
VR_ENABLE
FROM
CPU
+5V
TO CPU
TO CPU
FROM
CHARGER
IMON AND DROOP
CIRCUITRY
OCP
DROOP
ERROR
AMPLIFIER
ISUMP_A
ISUMN_A
FCCM_A
- V
DROOP
+
FROM
CPU
COMP_B
PWM1_B
VR B
R3
TM
MODULATOR
RTN_B
DIGITAL
BLOCK
SVID
START-UP
PROTECTION
ISUMP_B
ISUMN_B
FB_B
PROG2
IMON_B
OCP
DROOP
ERROR
AMPLIFIER
PWM2_B
FCCM_B
ISEN2_B
ISEN1_B
VIN
- V
DROOP
+
FROM
CPU
COMP_C
VR C
R3
TM
MODULATOR
RTN_C
DIGITAL
BLOCK
SVID
START-UP
PROTECTION
ISUMP_C
ISUMN_C
FB_C
IMON_C
OCP
DROOP
ERROR
AMPLIFIER
PWM_C
FCCM_C
CURRENT
SENSE
VIN
CURRENT
SENSE
AND
BALANCE
CURRENT
SENSE
AND
BALANCE
TALRT
NTC_B
IC THERMAL
MONITOR
IC THERMAL
MONITOR
IMON AND DROOP
CIRCUITRY
DIFF REMOTE
SENSING
DIFF REMOTE
SENSING
IMON AND DROOP
CIRCUITRY
DIFF REMOTE
SENSING
1. Overview
1.1 Block Diagram
CONFIDENTIAL
FN8973 Rev.0.00 Page 4 of 74
Figure 4. Block Diagram
Oct 6, 2017
VR_ ENABLE
VR_READY
VCC
SENSE_CPU
VR_ ENABLE
VR_READY
SDA
SDA
ALERT #
ALERT #
SCLK
SCLK
GND
VCC
VR_HOT#
VR_HOT#
V+5
ISL95859C
PSYS
VSS
SENSE_CPU
VCC
SENSE_SA
VSS
SENSE_SA
SA
V
CORE
NTC_B
FCCM_B
PWM_C
FCCM_C
ISUMP_C
ISUMN_C
COMP_C
FB_C
RTN_ C
PSYS
VIN
VIN
PROG1
PROG2
PWM1_ B
UGATE
LGATE
PHASE
BOOT
PWM
FCCM
GND
ISL95808
VCC
VIN
°C
IMON_C
IMON_ A
FB_A
RTN_ A
VCC
SENSE_GT
GT
V
CORE
VSS
SENSE_GT
ISUMP_B
ISUMN_B
ISEN1_B
ISEN2_B
VIN
PWM2_B
VIN
UGATE
LGATE
PHASE
BOOT
PWM
FCCM
GND
ISL95808
VCC
V+5
UGATE
LGATE
PHASE
BOOT
PWM
FCCM
GND
ISL95808
VCC
COMP _B
FB_B
RTN_ B
°C
°C
V+5
IMON_B
NTC_ A
°C
SA
V
CORE
PWM_A
FCCM_ A
ISUMP_A
ISUM N_ A
COMP_ A
UGATE
LGATE
PHASE
BOOT
PWM
FCCM
GND
ISL95808
VCC
VIN
V+5
°C
ISL95859C 1. Overview
1.2 Simplified Application Circuits
CONFIDENTIAL
Figure 5. Typical ISL95859C Application Circuit Using Inductor DCR Current Sensing
FN8973 Rev.0.00 Page 5 of 74
Oct 6, 2017
ISL95859C 1. Overview
VR_ ENABLE
VR_READY
VCC
SENSE_CPU
VR_ENABLE
VR_READY
SDA
SDA
ALERT #
ALERT #
SCLK
SCLK
GND
VCC
VR_HOT#
VR_HOT#
V+5
ISL95859 C
CPU
V
CORE
PSYS
VSS
SENSE_CPU
NTC _B
FCCM_B
PSYS
VIN
VIN
PROG1
PROG2
PWM1_B
IMON_ A
FB_A
RTN_A
VCC
SENSE_GT
GT
V
CORE
VSS
SENSE_GT
ISUMP_B
ISUMN_B
ISEN1_B
ISEN2_B
VIN
PWM2_B
VIN
UGATE
LGATE
PHASE
BOOT
PWM
FCCM
GND
ISL 9580 8
VCC
V+5
UGATE
LGATE
PHASE
BOOT
PWM
FCCM
GND
ISL 9580 8
VCC
COMP_B
FB_B
RTN _B
°C
IMON_ B
NTC_A
°C
PWM_A
FCCM_A
ISUMP_A
ISUMN_A
UGATE
LGATE
PHASE
BOOT
PWM
FCCM
GND
ISL 95808
VCC
VIN
V+5
VCC
SENSE_SA
VSS
SENSE_SA
SA
V
CORE
PWM_C
FCCM_C
ISUMP_C
ISUMN_C
COMP_ C
FB_C
RTN_C
UGATE
LGATE
PHASE
BOOT
PWM
FCCM
GND
ISL 95808
VCC
VIN
IMON_ C
V+5
COMP_ A
CONFIDENTIAL
Figure 6. Typical ISL95859C Application Circuit Using Resistor Sensing
FN8973 Rev.0.00 Page 6 of 74
Oct 6, 2017
ISL95859C 1. Overview
40 39 38 37 36 35 34 33 32 31
29
30
27
28
25
26
23
24
21
22
11 12 13 14 15 16 17 18 19
2
1
4
3
6
5
8
7
10
9
GND
(BOTTOM PAD)
NTC_B
COMP_B
FB_B
ISUMP_B
RTN_C
FB_C
COMP_C
ISUMP_C
ISUMN_C
SDA
SCLK
ALERT#
PROG2
PROG1
ISUMN_B
20
VR_HOT#
RTN_B
VR_ENABLE
FCCM_B
PWM1_B
PWM2_B
IMON_A
COMP_A
FB_A
RTN_A
ISUMP_A
NTC_A
ISEN 1_B
VR_READY
FCCM_A
ISUMN_A
FCCM_C
PWM_ C
PWM_ A
PSYS
IMON_B
IMON_C
VCC
ISEN 2_B
VIN
1.3 Ordering Information
Part Number
(Notes 1
ISL95859CHRTZ 95859C HRTZ -10 to +100 40 Ld 5x5 TQFN L40.5x5
ISL95859CIRTZ 95859C IRTZ -40 to +100 40 Ld 5x5 TQFN L40.5x5
Notes:
1. Add “-T” for 6k unit tape and reel options. Refer to TB347
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials
and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pbfree soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For more information on MSL, refer to TB363
, 2, 3)Part Marking
.
Temp Range
(°C)
for details on reel specifications.
Package
(RoHS Compliant)
Pkg.
Dwg. #
1.4 Pin Configuration
ISL95859C
(40 LD TQFN)
Top View
CONFIDENTIAL
FN8973 Rev.0.00 Page 7 of 74
Oct 6, 2017
ISL95859C 1. Overview
1.5 Pin Descriptions
Pin Number Pin Name Description
BOTTOM PAD GND Signal common to the IC. Unless otherwise stated, all signals are referenced to the GND pad. It is also
the primary thermal conduction pad for heat removal. Connect this ground pad to the ground plane or
planes through a low impedance path. Best performance is obtained with an uninterrupted ground plane
under the ISL95859C and all associated components, signal sources, signal paths and extending from
the controller to the load. Do not attempt to isolate signal and power grounds.
1 PSYS Analog input from the platform battery charger that is proportional to real-time, total system power
dissipation. Information is to be digitized and stored by the controller to be read by the CPU from SVID.
2 IMON_B Regulator B current monitor. The IMON_B pin sources a current proportional to the regulator output
3 NTC_B Thermistor input from VR B to the temperature monitor circuit of the IC controlling the VR_HOT# output.
4 COMP_B Output of the transconductance error amplifier for VR B regulation and stability. Connect to ground
5 FB_B Output voltage feedback sensing input for regulation of Regulator B. Connect to the remote positive
6 RTN_B Ground return for differential remote output voltage sensing. Connect to the remote negative sense point
CONFIDENTIAL
7 ISUMP_B VR B droop current sensing inputs.
8ISUMN_B
9 ISEN1_B Individual current sensing for VR B Phase 1. This signal monitors and corrects for phase current
10 ISEN2_B Individual current sensing for VR B Phase 2. When ISEN2_B is pulled to VDD (+5V), the controller will
11 FCCM_B Driver control signal for Regulator B. When FCCM_B is high, continuous conduction mode is forced.
12 PWM1_B Regulator B, Channel 1 PWM output. See “
13 PWM2_B Regulator B, Channel 2 PWM output. See “
14 IMON_A Regulator A current monitor. The IMON_A pin sources a current proportional to the regulator output
15 NTC_A Thermistor input from VR A to the temperature monitor circuit of the IC controlling the VR_HOT# output.
16 COMP_A Output of the transconductance error amplifier for VR A regulation and stability. Connect to ground
17 FB_A Output voltage feedback sensing input for regulation of Regulator A. Connect to the remote positive
18 RTN_A Ground return for differential remote output voltage sensing. Connect to the remote negative sense point
current. A resistor connected from this pin to ground will set a voltage that is proportional to the load
current. This voltage is sampled internally to produce a digital IMON signal that is read through the serial
communication bus.
Connect this pin to a resistor network with a thermistor (NTC) to GND. A current is sourced from the pin
and generates a voltage, which is monitored versus an internal threshold to determine when the VR is too
hot.
through a type-II network to compensate the control loop.
sense point on the CPU through a resistor. The resistor value is used to scale droop for VR B.
on the CPU through a resistor.
Connecting ISUMN_B to VCC disables VR B.
imbalance. In 1-phase configurations, connect ISEN1_B to VCC or leave it open.
disable VR Phase 2. This signal is used to monitor and correct for phase current imbalance.
When FCCM_B is low, diode emulation is allowed. FCCM_B is high impedance and interfaces with the
ISL95808 or similar driver when entering a PS4 state.
Driver Selection” on page 35 for more information on
interfacing with the ISL95808 driver or compatible power stages.
Driver Selection” on page 35 for more information on
interfacing with the ISL95808 driver or compatible power stages.
current. A resistor connected from this pin to ground will set a voltage that is proportional to the load
current. This voltage is sampled internally to produce a digital IMON_A signal that is read through the
serial communication bus.
Connect this pin to a resistor network with a thermistor (NTC) to GND. A current is sourced from the pin
and generates a voltage, which is monitored versus an internal threshold to determine when the VR is too
hot.
through a type-II network to compensate the control loop.
sense point on the CPU through a resistor. The resistor value is used to scale droop for VR A.
on the CPU through a resistor.
FN8973 Rev.0.00 Page 8 of 74
Oct 6, 2017
ISL95859C 1. Overview
Pin Number Pin Name Description
19 ISUMP_A VR A droop current sensing inputs.
20 ISUMN_A
21 FCCM_A Driver control signal for Regulator A. When FCCM_A is high, Continuous Conduction Mode (CCM) is
22 PWM_A Regulator A, PWM output. See “
23 IMON_C Regulator C current monitor. The IMON_C pin sources a current proportional to the regulator output
24 COMP_C Output of the transconductance error amplifier for VR C regulation and stability. Connect to ground
25 FB_C Output voltage feedback sensing input for regulation of Regulator C. Connect to the remote positive
26 RTN_C Ground return for differential remote output voltage sensing. Connect to the remote negative sense point
27 ISUMP_C VR C droop current sensing inputs.
28 ISUMN_C
29 FCCM_C Driver control signal for Regulator C. When FCCM_C is high, Continuous Conduction Mode (CCM) is
CONFIDENTIAL
30 PWM_C Regulator C, PWM Output. See “
31 PROG2 Place a resistor from this pin to GND. The resistor value is selected based on programming options
32 PROG1 Place a resistor from this pin to GND. The resistor value is selected based on programming options
33 VIN Input supply voltage used for input voltage feed-forward.
34 VCC +5V bias supply input for the controller. Bypass to ground with a high quality 0.1µF ceramic capacitor.
35 SDA Communication bus between the CPU and the VRs.
36 ALERT#
37 SCLK
38 VR_HOT# Open-drain thermal overload output indicator. Considered part of the communication bus with the CPU.
39 VR_READY Power-good open-drain output indicating when controller is able to supply regulated voltage on all
40 VR_ENABLE Controller enable input. A high level logic signal on this pin enables the controller.
Connecting ISUMN_A to VCC disables VR A.
forced. When FCCM_A is low, diode emulation is allowed. FCCM_A is high impedance and interfaces
with the ISL95808 or similar driver when entering a PS4 state.
Driver Selection” on page 35 for more information on interfacing with the
ISL95808 driver or compatible power stages.
current. A resistor connected from this pin to ground will set a voltage that is proportional to the load
current. This voltage is sampled internally to produce a digital IMON signal that is read through the serial
communication bus.
through a type-II network to compensate the control loop.
sense point on the CPU through a resistor. The resistor value is used to scale droop for VR C.
on the CPU through a resistor.
Connecting ISUMN_C to VCC disables VR C.
forced. When FCCM_C is low, diode emulation is allowed. FCCM_C is high impedance and interfaces
with the ISL95808 or similar driver when entering a PS4 state.
Driver Selection” on page 35 for more information on interfacing with the
ISL95808 driver or compatible power stages.
defined in the controller option tables.
defined in the controller option tables.
This pin establishes the voltage reference for all PWM and FCCM driver interface outputs. To ensure
proper operation of drivers, especially during power-up and power-down sequencing, it is essential that
this pin be powered with the same +5V power supply as the VCC or VCCP pins of the Intersil gate
drivers.
outputs. Pull up externally with a 680Ω resistor to VCC or 1.9kΩ to 3.3V
FN8973 Rev.0.00 Page 9 of 74
Oct 6, 2017
ISL95859C 2. Specifications
2. Specifications
2.1 Absolute Maximum Ratings
Parameter Minimum Maximum Unit
Supply Voltage, V
Battery Voltage, V
All Other Pins -0.3 V
Open-Drain Outputs, VR_READY, VR_HOT#, ALERT# -0.3 +6.5 V
Human Body Model (Tested per JESD22-A114E) 2 kV
Charged Device Model (Tested per JESD22-C101A) 1 kV
Latch-Up (Tested per JESD78B; Class 2, Level A) 100 mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may
adversely impact product reliability and result in failures not covered by warranty.
CC
IN
ESD Rating Value Unit
2.2 Thermal Information
Thermal Resistance (Typical)
40 Ld TQFN Package (Notes 4, 5)30 1.5
Notes:
4.
is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach”
JA
CONFIDENTIAL
features. Refer to TB379
5. For
, the “case temp” location is the center of the exposed metal pad on the package underside.
JC
.
(°C/W) JC (°C/W)
JA
-0.3 +6.5 V
+28 V
+ 0.3 V
CC
Parameter Minimum Maximum Unit
Maximum Junction Temperature +150 °C
Maximum Storage Temperature Range -65 +150 °C
Maximum Junction Temperature (Plastic Package) +150 °C
Storage Temperature Range -65 +150 °C
Pb-Free Reflow Profile Refer to TB493
2.3 Recommended Operating Conditions
Parameter Minimum Maximum Unit
Supply Voltage, V
Input Voltage, VIN +4.5 25 V
Ambient Temperature
HRTZ -10 +100 °C
IRTZ -40 +100 °C
Junction Temperature
HRTZ -10 +125 °C
IRTZ -40 +125 °C
CC
+5V ±5% V
FN8973 Rev.0.00 Page 10 of 74
Oct 6, 2017
ISL95859C 2. Specifications
2.4 Electrical Specifications
V
= 5V, VIN = 15V, fSW = 583kHz, unless otherwise noted. Boldface limits apply across the operating temperature range
CC
T
= -40°C to +100°C for industrial (IRTZ) and TA = -10°C to +100°C for high temperature commercial (HRTZ).
A
Min
Symbol Parameter Test Conditions
Input Power Supply
I
VCC
I
R
Power-on-Reset Thresholds
VCCPOR
VCCPOR
VINPOR
VINPOR
System and References
HRTZ System Accuracy VID = 0.75V to 1.52V -0.5 0.5 %
IRTZ VID = 0.75V to 1.52V -0.8 0.8 %
HRTZ SA Internal V
IRTZ 1.05 V
HRTZ IA, GT, GTUS Internal V
IRTZ 0V
V
OUT(max)
V
OUT(min)
Switching Frequency
f
SW_450k
f
SW_583k
f
SW_750k
Amplifiers
HRTZ Current-sense Amplifier Input
IRTZ -0.3 0.3 mV
A
GBW Error Amplifier
+5V Supply Current VR_ENABLE = 1V (PWMs are not
VIN Supply Current VR_ENABLE = 0V 1 µA
VIN
VIN Input Resistance VR_ENABLE = 1V 700 kΩ
VIN
Power-On Reset
rVCC
Threshold
f
Power-On Reset
rVIN
Threshold
f
CONFIDENTIAL
BOOT
Maximum Programmed
Output Voltage
Minimum Programmed
Output Voltage
450kHz Configuration Set by R_PROG1 and R_PROG2 415 500 kHz
583kHz Configuration 540 630 kHz
750kHz Configuration 685 795 kHz
Offset
Error Amplifier DC Gain
v0
(Note 7
)
Gain-Bandwidth Product
(Note 7
)
switching)
VR_ENABLE = 0V 1 µA
PS4 state for all VRs and input power
domain
VCC rising 4.40 4.50 V
VCC falling 4.00 4.15 V
VIN rising 4.00 4.35 V
VIN falling 2.90 3.40 V
VID = 0.5V to 0.745V -7 7 mV
VID = 0.25V to 0.495V -10 10 mV
VID = 0.5V to 0.745V -9 9 mV
VID = 0.25V to 0.495V -12 12 mV
BOOT
VI D = [11111111] 1. 52 V
VID = [00000001] 0.25 V
= 0A -0.2 0.2 mV
I
FB
C
= 20pF 30 MHz
L
(Note 6
)Typ
16 18 mA
80 140 µA
1.05 V
0V
38 dB
Max
(Note 6)Unit
FN8973 Rev.0.00 Page 11 of 74
Oct 6, 2017
ISL95859C 2. Specifications
= 5V, VIN = 15V, fSW = 583kHz, unless otherwise noted. Boldface limits apply across the operating temperature range
V
CC
T
= -40°C to +100°C for industrial (IRTZ) and TA = -10°C to +100°C for high temperature commercial (HRTZ).
A
Symbol Parameter Test Conditions
ISEN
Imbalance Voltage Maximum of ISENs - minimum of
ISENs
Input Bias Current 20 nA
Power-Good and Protection Monitors
V
I
PWM and FCCM
V
V
t
PS4EXIT
Protection
OV
Logic Thresholds
V
V
V
Thermal Monitor
VR_READY Low Voltage I
OL
VR_READY Leakage Current VR_READY = 3.3V 1 µA
OH
ALERT# Low Voltage
(Note 7
VR_HOT# Low Voltage
(Note 7
ALERT# Leakage Current 1 µA
VR_HOT# Leakage Current 1 µA
PWM Output Low Sinking 5mA 0.6 0.9 V
0L
FCCM Output Low Sinking 4mA 0.6 0.9 V
PWM Output High (Note 7) Sourcing 5mA 3.5 4.2 V
0H
FCCM Output High (Note 7
CONFIDENTIAL
PWM Tri-State Voltage 2.5 V
FCCM Mid-State Voltage 2.5 V
PWM Tri-State and FCCM
High Impedance Leakage
PS4 Exit Latency VCC = 5V 50 100 µs
Overvoltage Threshold ISUMN rising above setpoint for >1µs 240 360 mV
H
Overcurrent Threshold
(ISUMN Pin Current)
VR_ENABLE Input Low 0.3 V
IL
VR_ENABLE Input High HRTZ 0.7 V
IH
IH
NTC Source Current NTC = 1.3V 9.5 10 10.5 µA
VR_HOT# Trip Voltage Falling 0.187 0.198 0.209 V
VR_HOT# Reset Voltage Rising 0.209 0.220 0.231 V
VR_HOT# Hysteresis 20 mV
Thermal Alert Trip Voltage Falling 0.203 0.214 0.225 V
Thermal Alert Reset Voltage Rising 0.225 0.236 0.247 V
Thermal Alert Hysteresis 20 mV
VR_READY
)
)
) Sourcing 4mA 3.3 3.6 V
PWM and FCCM = 2.5V -1 1 µA
2-phase configuration PS0 state or
1-phase configuration covering all
power states
2-phase configuration with 1-phase
operation in PS1, PS2 and PS3 states
IRTZ 0.75 V
= 4mA 0.15 0.40 V
Min
(Note 6
)Typ
7 12 Ω
7 12 Ω
56 60 64 µA
27 30 33 µA
Max
(Note 6)Unit
1 mV
FN8973 Rev.0.00 Page 12 of 74
Oct 6, 2017
ISL95859C 2. Specifications
V
= 5V, VIN = 15V, fSW = 583kHz, unless otherwise noted. Boldface limits apply across the operating temperature range
CC
T
= -40°C to +100°C for industrial (IRTZ) and TA = -10°C to +100°C for high temperature commercial (HRTZ).
A
Symbol Parameter Test Conditions
Current Monitor
I
IMON
V
IMONrICCMAX
V
IMONf
Inputs
I
VR_ENABLE
Slew Rate (For VID Change)
Notes:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
7. Limits established by characterization and are not production tested.
IMON Output Current ISUM- pin current = 40µA 9.7 10 10.3 µA
ISUM- pin current = 20µA 4.8 5 5.2 µA
ISUM- pin current = 4µA 0.875 1 1.125 µA
Alert Trip Voltage Rising 1.185 1.200 1.215 V
I
Alert Reset Voltage Falling 1.115 1.130 1.145 V
CCMAX
VR_ENABLE Leakage
Current
SCLK, SDA Leakage VR_ENABLE = 0V, SCLK and
CONFIDENTIAL
Fast Slew Rate 30 mV/µs
Slow Slew Rate 15 mV/µs
SVID
SVID CLK Maximum Speed
(Note 7
)
SVID CLK Minimum Speed
(Note 7
)
characterization and are not production tested.
VR_ENABLE = 0V -1 0µA
VR_ENABLE = 1V 3 5 µA
SDA = 0V and 1V
VR_ENABLE = 1V, SCLK and
SDA = 1V
VR_ENABLE = 1V, SCLK and
SDA = 0V, SCLK Leakage
VR_ENABLE = 1V, SCLK and
SDA = 0V, SDA Leakage
Min
(Note 6
)Typ
-1 1 µA
-5 1 µA
-42 µA
-24 µA
42 MHz
13 MHz
Max
(Note 6)Unit
FN8973 Rev.0.00 Page 13 of 74
Oct 6, 2017
ISL95859C 3. Typical Performance Curves for VR A
3. Typical Performance Curves for VR A
Figure 7. V
Figure 9. V
/VR A Soft-Start, SetVID_fast 0V to 0.9V,
CORE
I
O
=0A
Figure 8. V
/VR A Soft-Start with Precharged Output,
CORE
SetVID_fast 0.9V, I
= 0A
O
CONFIDENTIAL
/VR A Shutdown, IO= 23A, VID = 0.9V
CORE
Figure 10. V
/VR A PS0 Steady-State Phase and
CORE
Ripple, IO= 23A, VID = 0.9V
Figure 11. V
FN8973 Rev.0.00 Page 14 of 74
Oct 6, 2017
/VR A PS1 Steady-State Phase and
CORE
Ripple, IO= 23A, VID = 0.9V
Figure 12. V
/VR A PS2 Steady-State Phase and
CORE
Ripple, IO= 2A, VID = 0.9V
ISL95859C 3. Typical Performance Curves for VR A
Figure 13. V
CONFIDENTIAL
Figure 15. V
/VR A PS0 Load Step, IO = 4A to 29A,
CORE
VID = 0.9V, R_LL = 2.4mΩ
/VR A Load Step, IO = 1A IN PS2 to 26A
CORE
in PS0, VID = 0.9V, R_LL = 2.4mΩ
Figure 14. V
Figure 16. V
/VR A PS0 Load Step, IO = 18A to 28A,
CORE
VID = 0.9V, R_LL = 2.4mΩ
/VR A SetVID_fast, 0.6V to 0.9V, PS0,
CORE
IO= 7A, R_LL = 2.4mΩ
Figure 17. V
FN8973 Rev.0.00 Page 15 of 74
Oct 6, 2017
/VR A SetVID_fast, 0.9V to 0.6V, PS0,
CORE
IO= 7A, R_LL = 2.4mΩ
Figure 18. V
/VR A SetVID_slow, 0.6V to 0.9V to 0.6V,
CORE
PS0, IO= 7A, R_LL = 2.4mΩ
ISL95859C 3. Typical Performance Curves for VR A
Figure 19. V
SetVID_decay, 0.9V to 0.7V, IO = 1.5A, R_LL = 2.4mΩ
/VR A SetVID_fast, 0.7V to 0.9V, PS0,
CORE
CONFIDENTIAL
Figure 21. V
SetVID_slow to 0.3V, PS2, I
/VR A SetVID_fast, 0.3V to 0.9V,
CORE
= 1A, R_LL = 2.4mΩ
O
Figure 20. V
Figure 22. V
/VR A SetVID_fast, 0.3V to 0.9V to 0.3V,
CORE
PS1, IO= 7A, R_LL = 2.4mΩ
/VR A PS4 EXIT, SetVID_fast 0.9V, PS0,
CORE
= 0A, R_LL = 2.4mΩ
I
O
Figure 23. V
Pre-Empted Downward by SetVID_fast 0.6V, IO = 2.1A,
FN8973 Rev.0.00 Page 16 of 74
Oct 6, 2017
/VR A SetVID_decay 0.9V to 0.3V,
CORE
R_LL = 2.4mΩ
Figure 24. V
Pre-Empted Upward by SetVID_fast 0.6V, IO = 4.4A,
/VR A SetVID_decay 0.9V to 0.3V,
CORE
R_LL = 2.4mΩ
ISL95859C 4. Typical Performance Curves for VR B
4. Typical Performance Curves for VR B
Figure 25. VGT/VR B Soft-Start, SetVID_fast 0V to 0.9V,
=0A
I
O
CONFIDENTIAL
Figure 27. VGT/VR B Shutdown, IO= 35A, VID = 0.9V
Figure 26. VGT/VR B Soft-Start with Precharged Output,
SetVID_fast 0.9V, IO = 0A
Figure 28. VGT/VR B PS0 Steady-State Phase and Ripple,
I
= 35A, VID = 0.9V
O
Figure 29. VGT/VR B PS1 Steady-State Phase and Ripple,
= 10A, VID = 0.9V
I
O
FN8973 Rev.0.00 Page 17 of 74
Oct 6, 2017
Figure 30. VGT/VR B PS2 Steady-State Phase and Ripple,
= 2A, VID = 0.9V
I
O
ISL95859C 4. Typical Performance Curves for VR B
Figure 31. VGT/VR B PS0 Load Step, IO = 11A to 57A,
VID = 0.9V, R_LL = 2.0mΩ
CONFIDENTIAL
Figure 33. VGT/VR B Load Step, I
PS0, VID = 0.9V, R_LL = 2.0mΩ
= 1A in PS2 to 47A in
O
Figure 32. IVGT/VR B PS0 Load Step, IO = 30A to 40A,
VID = 0.9V, R_LL = 2.0mΩ
Figure 34. VGT/VR B SetVID_fast, 0.6V to 0.9V, PS0,
= 11A, R_LL = 2.0mΩ
I
O
Figure 35. IVGT/VR B SetVID_fast, 0.9V to 0.6V, PS0,
= 11A, R_LL = 2.0mΩ
I
O
FN8973 Rev.0.00 Page 18 of 74
Oct 6, 2017
Figure 36. VGT/VR B SetVID_slow, 0.6V to 0.9V to 0.6V,
PS0, I
= 11A, R_LL = 2.0mΩ
O
ISL95859C 4. Typical Performance Curves for VR B
Figure 37. VGT/VR B SetVID_fast, 0.6V to 0.9V, PS0,
SetVID_decay, 0.9V to 0.6V, IO = 2A, R_LL = 2.0mΩ
CONFIDENTIAL
Figure 39. VGT/VR B SetVID_fast, 0.3V to 0.9V,
SetVID_slow to 0.3V, PS2, I
= 1A, R_LL = 2.0mΩ
O
Figure 38. VGT/VR B SetVID_fast, 0.3V to 0.9V to 0.3V, PS1,
IO= 10A, R_LL = 2.0mΩ
Figure 40. VGT/VR B PS4 Exit, SetVID_fast 0.9V, PS0,
= 0A, R_LL = 2.0mΩ
I
O
Figure 41. VGT/VR B SetVID_decay 0.9V to 0.3V,
Pre-Empted Downward by SetVID_fast 0.6V, I
R_LL = 2.0mΩ
FN8973 Rev.0.00 Page 19 of 74
Oct 6, 2017
= 1.5A,
O
Figure 42. VGT/VR B SetVID_decay 0.9V to 0.3V,
Pre-Empted Upward by SetVID_fast 0.6V, I
R_LL = 2.0mΩ
= 4A,
O
ISL95859C 5. Typical Performance Curves for VR C
5. Typical Performance Curves for VR C
Figure 43. VSA/VR C Soft-Start, 0V to V
=0A
I
O
BOOT
= 1.05V,
CONFIDENTIAL
Figure 45. VSA/VR C Shutdown, IO=5A, VID=0.9V
Figure 44. VSA/VR C Soft-Start with Precharged Output,
V
= 1.05V, IO = 0A
BOOT
Figure 46. VSA/VR C PS0 Steady-State Phase and Ripple,
I
= 5A, VID = 0.9V
O
Figure 47. VSA/VR C PS1 Steady-State Phase and Ripple,
= 5A, VID = 0.9V
I
O
FN8973 Rev.0.00 Page 20 of 74
Oct 6, 2017
Figure 48. VSA/VR C PS0 Steady-State Phase and Ripple,
IO= 1A, VID = 0.9V
ISL95859C 5. Typical Performance Curves for VR C
Figure 49. VSA/VR C PS0 Load Step, IO = 2A to 5A,
VID = 0.9V, R_LL = 10.3mΩ
CONFIDENTIAL
Figure 51. VSA/VR C Load Step, I
PS0, VID = 0.9V, R_LL = 10.3mΩ
= 1A in PS2 to 5A in
O
Figure 50. VSA/VR C PS0 Load Step, IO = 2A to 3A,
VID = 0.9V, R_LL = 10.3mΩ
Figure 52. VSA/VR C SetVID_fast, 0.6V to 0.9V, PS0,
IO= 3A, R_LL = 10.3mΩ
Figure 53. VSA/VR C SetVID_fast, 0.9V to 0.6V, PS0,
I
= 3A, R_LL = 10.3mΩ
O
FN8973 Rev.0.00 Page 21 of 74
Oct 6, 2017
Figure 54. VSA/VR C SetVID_slow, 0.6V to 0.9V to 0.6V,
PS0, I
= 3A, R_LL = 10.3mΩ
O
ISL95859C 5. Typical Performance Curves for VR C
Figure 55. VSA/VR C SetVID_fast, 0.6V to 0.9V, PS0,
SetVID_decay, 0.9V to 0.6V, IO = 200mA, R_LL = 10.3mΩ
CONFIDENTIAL
Figure 57. VSA/VR C SetVID_fast, 0.3V to 0.9V,
SetVID_slow to 0.3V, PS2, I
= 200mA, R_LL = 10.3mΩ
O
Figure 56. VSA/VR C SetVID_fast, 0.3V to 0.9V to 0.3V, PS1,
IO= 3A, R_LL = 10.3mΩ
Figure 58. VSA/VR C PS4 Exit, SetVID_fast 0.9V, PS0,
IO= 0A, R_LL = 10.3mΩ
Figure 59. VSA/VR C SetVID_decay 0.9V to 0.3V,
Pre-Empted Downward by SetVID_fast 0.6V, IO = 250mA,
R_LL = 10.3mΩ
FN8973 Rev.0.00 Page 22 of 74
Oct 6, 2017
Figure 60. VSA/VR C SetVID_decay 0.9V to 0.3V,
Pre-Empted Upward by SetVID_fast 0.6V, I
R_LL = 10.3mΩ
= 650mA,
O
ISL95859C 6. Theory of Operation
Figure 61. Modulator Waveforms During Load Transient
PWM
SYNTHETIC CURRENT SIGNAL
ERROR AMPLIFIER
WINDOW VOLTAGE V
W
(WRT V
COMP
)
VOLTAGE V
COMP
6. Theory of Operation
The ISL95859C is a three output, multiphase controller supporting Intel IMVP8 microprocessor Core (IA), Graphics
(GT), and System Agent (SA), or GTUS rails. The controller supports single-phase operation on outputs VR A and VR C.
Voltage regulator VR B supports 1- or 2-phase operation. The ISL95859C is compliant to Intel IMVP8 specifications with
SerialVID features. The system parameters and SVID required registers are programmable through 2 dedicated
programming pins. This greatly simplifies the system design for various platforms and lowers inventory complexity and
cost by using a single device. The “Typical Application Circuits” section beginning on page 14
view of configuring all three outputs using the ISL95859C controller.
6.1 R3 Modulator
The R3 modulator is Intersil’s proprietary synthetic current-mode hysteretic controller which blends both fixed
frequency PWM and variable frequency hysteretic control technologies. This modulator topology offers high noise
immunity and a rapid transient response to dynamic load scenarios. Under static conditions the desired switching
frequency is maintained within the entire specified range of input voltages, output voltages and load currents.
During load transients the controller will increase or decrease the PWM pulses and switching frequency to maintain
output voltage regulation. Figure 61
climb from a load step, the time between PWM pulses decreases as f
regulation.
illustrates this effect during a load insertion. As the window voltage starts to
increases to keep the output within
SW
provides a top level
CONFIDENTIAL
6.2 Multiphase Power Conversion
Microprocessor load current profiles have changed to the point that the advantages of multiphase power conversion
are impossible to ignore. Multiphase converters overcome the daunting technical challenges in producing a costeffective and thermally viable single-phase converter at the high Thermal Design Current (TDC) levels. The
ISL95859C controller VR B output reduces the complexity of multiphase implementation by integrating vital
functions and requiring minimal output components.
6.2.1 Interleaving
The switching of each channel in a multiphase converter is timed to be symmetrically out-of-phase with the
other channels. For the example of a 3-phase converter, each channel switches 1/3 cycle after the previous
channel and 1/3 cycle before the following channel. As a result, the 3-phase converter has a combined ripple
frequency 3x that of the ripple frequency of any one phase, as illustrated in Figure 62
currents (I
, IL2, and IL3) combine to form the AC ripple current and to supply the DC load current.
L1
. The three channel
FN8973 Rev.0.00 Page 23 of 74
Oct 6, 2017
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