Intersil ISL95839HRTZ Schematic [ru]

ISL6208B

DRIVER

ISL95839

VR2

Vin

VR1

Vin

Vin

Vin

0.80

0.81

0.82

0.83

0.84

0.85

0.86

0.87

0.88

0.89

0.90

0.91

30 36 42 48 54 60 66

I

OUT

(A)

V

OUT

(V)

0 6 12 18 24

VIN = 19V

VIN = 12V

VIN = 8V

S

N

G

I

S

E

D

W

E

N

R

FO

D

E

D

N

E

M

M

O

C

E

R

T

O

N

O

C

E

R

O

c

1

N
ont

8

-

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N

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8

8

M

R

N

E

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T

L

I

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R

D

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w

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Dual 3+1 PWM Controller with Current Monitor for
IMVP-7/VR12™ CPUs

ISL95839

The ISL95839 Pulse Width Modulation (PWM) controller IC
provides a complete solution for IMVP-7/VR12™ compliant
microprocessor and graphic processor core power supplies. It
provides the control and protection for two Voltage Regulators
(VRs). The first VR, typical for V
drivers and can operate in 3-, 2- or 1-phase configurations. The
second VR, typical for Graphics, incorporates 1 integrated
driver. The two VRs share a serial control bus to communicate
with the CPU and achieve lower cost and smaller board area
compared with the two-chip approach.

Both VRs utilize Intersil’s Robust Ripple Regulator R3
Technology™. The R3 modulator has numerous advantages
compared to traditional modulators, including faster transient
response, variable switching frequency during load transients,
and improved light load efficiency due to its ability to
automatically change switching frequency.

The ISL95839 has several other key features. Both outputs
support either DCR current sensing with a single NTC
thermistor for DCR temperature compensation, or more
precise resistor current sensing if desired. Both outputs come
with remote voltage sense, programmable V
I

and switching frequency, adjustable overcurrent

MAX,

protection and separate Power-Good signals.

, incorporates 2 integrated

core

voltage,

BOOT

Features

• Serial data bus

•Dual outputs:

- Configurable 3-, 2- or 1-phase for the 1st output using two
integrated gate drivers

- 2nd output using an integrated gate driver

•R3™ Modulator

- Excellent transient response

- High light load efficiency

• 0.5% system accuracy over-temperature

• Supports multiple current sensing methods

- Lossless inductor DCR current sensing

- Precision resistor current sensing

• Differential remote voltage sensing

•Programmable V

• Resistor programmable I
outputs

• Output current monitor (IMON and IMONG)

• Adaptive body diode conduction time reduction

voltage at start-up

BOOT

MAX

, switching frequency for both

Applications

• IMVP-7/VR12 compliant computers

May 9, 2013
FN8315.0

FIGURE 1. SIMPLIFIED APPLICATION CIRCUIT FIGURE 2. LOAD LINE REGULATION

1

Intersil (and design) and R3 Technology™ are trademarks owned by Intersil Corporation or one of its subsidiaries.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

All other trademarks mentioned are the property of their respective owners.

|Copyright Intersil Americas LLC 2013. All Rights Reserved

ISL95839

Table of Contents

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Simplified Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Gate Driver Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Multiphase R3™ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Start-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Voltage Regulation and Load Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Differential Voltage Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

CCM Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Dynamic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

VR_HOT#/ALERT# Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

FB2 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Adaptive Body Diode Conduction Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Supported Data and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Key Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Programming Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Slew Rate Compensation Circuit for VID Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2

FN8315.0

May 9, 2013

Ordering Information

GND PAD

(BOTTOM)

40 39 38 37 36 35 34 33 32 31

29

30

27

28

25

26

23

24

21

22

11 12 13 14 15 16 17 18 19 20

2

1

4

3

6

5

8

7

10

9

NTCG

SCLK

ALERT#

SDA

VR_HOT#

FB2

NTC

ISEN2

ISEN1

ISUMP

ISUMN

RTN

FB

COMP

UGATE2

LGATE2

PWM3
LGATE1

FBG

COMPG

PGOODG

VR_ON

LGATE1G

PGOOD

PHASE2

VDD

BOOT2

IMON

PHASE1
UGATE1

PHASE1G

RTNG

ISUMNGISEN3

UGATE1G

IMONG

ISUMPG

BOOT1 BOOT1G

VCCP

ISL95839

PART NU MBER

(Notes 1, 2, 3) PART MARKING

ISL95839HRTZ 95839 HRTZ -10 to +100 40 Ld 5x5 TQFN L40.5x5

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL95839

for details on reel specifications.

TEMP. RANGE

(°C)

PACKAGE

(Pb-Free)

. For more information on MSL please see techbrief TB363.

PKG.

DWG. #

Pin Configuration

ISL95839

(40 LD TQFN)

TOP VIEW

Pin Descriptions

PIN # SYMBOL DESCRIPTION

2 IMONG Output current monitor for VR2.

3 IMON Output current monitor for VR1.

4 NTCG The second thermistor input to VR_HOT# circuit. Use it to monitor VR2 temperature.

5, 6, 7 SCLK, ALERT#,

SDA

8 VR_HOT# Open drain thermal overload output indicator. Can be considered part of communication bus with CPU.

9 FB2 There is a switch between the FB2 pin and the FB pin. The switch is on when VR1 is in 3-phase and 2-phase mode and is off

10 NTC One of the thermistor inputs to VR_HOT# circuit. Use it to monitor VR1 temperature.

11 ISEN3 ISEN3 is the individual current sensing for VR1 phase 3.

Communication bus between the CPU and the VRs.

in 1-phase mode. The components connecting to FB2 are used to adjust the compensation in 1-phase mode to achieve
optimum performance for VR1.

3

FN8315.0

May 9, 2013

ISL95839

Pin Descriptions (Continued)

PIN # SYMBOL DESCRIPTION

12 ISEN2 Individual current sensing for VR1 Phase 2. When ISEN2 and PWM3 are both pulled to 5V VDD, the controller will disable VR1

Phases 3 and 2.

13 ISEN1 Individual current sensing for VR1 Phase 1.

14, 15 ISUMP, ISUMN VR1 droop current sense input.

16 RTN VR1 remote voltage sensing return.

17 FB This pin is the inverting input of the error amplifier for VR1.

18 COMP This pin is the output of the error amplifier for VR1. Also, a resistor from this pin to GND programs I

for both VR1 and VR2.

19 PG OO D Po wer -G ood open -dra in ou tput indi cati ng w he n VR 1 i s ab le to supply regulated voltage. Pull up externally with a 680Ω resistor

20 BOOT1 Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is charged through an internal boot

21 UGATE1 Output of VR1 Phase-1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of the Phase-1 high-side MOSFET.

22 PHASE1 Current return path for the VR1 Phase-1 high-side MOSFET gate driver. Connect the PHASE1 pin to the node consisting of the

23 LGATE1 Output of VR1 Phase-1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of VR1 Phase-1 low-side MOSFET.

24 PWM3 PWM output for VR1 Phase 3. When PWM3 is pulled to 5V V

25 VDD 5V bias power.

26 VCCP Input voltage b ias for the in tern al gate drivers . Connect +5V to th e VCCP pin. Deco uple with at l east 1µF of an MLCC capacitor.

27 LGATE2 Output of VR1 Phase-2 low-side MOSFET gate driver. Connect the LGATE2 pin to the gate of VR1 Phase-2 low-side MOSFET.

28 PHASE2 Current return path for VR1 Phase-2 high-side MOSFET gate driver. Connect the PHASE2 pin to the node consisting of the

29 UGATE2 Output of VR1 Phase-2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of VR1 Phase-2 high-side MOSFET.

30 BOOT2 Connect an MLCC capacitor across the BOOT2 and the PHASE2 pins. The boot capacitor is charged through an internal boot

31 BOOT1G Connect an MLCC capacitor across the BOOT1G and the PHASE1G pins. The boot capacitor is charged through an internal

32 UGATE1G Output of VR2 Phase-1 high-side MOSFET gate driver. Connect the UGATE1G pin to the gate of VR2 Phase-1 high-side MOSFET.

33 PHASE1G Current return path for VR2 Phase-1 high-side MOSFET gate driver. Connect the PHASE1G pin to the node consisting of the

34 LGATE1G Output of VR2 Phase-1 low-side MOSFET gate driver. Connect the LGATE1G pin to the gate of VR2 Phase-1 low-side MOSFET.

35 VR_ON Controller enable input. A high level logic signal on this pin enables the controller.

36 PGOODG Power-Good open-drain output indicating when VR2 is able to supply regulated voltage. Pull-up externally with a 680Ω

37 COMPG This pin is the output of the error amplifier for VR2. Also, a resistor from this pin to GND programs I

38 FBG This pin is the inverting input of the error amplifier for VR2.

39 RTNG VR2 remote voltage sensing return.

40, 1 ISUMNG and

ISUMPG

Bottom

Pad

GND Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin. In addition, it is the return path for

to VCCP or 1.9kΩ to 3.3V.

diode connected from the VCCP pin to the BOOT1 pin, each time the PHASE1 pin drops below VCCP minus the voltage
dropped across the internal boot diode.

high-side MOSFET source, the low-side MOSFET drain, and the output inductor of VR1 Phase 1.

, the controller will disable VR1 Phase 3.

DD

high-side MOSFET source, the low-side MOSFET drain, and the output inductor of VR1 Phase 2.

diode connected from the VCCP pin to the BOOT2 pin, each time the PHASE2 pin drops below VCCP minus the voltage
dropped across the internal boot diode.

boot diode connected from the VCCP pin to the BOOT1G pin, each time the PHASE1G pin drops below VCCP minus the voltage
dropped across the internal boot diode.

high-side MOSFET source, the low-side MOSFET drain, and the output inductor of VR2 Phase 1.

resistor to VCCP or 1.9kΩ to 3.3V.

both VR1 and VR2.

VR2 droop current sense input. When ISUMNG is pulled to 5V V

all the low-side MOSFET gate drivers. It should also be used as the thermal pad for heat removal.

, all the communication to VR2 is disabled.

DD

for VR1, and V

MAX

for VR2 and T

MAX

MAX

BOOT

for

4

FN8315.0

May 9, 2013

Block Diagram

RTN

E/A

FB

IDROOP

CURRENT

SENSE

ISUMP

ISUMN

COMP

DRIVER

DRIVER

LGATE1

PHASE1

UGATE1

BOOT1

VCCP

OV FAULT

PGOOD

_

+

_

+

+

+

DRIVER

DRIVER

LGATE2

PHASE2

UGATE2

BOOT2

IBAL FAULT

OC FAULT

PWM3

ISEN3

ISEN2

ISEN1

CURRENT

BALANCING

DIGITAL

INTERFACE

SDA

ALERT#

SCLK

DRIVER

DRIVER

LGATE1G

PHASE1G

UGATE1G

BOOT1G

OV FAULT

PGOODG

OC FAULT

MODE1

DAC1

MODE2

DAC2

TEMP

MONITOR

NTCG

NTC

VR_HOT#

T_MONITOR

IMAX

VBOOT

TMAX

SET (A/D)

PROG

VR_ON

MODE

D/A

A/D IDROOP

IDROOPG

VREADY

RTNG

E/A

FBG

IDROOPG

CURRENT

SENSE

ISUMPG

ISUMNG

COMPG

VR2

MODULATOR

_

+

_

+

+

+

VR1

MODULATOR

FB2

CIRCUIT

VDD

GNDIMON

IMONG

FB2



ISL95839



5

FN8315.0

May 9, 2013

Simplified Application Circuit

FIGURE 3. TYPICAL ISL95839 APPLICATION CIRCUIT USING INDUCTOR DCR SENSING

NTCG

GND

VCCP

+5V

ISL95839

L2

L1

ISEN3

PHASE2

UGATE2

Rsum2

Rsum1

Rn

Cn

Ri

L3

Rsum3

BOOT2

V+5

Vin

LGATE2

ISEN2

PHASE1

UGATE1

BOOT1

LGATE1

PWM3

ISUMP

ISUMN

o

C

Risen2

Risen1

Risen3

ISEN1

Vsumn

Cisen3Cisen2Cisen1

Cvsumn

L4

GT Vcore

IMONG

UGATE1G

Rsum4

Rng

Cng

Rig

BOOT1G

Vin

LGATE1G

IMON

ISUMPG

ISUMNG

o

C

Rimon

Vsumng

Cvsumng

CPU Vcore

PHASE1G

VDD

Rdroop

VR_ON

PGOOD

VSSSENSE

VCCSENSE

Rntc

o

C

FB

VR_ON

COMP

RTN

PGOOD

NTC

Rdroopg

VSSSENSEG

VCCSENSEG

Rntcg

o

C

FBG

COMPG

RTNG

SDA SDA

ALERT# ALERT#

SCLK SCLK

PGOODG PGOODG

VR_HOT# VR_HOT#

RCOMPG

RCOMP

VCC

UGATE

LGATE

PHASE

BOOT

PWM

FCCM

GND

ISL6208

Cimon

Rimong

Cimong

FB2

ISL95839

6

FN8315.0

May 9, 2013

ISL95839

Absolute Maximum Ratings Thermal Information

Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V

Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V

Boot Voltage (BOOT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V

Boot-to-Phase Voltage

(BOOT-PHASE) -0.3V to +7V(DC) . . . . . . . . . . . . . . . .-0.3V to +9V (<10ns)

Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)

UGATE Voltage (UGATE) . . . . . . . . . . . . . . . . . . . PHASE - 0.3V (DC) to BOOT

. . . . . . . . . . . . . . . . . . . . PHASE - 5V (<20ns Pulse Width, 10µJ) to BOOT

LGATE Voltage . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD+0.3V

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)

Open Drain Outputs, PGOOD, VR_HOT#, ALERT#. . . . . . . . . . -0.3V to +7V

ESD Rating

Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . 2kV

Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V

Charged Device Model (Tested per JESD22-C101A) . . . . . . . . . . . . . . 1k

Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.

NOTES:

4. 

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379

5. For 

.

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Thermal Resistance (Typical) 

40 Ld TQFN Package (Notes 4, 5) . . . . . . . 32 4

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

(°C/W) JC (°C/W)

JA

Recommended Operating Conditions

Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Battery Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to 25V

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C

Electrical Specifications Operating Conditions: V

apply over the operating temperature range, -10°C to +100°C

PARAMETER SYMBOL TEST CONDITIONS

= 5V, TA = -10°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface limits

DD

MIN

(Note 6) TYP

MAX

(Note 6) UNITS

INPUT POWER SUPPLY

+5V Supply Current I

VDD

VR_ON = 1V 6.4 8.0 mA

VR_ON = 0V 1 µA

POWER-ON-RESET THRESHOLDS

VDD Power-On-Reset Threshold VDDPOR

VDDPOR

VIN Power-On-Reset Threshold VINPOR 4.40 4.75 V

VDD rising 4.35 4.5 V

r

VDD falling 4.00 4.15 V

f

SYSTEM AND REFERENCES

System Accuracy %Error (V

Internal V

Maximum Output Voltage V

Minimum Output Voltage V

BOOT

OUT(max)

OUT(min)

) No load; closed loop, active mode range,

OUT

VID = 0.75V to 1.52V, -0.5 +0.5 %

VID = 0.5V to 0.745V -6 +6 mV

VID = 0.25V to 0.495V -10 +10 mV

1.0945 1.100 1.1055 V

VID = [11111111] 1.52 V

VID = [00000001] 0.25 V

CHANNEL FREQUENCY

300kHz Configuration fSW_300k 277 300 323 kHz

350kHz Configuration f

400kHz Configuration f

450kHz Configuration f

AMPLIFIERS

Current-Sense Amplifier Input Offset I

Error Amp DC Gain A

Error Amp Gain-Bandwidth Product GBW C

_350k 324 350 376 kHz

SW

_400k 370 400 430 kHz

SW

_450k 412 445 478 kHz

SW

= 0A -0.2 +0.2 mV

FB

V0

= 20pF 18 MHz

L

90 dB

7

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ISL95839

Electrical Specifications Operating Conditions: V

= 5V, TA = -10°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface limits

DD

apply over the operating temperature range, -10°C to +100°C (Continued)

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 6) TYP

MAX

(Note 6) UNITS

ISEN

Imbalance Voltage Maximum of ISENs - Minimum of ISENs 1 mV

Input Bias Current 20 nA

POWER-GOOD AND PROTECTION MONITORS

I

PGOOD Low Voltage V

PGOOD Leakage Current I

OL

OH

= 4mA 0.15 0.4 V

PGOOD

PGOOD = 3.3V 1 µA

PGOOD Delay tpgd 2.6 ms

ALERT# Low 7 12 Ω

VR_HOT# Low 7 12 Ω

ALERT# Leakage Current 1 µA

VR_HOT# Leakage Current 1 µA

CURRENT MONITOR

IMON and IMONG Output Current I

IMON

ISUM- pin current = 40µA 9.7 10 10.3 µA

ISUM- pin current = 20µA 4.8 5 5.2 µA

ISUM- pin current = 4µA 0.875 1 1.125 µA

Alert Trip Voltage V

I

CCMAX

Alert Reset Voltage Falling 1.14 V

I

CCMAX

IMONMAX

Rising 1.2 V

IMON Voltage Clamp 1.8 V

GATE DRIVER

UGATE Pull-Up Resistance R

UGATE Source Current I

UGATE Sink Resistance R

UGATE Sink Current I

LGATE Pull-Up Resistance R

LGATE Source Current I

LGATE Sink Resistance R

LGATE Sink Current I

UGATE to LGATE De ad ti me t

LGATE to UGATE De ad ti me t

UGPU

UGSRC

UGPD

UGSNK

LGPU

LGSRC

LGPD

LGSNK

UGFLGR

LGFUGR

200mA Source Current 1.0 1.5 Ω

UGATE - PHASE = 2.5V 2.0 A

250mA Sink Current 1.0 1.5 Ω

UGATE - PHASE = 2.5V 2.0 A

250mA Source Current 1.0 1.5 Ω

LGATE - VSSP = 2.5V 2.0 A

250mA Sink Current 0.5 0.9 Ω

LGATE - VSSP = 2.5V 4.0 A

UGATE falling to LGATE rising, no load 17 ns

LGATE falling to UGATE rising, no load 29 ns

BOOTSTRAP SWITCH

On Resistance R

Reverse Leakage I

F

R

VR = 25V 0.2 µA

15 Ω

PROTECTION

Overvoltage Threshold OV

H

VSEN rising above setpoint for >1µs 145 175 200 mV

Current Imbalance Threshold (VR1) One ISEN above another ISEN for >3.2ms 23 mV

VR1 Overcurrent Threshold 3-Phase - PS0 and 1-Phase - all states 56 60 64 µA

3-Phase - PS1 37 40 43 µA

3-Phase - PS2 18 20 22 µA

2-Phase - PS0 56 60 64 µA

2-Phase - PS1 and PS2 27 30 33 µA

VR2 Overcurrent Threshold 1-Phase - all states 56 60 64 µA

8

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ISL95839

Electrical Specifications Operating Conditions: V

apply over the operating temperature range, -10°C to +100°C (Continued)

PARAMETER SYMBOL TEST CONDITIONS

LOGIC THRESHOLDS

VR_ON Input Low V

VR_ON Input High V

PWM3

PWM Output Low V

PWM Output High V

PWM Tri-State Leakage PWM = 2.5V 1 µA

NTC and NTCG

NTC Source Current NTC = 1.3V 58 60 62 µA

VR_HOT# Trip Voltage (VR1 and VR2) Falling 0.881 0.893 0.905 V

VR_HOT# Reset Voltage
(VR1 and VR2)

Therm_Alert Trip Voltage
(VR1 and VR2)

Therm_Alert Reset Voltage
(VR1 and VR2)

IL

IH

0L

0H

= 5V, TA = -10°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface limits

DD

MIN

(Note 6) TYP

0.7 V

Sinking 5mA 1.0 V

Sourcing 5mA 3.5 4.2 V

Rising 0.924 0.936 0.948 V

Falling 0.920 0.932 0.944 V

Rising 0.962 0.974 0.986 V

MAX

(Note 6) UNITS

0.3 V

INPUTS

VR_ON Leakage Current I

SCLK, SDA Leakage VR_ON = 0V, SCLK and SDA = 0V and 1V -1 1 µA

SLEW RATE (For VID Change)

Fast Slew Rate 10 mV/µs

Slow Slew Rate 2.5 mV/µs

NOTE:

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

VR_ON

VR_ON = 0V -1 0µA

VR_ON = 1V 3.5 6 µA

VR_ON = 1V, SCLK and SDA = 1V -2 1 µA

VR_ON = 1V, SDA = 0V -21 µA

VR_ON = 1V, SCLK= 0V -42 µA

9

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Gate Driver Timing Diagram

PWM

UGATE

LGATE

1V

1V

t

UGFLGR

t

RL

t

FU

t

RU

t

FL

t

LGFUGR

FIGURE 4. R

3

™ MODULATOR CIRCUIT

Crm

gmVo

MASTER

CLOCK

VW

COMP

MASTER

CLOCK

Phase

Sequencer

Clock1
Clock2

R

I

L1

gm

Clock1

Phase1

Crs1

VW

S

Q

PWM1

L1

R

I

L2

gm

Clock2

Phase2

Crs2

VW

S

Q

PWM2

L2

Co

Vo

Vcrm

Vcrs1

Vcrs2

MASTER CLOCK CIRCUIT

SLAVE CIRCUIT 1

SLAVE CIRCUIT 2

R

I

L3

gm

Clock3

Phase3

Crs3

VW

S

Q

PWM3

L3

Vcrs3

SLAVE CIRCUIT 3

Clock3

ISL95839

Theory of Operation

Multiphase R3™ Modulator

The ISL95839 is a multiphase regulator implementing Intel™
IMVP-7/VR12™ protocol. It has two voltage regulators, VR1 and
VR2, on one chip. VR1 can be programmed for 1-, 2- or 3-phase
operation, and VR2 is 1-phase operation. The following description
is based on VR1, but also applies to VR2 because they are based
on the same architecture.

The ISL95839 uses Intersil patented R3™ (Robust Ripple
Regulator™) modulator. The R3™ modulator combines the best
features of fixed frequency PWM and hysteretic PWM while
eliminating many of their shortcomings. Figure 4 conceptually
shows the multiphase R3™ modulator circuit, and Figure 5 shows
the operation principles.

Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor Crm with a current source equal
to g
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a
one-shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. If VR1 is in 3-phase
mode, the master clock signal will be distributed to the three
phases, and the Clock1~3 signals will be 120° out-of-phase. If
VR1 is in 2-phase mode, the master clock signal will be
distributed to Phases 1 and 2, and the Clock1 and Clock2 signals
will be 180° out-of-phase. If VR1 is in 1-phase mode, the master
clock signal will be distributed to Phase 1 only and will be the
Clock1 signal.

Each slave circuit has its own ripple capacitor C
mimics the inductor ripple current. A g
inductor voltage into a current source to charge and discharge
C
clock signal, and the current source charges C
voltage V
and the current source discharges Crs.

Since the controller works with V
and noise-free synthesized signals, it achieves lower phase jitter

, where gm is a gain factor. Crm voltage V

mVo

. The slave circuit turns on its PWM pulse upon receiving the

rs

hits VW, the slave circuit turns off the PWM pulse,

Crs

10

amplifier converts the

m

, which are large-amplitude

crs

crm

, whose voltage

rs

. When Crs

rs

is a

than conventional hysteretic mode and fixed PWM mode
controllers. Unlike conventional hysteretic mode converters, the
ISL95839 uses an error amplifier that allows the controller to
maintain a 0.5% output voltage accuracy.

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ISL95839

FIGURE 5. R3™ MODULATOR OPERATION PRINCIPLES IN

STEADY STATE

COMP

Vcrm

Master

Clock

PWM1

VW

Clock1

PWM2

Clock2

HYSTERETIC

WINDOW

PWM3

Vcrs3

Clock3

Vcrs2 Vcrs1

VW

FIGURE 6. R3™ MODULATOR OPERATION PRINCIPLES IN LOAD

INSERTION RESPONSE

COMP

Vcrm

Master

Clock

PWM1

Vcrs1

VW

Clock1

PWM2

Vcrs2

Clock2

PWM3

Clock3

Vcrs3

VW

UGATE

Phase

IL

LGATE

FIGURE 7. DIODE EMULATION

rises as the COMP voltage rises, making the PWM pulses wider.
During load release response, the COMP voltage falls. It takes
the master clock circuit longer to generate the next master clock
signal so the PWM pulse is held off until needed. The VW voltage
falls as the COMP voltage falls, reducing the current PWM pulse
width. This kind of behavior gives the controller excellent
response speed.

The fact that all the phases share the same VW window voltage
also ensures excellent dynamic current balance among phases.

Diode Emulation and Period Stretching

Figure 6 shows the operation principles during load insertion
response. The COMP voltage rises during load insertion,
generating the master clock signal more quickly, so the PWM
pulses turn on earlier, increasing the effective switching
frequency, which allows for higher control loop bandwidth than
conventional fixed frequency PWM controllers. The VW voltage

11

ISL95839 can operate in diode emulation (DE) mode to improve
light load efficiency. In DE mode, the low-side MOSFET conducts
when the current is flowing from source to drain and doesn’t allow
reverse current, emulating a diode. As Figure 7 shows, when
LGATE is on, the low-side MOSFET carries current, creating
negative voltage on the phase node due to the voltage drop across
the ON-resistance. The controller monitors the current through
monitoring the phase node voltage. It turns off LGATE when the
phase node voltage reaches zero to prevent the inductor current
from reversing the direction and creating unnecessary power loss.

If the load current is light enough, as Figure 7 shows, the inductor
current will reach and stay at zero before the next phase node
pulse and the regulator is in discontinuous conduction mode
(DCM). If the load current is heavy enough, the inductor current
will never reach 0A, and the regulator is in CCM although the
controller is in DE mode.

Figure 8 shows the operation principle in diode emulation mode at
light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size, therefore is the same, making the inductor current
triangle the same in the three cases. The controller clamps the
master ripple capacitor voltage V
voltage V
takes the V

in DE mode to make it mimic the inductor current. It

crs

longer to hit COMP, naturally stretching the

crm

and the slave ripple capacitor

crm

switching period. The inductor current triangles move further apart
from each other such that the inductor current average value is
equal to the load current. The reduced switching frequency helps
increase light load efficiency.

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iL

iL

Vcrs

iL

Vcrs

Vcrs

VW

CCM/DCM BOUNDARY

LIGHT DCM

DEEP DCM

VW

VW

FIGURE 8. PERIOD STRETCHING

VDD

VR_ON

DAC

2.6ms

2.5mV/µs
VID

SLEW RATE

VID

COMMAND

VOLTAGE

PGOOD

ALERT#

…...

FIGURE 9. VR1 SOFT-START WAVEFORMS

ISL95839

Start-up Timing

With the controller's VDD voltage above the POR threshold, the
start-up sequence begins when VR_ON exceeds the logic high
threshold. Figure 9 shows the typical start-up timing of VR1 and
VR2. The controller uses digital soft-start to ramp-up DAC to the
voltage programmed by the SetVID command. PGOOD is asserted
high and ALERT# is asserted low at the end of the ramp up. Similar
results occur if VR_ON is tied to V
starting 2.6ms after VDD crosses the POR threshold.

Voltage Regulation and Load Line
Implementation

After the start sequence, the controller regulates the output
voltage to the value set by the VID information per Table 1. The
controller will control the no-load output voltage to an accuracy of
±0.5% over the range of 0.25V to 1.52V. A differential amplifier
allows voltage sensing for precise voltage regulation at the
microprocessor die.

, with the soft-start sequence

DD

12

TABLE 1. VID TABLE

VID

HEX V

(V)765 43210

O

0 0 0 0 0 0 0 0 0 0 0.00000

0 0 0 0 0 0 0 1 0 1 0.25000

0 0 0 0 0 0 1 0 0 2 0.25500

0 0 0 0 0 0 1 1 0 3 0.26000

0 0 0 0 0 1 0 0 0 4 0.26500

0 0 0 0 0 1 0 1 0 5 0.27000

0 0 0 0 0 1 1 0 0 6 0.27500

0 0 0 0 0 1 1 1 0 7 0.28000

0 0 0 0 1 0 0 0 0 8 0.28500

0 0 0 0 1 0 0 1 0 9 0.29000

0 0 0 0 1 0 1 0 0 A 0.29500

0 0 0 0 1 0 1 1 0 B 0.30000

0 0 0 0 1 1 0 0 0 C 0.30500

000 011010D0.31000

0 0 0 0 1 1 1 0 0 E 0.31500

0 0 0 0 1 1 1 1 0 F 0.32000

0 0 0 1 0 0 0 0 1 0 0.32500

0 0 0 1 0 0 0 1 1 1 0.33000

0 0 0 1 0 0 1 0 1 2 0.33500

0 0 0 1 0 0 1 1 1 3 0.34000

0 0 0 1 0 1 0 0 1 4 0.34500

0 0 0 1 0 1 0 1 1 5 0.35000

0 0 0 1 0 1 1 0 1 6 0.35500

0 0 0 1 0 1 1 1 1 7 0.36000

0 0 0 1 1 0 0 0 1 8 0.36500

000 11001190.37000

000 110101A0.37500

0 0 0 1 1 0 1 1 1 B 0.38000

0 0 0 1 1 1 0 0 1 C 0.38500

0 0 0 1 1 1 0 1 1 D 0.39000

0 0 0 1 1 1 1 0 1 E 0.39500

0 0 0 1 1 1 1 1 1 F 0.40000

0 0 1 0 0 0 0 0 2 0 0.40500

001 00001210.41000

0 0 1 0 0 0 1 0 2 2 0.41500

0 0 1 0 0 0 1 1 2 3 0.42000

0 0 1 0 0 1 0 0 2 4 0.42500

0 0 1 0 0 1 0 1 2 5 0.43000

0 0 1 0 0 1 1 0 2 6 0.43500

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