intersil ISL95311 DATA SHEET

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ISL95311

Digitally Controlled Potentiometer (XDCP™)

Data Sheet February 6, 2008

Terminal V oltage 0V to 13.2V, 128 Taps I2C Interface

The Intersil ISL95311 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by an I

The potentiometer is implemented by a resistor array composed of 127 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The wiper of the potentiometer has an associated volatile Wiper Counter Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper on the resistor array through the switches. At power-up, the device recalls the contents of the IVR to the corresponding WR.

The device can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications, including:

• LCD contrast control

• Parameter and bias adjustments

• Industrial and automotive control

• Mechanical pot replacement

C interface.

Features

• Non-volatile solid-state potentiometer

•I

C serial interface

• DCP terminal voltage, 0V to +13.2V

• 128 wiper tap points - 0.8% resolution

- Wiper position stored in nonvolatile memory and recalled on power-up

• 127 resistive elements

- Temperature compensated

- Low wiper resistance 70Ω typical @ 3.3V

• Low power CMOS

- Standby current, 2µA @ V

= +3.6V

• High reliability

- Endurance, 200,000 data changes per bit

- Register data retention 50 years @ T ≤ +75°C

•R

values = 10kΩ, 50kΩ

TOTAL

• 10 Ld MSOP package

• Pb-free (RoHS compliant)

Pinout

ISL95311

(10-LD MSOP)

TOP VIEW

FN8084.1

Ordering Information

PART NUMBER

(Note) PART MARKING

ISL95311WIU10Z AJE 10k -40 to +85 10-Ld MSOP M10.118 ISL95311UIU10Z AJD 50k -40 to +85 10-Ld MSOP M10.118 Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

RESISTANCE OPTION

(Ω)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

TEMP RANGE

(°C)

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

SDA

GND

A1 A0V+5

1 2 3 4

PACKAGE

(Pb-Free) PKG. DWG. #

SCL

9 8

Block Diagram

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VCC

V+

SDA SCL

ISL95311

7-BIT

WIPER

(VOLATILE)

127

126

SDA SCL

CONTROL

AND

MEMORY

GND

SIMPLE BLOCK DIAGRAM

7-BIT

NONVOLATILE

MEMORY

STORE AND

RECALL

CONTROL

CIRCUITRY

SLAVE

ADDRESS

DECODE

ONE

128

DECODER

Pin Descriptions

PIN NUMBER SYMBOL DESCRIPTION

1 SDA Data I/O for I2C serial interface; it has an open drain output and may be wire-or’d with other open

drain active low outputs 2 GND Ground 3 VCC Positive logic supply voltage 4 A1 Address select pin used to set the slave address for the I 5 A0 Address select pin used to set the slave address for the I 6R 7R 8R

9 V+ Positive bias voltage for the potentiometer wiper control

10 SCL Clock input for the I

A fixed terminal for one end of the potentiometer resistor

The wiper terminal, which is equivalent to the movable terminal of a potentiometer

A fixed terminal for one end of the potentiometer resistor

C serial interface

125

124

TRANSFER

GATES

RESISTOR

ARRAY

DETAILED BLOCK DIAGRAM

C serial interface

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Absolute Maximum Ratings Recommended Operating Conditions

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on SDA, SCL, A0, A1

with respect to GND. . . . . . . . . . . . . . . . . . . .-0.3V to V

Voltage on V+ (referenced to GND). . . . . . . . . . . . . . . . . . . . +13.2V

ΔV = |V

, RL, RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

Power rating of DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mW

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

- V

(RH)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+

(RL)

+ 0.3V

Analog Specifications Over recommended operating conditions, unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS

TOTAL

H/CL/CW

LkgDCP

VOLTAGE DIVIDER MODE (0V @ RL; V+ @ RH; measured at RW, unloaded)

INL

(Note 6)

DNL

(Note 5)

ZSerror

(Note 3)

FSerror

(Note 4)

(Note 7)

RESISTOR MODE (Measurements between R

RINL

(Note 11)

RDNL

(Note 10)

Roffset

(Note 9)

(Note 12)

RH to RL Resistance W option 10 kΩ

U option 50 kΩ

to RL Resistance Tolerance -20 +20 %

RH Terminal Voltage VRL = 0V 0 V+ V Wiper Resistance V+ = 12.0V, wiper current = V+/R

Potentiometer Capacitance 10/10/25 pF

Leakage on DCP Pins Voltage at pin from GND to V+ 0.1 1 µA

Integral Non-Linearity W and U option -1 1 LSB

Differential Non-Linearity W and U option -0.5 0.5 LSB

Zero-Scale Error W option 0 1 7 LSB

U option 0 0.5 2

Full-Scale Error W option -7 -1 0 LSB

U option -2 -0.5 0

Ratiometric Temperature Coefficient DCP register set to 40 hex ±4 ppm/°C

and RL with RH not connected, or between RW and RH with RL not connected)

Integral Non-Linearity DCP register set between 20 hex and 7F hex;

monotonic over all tap positions

Differential Non-Linearity W and U option -0.5 0.5 MI

Offset DCP Register set to 00 hex, W option 0 1 7 MI

DCP Register set to 00 hex, U option 0 0.5 2

Resistance Temperature Coefficient DCP register set between 20 hex and 7F hex ±45 ppm/°C

Temperature Range (Industrial). . . . . . . . . . . . . . . . .-40°C to +85°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 13.2V

Wiper current of DCP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

MIN

(Note 15)

TOTAL

-1.0 1.0 MI

TYP

(Note 1)

70 200 Ω

MAX

(Note 15) UNIT

(Note 2)

(Note 8)

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Operating Specifications Over the recommended operating conditions unless otherwise specified.

MIN

SYMBOL PARAMETER TEST CONDITIONS

CC1

CC2

V+

LkgDig

DCP

Vpor Power-On Recall Voltage V

Ramp VCC Ramp Rate 0.2 V/ms

EEPROM SPECS

SERIAL INTERFACE SPECS

Hysteresis

Cpin A0, A1, SDA, and SCL Pin

SCL

BUF

LOW

HIGH

SU:STA

HD:STA

SU:DAT

VCC Supply Current, Volatile Write/read

VCC Supply Current, Nonvolatile Write

VCC Current, Standby V

V+ Bias Current V+ = 13.2V, V Leakage Current, at Pins SDA, SCL,

A0, and A1 Pins

DCP Wiper Response Time SCL falling edge of last bit of DCP data byte to

Power-Up Delay VCC above Vpor, to DCP initial value register

EEPROM Endurance 200,000 Cycles EEPROM Retention Temperature ≤ +75°C 50 Years

A0, A1, SDA, and SCL Input Buffer

LOW Voltage A0, A1, SDA, and SCL Input Buffer

HIGH Voltage SDA and SCL Input Buffer Hysteresis 0.05*

SDA Output Buffer LOW Voltage,

Sinking 4mA

Capacitance SCL Frequency 400 kHz

Pulse Width Suppression Time at

SDA and SCL Inputs

SCL Falling E dge to SDA Output Data

Valid

Time the Bus Must be Free Before the

Start of a New Transmission

Clock LOW Time Measured at the 30% of VCC crossing 1300 ns Clock HIGH Time Measured at the 70% of VCC crossing 600 ns START Condition Set-up Time SCL rising edge to SDA falling edge; both

STAR T Condition Hold Time From SDA falling edge crossing 30% of VCC to

Input Data Set-up Time From SDA exiting the 30% to 70% of VCC

= 400kHz; SDA = Open; (for I2C, active,

SCL

read, and volatile write states only) f

= 400kHz; SDA = Open; (for I2C, active,

SCL

nonvolatile write states only)

= +5.5V, I2C interface in standby state 5 µA

= +3.6V, I2C interface in standby state 2 µA

= +5.5V 1 µA

Voltage at pin from GND to V

wiper change

range at which memory recall occurs 1.5 1.8 2.6 V

recall completed, and I state

Any pulse narrower than the max spec is suppressed

SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of V

SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of V the following START condition

crossing 70% of V

SCL falling edge crossing 70% of V

window, to SCL rising edge crossing 30% of V

C Interface in standby

window

during

(Note 15)

-10 10 µA

-0.3 0.3*

0.7* V

00.4V

1300 ns

600 ns

100 ns

TYP

(Note 1)

10 pF

MAX

(Note 15) UNIT

VCC+

1mA

3mA

1µs

3ms

0.3 V

50 ns

900 ns

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Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

MIN

SYMBOL PARAMETER TEST CONDITIONS

HD:DAT

SU:STO

HD:STO

(Note 14)

Input Data Hold Time From SCL rising edge crossing 30% of VCC to

SDA entering the 30% to 70% of V

STOP Condition Set-up time From SCL rising edge crossing 70% of VCC, to

SDA rising edge crossing 30% of V

STOP Condition Hold Time From SDA rising edge to SCL falling edge. Both

crossing 70% of V

Output Data Hold Time From SCL falling edge crossing 30% of VCC,

until SDA enters the 30% to 70% of V

SDA and SCL Rise Time From 30% to 70% of V

SDA and SCL Fall Time From 70% to 30% of V

(Note 14)

Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF

window

(Note 15)

0ns

600 ns

0ns

20 +

0.1 * Cb 20 +

0.1 * Cb

(Note 14)

Rpu

(Note 14)

SDA and SCL Bus Pull-Up Resistor Off-Chip

Maximum is determined by t For Cb = 400pF, max is about 2kΩ~2.5kΩ.

and tF,

1kΩ

For Cb = 40pF, max is about 15kΩ~20kΩ.

(Notes 13)

SU:A

HD:A

Non-Volatile Write Cycle Time 12 20 ms

A0, A1 Set-up Time Before START condition 600 ns A0, A1 Hold Time After STOP condition 600 ns

NOTES:

1. Typical values are for T

2. LSB: [V(R

– V(RW)0]/127. V(RW)

W)127

= +25°C and 3.3V supply voltage.

and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the

127

incremental voltage when changing from one tap to an adjacent tap.

3. ZS error = V(R

4. FS error = [V(R

5. DNL = [V(R

6. INL = V(R

W)i

----------------------------------------------------------------------------------------------

Max V RW()

/LSB.

W)0

– V+]/LSB.

W)127

– V(RW)

W)i

]/LSB-1, for i = 1 to 127. i is the DCP register setting.

i-1

– (i • LSB – V(RW)0) for i = 1 to 127.

Max V RW()

()Min V RW()

()–

()+[]2⁄

---------------- -

×=

125°C

for i = 16 to 120 decimal, T = -40°C to 85°C. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

– R

8. MI =

127

9. Roffset = R Roffset = R

10. RDNL = (R

11. RINL = [R

12.

----------------------------------------------------------------

|/127. R

/MI, when measuring between R

127

– R

)/MI, for i = 16 to 127.

i-1

– (MI • i) – R0]/MI, for i = 16 to 127.

Max Ri()Min Ri()–[]

Max Ri()Min Ri()+[]2⁄

and R0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively.

127

and RL.

and RH.

---------------- -

×=

125°C

for i = 16 to 127, T = -40°C to +85°C. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the temperature range.

is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a valid

13. t

STOP condition at the end of a Write sequence of a I

C serial interface Write operation, to the end of the self-timed internal non-volatile write

cycle.

14. Recommended operating limits and are not production tested.

15. Parts are 100% tested at +85°C. Over temperature limits established by characterization and are not production tested.

TYP

(Note 1)

MAX

(Note 15) UNIT

250 ns

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SDA vs SCL Timing

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ISL95311

SCL

SU:STA

(INPUT TIMING)

(OUTPUT TIMING)

SDA

A0, A1 Pin Timing

SCL

SDA IN

A0, A1

HD:STA

START

SU:A

SU:DAT

HIGH

CLK 1

LOW

HD:DAT

SU:STO

STOP

HD:A

BUF

Pin Descriptions

Potentiometer Pins R

and R

and RH are referenced to the relative position of the

wiper and not the voltage potential on the terminals. With WR set to 127, the wiper will be closest to R WR set to 00, the wiper is closest to R

RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR.

Bus Interface Pins

SERIAL DATA INPUT/OUTPUT (SDA)

The SDA is a bidirectional serial data input/output pin for the I2C interface. It receives device address, operation code, wiper register address and data from a I device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL.

SDA requires an external pull-up resistor, since it’s an open drain input/output.

SERIAL CLOCK (SCL)

This input is the serial clock of the I SCL requires an external pull-up resistor, since it’s an open

drain input.

, and with the

C external master

C serial interface.

DEVICE ADDRESS (A1–A0)

The Address inputs are used to set the least significant 2 bits of the 8-bit I

C interface slave address. A match in the slave address serial data stream must be made with the Address input pins in order to initiate communication with the ISL95311. A maximum of four ISL9531 1 devices may occupy

the I

C serial bus.

Principles of Operation

The ISL95311 is an integrated circuit incorporating one DCP with their associated register, non-volatile memory, and a

C serial interface providing direct communication between a host and the potentiometers and memory. The resistor array is comprised of 127 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch between that point and the wiper.

The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme.

The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions.

When the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the wiper is set to the value last stored.

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On applying power to the ISL95311, the VCC supply should have a monotonic ramp to the specified operating voltage. It is important that once V least 2.5V in less than 7.5ms (0.2V/ms). The ramp rate before and after these thresholds is not important.

must be applied prior to, or simultaneously, with V+.

Under no condition should V+ be applied without V the sequence of applying V+ and V not affect the proper recall of the wiper position, applying V+ before V before the electronic switch control signals are applied. This can result in multiple electronic switches being turned on, which could load the power supply and cause brief, unexpected potentiometer wiper settings.

To prevent unknown wiper positions on the ISL95311 on power-down, it is recommended that V+ turn off before or simultaneously with V off, the wiper position can remain unchanged from its previous setting or it can go to an undefined state.

powers the electronic switches of the DCP

reaches 1V that it increases to at

to the ISL95311 does

. If V+ remains on after VCC turns

. While

DCP Description

The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of the DCP are equivalent to the fixed terminals of a mechanical potentiometer (R intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by a 7-bit volatile Wiper Register (WR). When the WR contains all zeroes (00h), the wiper terminal (R When the WR contains all ones (7Fh), the wiper terminal (R

) is closest to its “High” terminal (RH). As the value of the

WR increases from all zeroes (00h) to all ones (7Fh), the wiper moves monotonically from the position closest to R the position closest to R between R resistance between R

While the ISL9531 1 is being powe red up, the WR is reset to 20h (64 decimal), which locates the R R

and RH. Soon after the power supply voltage becomes

large enough for reliable non-volatile memory reading, the ISL9531 1 reads the value store d on a non-volatile Initia l Value Register (IVR) and loads it into the WR.

The WR and IVR can be read from or written to directly using

the I

C serial interface as described in the following

sections.

and RL pins). The RW pin is connected to

) is closest to its “Low” terminal (RL).

. At the same time, the resistance

and RL increases monotonically, while the

and RW decreases monotonically.

at the center between

Memory Description

The ISL95311 contains 1 non-volatile byte know as the Initial Va lue Register (IVR). It is accessed by the I operations with Address 00h. The IVR contains the value which is loaded into the Volatile Wiper Register (WR) at power-up.

C interface

The volatile WR, and the non-volatile IVR of a DCP are accessed with the same address.

The Access Control Register (ACR) determines which word at address 00h is accessed (IVR or WR). The volatile ACR must be set as follows:

When the ACR is all zeroes, which is the default at power-up:

• A read operation to address 0 outputs the value of the

non-volatile IVR.

• A write operation to address 0 writes the identical values

to the WR and IVR of the DCP.

• When the ACR is 80h:

• A read operation to address 0 outputs the value of the

volatile WR.

• A write operation to address 0 only writes to the

volatile WR.

It is not possible to write to an IVR without writing the same value to its WR.

00h and 80h are the only values that should be written to address 2. All other values are reserved and must not be written to address 2.

TABLE 1. MEMORY MAP

ADDRESS NON-VOLATILE VOLATILE

2-ACR 1 Reserved 0IVRWR

WR: Wiper Register, IVR: Initial value Register.

The ISL95311 is pre-programmed with 40h in the IVR.

I2C Serial Interface

The ISL95311 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL95311 operates as a slave device in all applications.

All communication over the I sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 1). On power-up of the ISL95311, the SDA pin is in the input mode.

All I

C interface operations must begin with a START

condition, which is a HIGH to LOW transition of SDA while

C interface is conducted by

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SCL is HIGH. The ISL95311 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 1). A STAR T condition is ignored during the power-up sequence and during internal non-volatile write cycles.

All I

C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 1). A STOP condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. A STOP condition during a write operation to a non-volatile byte, initiates an internal non-volatile write cycle. The device enters its standby state when the internal non-volatile write cycle is completed.

An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 2).

The ISL95311 responds with an ACK after recognition of a START condition follo wed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL95311 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation

A valid Identification Byte contains 01010 as the five MSBs, and the following two bits matching the logic values present at pins A1, and A0. The LSB is in the Read/Write value is “1” for a Read operation, and “0” for a Write operation (see Table 2.)

bit. Its

The byte at address 02h determines if the Data Byte is to be written to volatile and/or non-volatile memory (see “Memory Description” on page 7).

Data Protection

A STOP condition also acts as a protection of non-volatile memory. A valid Identification Byte, Address Byte, and total number of SCL pulses act as a protection of both volatile and non-volatile registers. During a Write sequence, the Data Byte is loaded into an internal shift register as it is received. If the Address Byte is 0 or 2, the Data Byte is transferred to the Wiper Register (WR) or to the Access Control Register respectively, at the falling edge of the SCL pulse that loads the last bit (LSB) of the Data Byte. If the Address Byte is 0, and the Access Control Register is all zeros (default), then the STOP condition initiates the internal write cycle to non-volatile memory.

Read Operation

A Read operation consists of a three byte instruction followed by one or more Data Bytes (See Figure 4). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W the three bytes, the ISL95311 responds with an ACK; then the ISL95311 transmits the Data Byte. The master then terminates the read operation (issuing a STOP condition) following the last bit of the Data Byte (See Figure 4).

The byte at address 02h determines if the Data Bytes being read are from volatile or non-volatile memory. (see “Memory Description” on page 7.)

bit set to “1”. After each of

bit

LOGIC VALUES AT PINS A1, AND A0 RESPECTIVELY

01010A1A0R/W

(MSB) (LSB)

TABLE 2. DENTIFICATION BYTE FORMAT

Write Operation

A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition (see Figure 3). After each of the three bytes, the ISL95311 responds with an ACK. At this time, if the Data Byte is to be written only to volatile registers, then the device enters its standby state. If the Data Byte is to be written also to non-volatile memory, the ISL95311 begins its internal write cycle to non-volatile memory. During the internal non-volatile write cycle, the device ignores transitions at the SDA and SCL pins, and the SDA output is at a high impedance state. When the internal non-volatile write cycle is completed, the ISL9531 1 enters its standby state.

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SCL

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SDA

ISL95311

SCL FROM

MASTER

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

SIGNALS FROM

START DATA DATA STOP

STABLE CHANGE

DATA

STABLE

FIGURE 1. VALID DATA CHANGES, START, AND STOP CONDITIONS

81 9

HIGH IMPEDANCE

START ACK

FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER

WRITE

THE MASTER

T A

IDENTIFICATION

R T

BYTE

ADDRESS

BYTE

DATA BYTE

HIGH IMPEDANCE

T O P

SIGNALS

FROM THE

MASTER

SIGNAL AT SDA

SIGNALS FROM

THE SLAVE

SIGNAL AT SDA

SIGNALS FROM

THE ISL95311

S T A

IDENTIFICATION

BYTE WITH

R/W

0011

0000A

0000

A C K

FIGURE 3. BYTE WRITE SEQUENCE

S T A

IDENTIFICATION

R T

A C K

BYTE WITH

R/W

= 1

01011

ADDRESS

= 0

00 0000 00 0A

1A0

A C K

BYTE

FIGURE 4. READ SEQUENCE

1A0

A C K

FIRST READ

DATA BYTE

A C K

LAST READ DATA BYTE

S T O P

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Communicating with the ISL95311

There are 3 register addresses in the ISL95311, of which two can be used. Address 00h and address 02h are used to control the device. Address 01h is reserved and should not be used. Address 00h contains the nonvolatile Initial Value Register (IVR), and the volatile Wiper Register (WR). Address 02h contains only a volatile word and is used as a pointer to either the IVR or WR. See Table 1.

The Access Control Register (ACR) is volatile and is at address 02h. It is 8-bits, and only the MSB is significant, all other bits should be zero (0). The ACR controls which word is accessed at register 00h as follows:

00h = Nonvolatile IVR 80h = Volatile WR All other bits of the ACR should be written to as zeros. Only

the MSB can be either 0 or 1. Power-up default for this address is 00h.

Example 1

WRITING A NEW VALUE (77H) TO THE IVR:

The ISL95311 has a single potentiometer . The wiper of the potentiometer is controlled dire ctl y by th e WR. Writes and reads can be made directly to this register to control and monitor the wiper position without any nonvolatile memory changes. This is done by setting address 02h to data 80h, then writing the data.

The nonvolatile IVR stores the power-up value of the wiper. On power-up, the contents of the IVR are transferred to the WR.

To write to the IVR, first address 02h is set to data 00h, then the data is written. Writing a new value to the IVR register will set a new power-up position for the wiper. Also, writing to this register will load the same value into the WR as the IVR. So, if a new value is loaded into the IVR, not only will the non-volatile IVR change, but the WR will also contain the same value after the write, and the wiper position will change. Reading from the IVR will not change the WR, if its contents are different.

Write to ACR first

01010000A00000010A00000000A

Then, write to IVR

01010000A00000000A01110111A

(Note that the WR will also reflect this new value since both registers get written to at the same time)

Example 2

READING FROM THE WR:

Write to the ACR first (to index the WR)

01010000A00000010A00000010A

Then, Set the WR address

01010000A00000000A

Read from the WR

01010001Axxxxxxx

Notes: A = acknowledge, x = data bit read

FN8084.1

February 6, 2008

ISL95311

www.BDTIC.com/Intersil

Mini Small Outline Plastic Packages (MSOP)

EE1

INDEX

AREA

AA1A2

-H-

SIDE VIEW

TOP VIEW

NOTES:

1. These package dimensions are within allowable dimensions of JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only

-B-

0.20 (0.008) A

GAUGE PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING PLANE

0.20 (0.008) C

- H -

4X θ

END VIEW

-B-

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.007 0.011 0.18 0.27 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.020 BSC 0.50 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N10 107

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

Rev. 0 12/02

NOTESMIN MAX MIN MAX

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8084.1

February 6, 2008

intersil ISL95311 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual