intersil ISL95311 DATA SHEET

®

www.BDTIC.com/Intersil

ISL95311

Digitally Controlled Potentiometer (XDCP™)

Data Sheet February 6, 2008

Terminal V oltage 0V to 13.2V, 128 Taps I2C
Interface

The Intersil ISL95311 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by an I

The potentiometer is implemented by a resistor array
composed of 127 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The wiper of the
potentiometer has an associated volatile Wiper Counter
Register (WR) and a non-volatile Initial Value Register (IVR)
that can be directly written to and read by the user. The
contents of the WR controls the position of the wiper on the
resistor array through the switches. At power-up, the device
recalls the contents of the IVR to the corresponding WR.

The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications, including:

• LCD contrast control

• Parameter and bias adjustments

• Industrial and automotive control

• Mechanical pot replacement

2

C interface.

Features

• Non-volatile solid-state potentiometer

2

•I

C serial interface

• DCP terminal voltage, 0V to +13.2V

• 128 wiper tap points - 0.8% resolution

- Wiper position stored in nonvolatile memory and
recalled on power-up

• 127 resistive elements

- Temperature compensated

- Low wiper resistance 70Ω typical @ 3.3V

• Low power CMOS

- Standby current, 2µA @ V

= +3.6V

CC

• High reliability

- Endurance, 200,000 data changes per bit

- Register data retention 50 years @ T ≤ +75°C

•R

values = 10kΩ, 50kΩ

TOTAL

• 10 Ld MSOP package

• Pb-free (RoHS compliant)

Pinout

ISL95311

(10-LD MSOP)

TOP VIEW

FN8084.1

Ordering Information

PART NUMBER

(Note) PART MARKING

ISL95311WIU10Z AJE 10k -40 to +85 10-Ld MSOP M10.118
ISL95311UIU10Z AJD 50k -40 to +85 10-Ld MSOP M10.118
Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.

1

RESISTANCE OPTION

(Ω)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved

TEMP RANGE

(°C)

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

SDA

GND

V

CC

A1
A0V+5

1
2
3
4

PACKAGE

(Pb-Free) PKG. DWG. #

SCL

10

9
8

R

L

7

R

W

6

R

H

Block Diagram

www.BDTIC.com/Intersil

VCC

V+

SDA
SCL

ISL95311

7-BIT

WIPER

REGISTER

(VOLATILE)

127

126

R

H

SDA
SCL

CONTROL

A1

A0

AND

MEMORY

GND

SIMPLE BLOCK DIAGRAM

R

H

7-BIT

R

W

R

L

A1

A0

NONVOLATILE

MEMORY

STORE AND

RECALL

CONTROL

CIRCUITRY

SLAVE

ADDRESS

DECODE

ONE

OF

128

DECODER

Pin Descriptions

PIN NUMBER SYMBOL DESCRIPTION

1 SDA Data I/O for I2C serial interface; it has an open drain output and may be wire-or’d with other open

drain active low outputs
2 GND Ground
3 VCC Positive logic supply voltage
4 A1 Address select pin used to set the slave address for the I
5 A0 Address select pin used to set the slave address for the I
6R
7R
8R

H

W

L

9 V+ Positive bias voltage for the potentiometer wiper control

10 SCL Clock input for the I

A fixed terminal for one end of the potentiometer resistor

The wiper terminal, which is equivalent to the movable terminal of a potentiometer

A fixed terminal for one end of the potentiometer resistor

2

C serial interface

125

124

TRANSFER

GATES

2

1

0

RESISTOR

ARRAY

DETAILED BLOCK DIAGRAM

2

C serial interface

2

C serial interface

R

L

R

W

2

FN8084.1

February 6, 2008

ISL95311

www.BDTIC.com/Intersil

Absolute Maximum Ratings Recommended Operating Conditions

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on SDA, SCL, A0, A1

with respect to GND. . . . . . . . . . . . . . . . . . . .-0.3V to V

Voltage on V+ (referenced to GND). . . . . . . . . . . . . . . . . . . . +13.2V

ΔV = |V

, RL, RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+

R

H

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

V

CC

Power rating of DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mW

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

- V

(RH)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+

(RL)

CC

+ 0.3V

Analog Specifications Over recommended operating conditions, unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS

R

TOTAL

V

RH

R

C

H/CL/CW

I

LkgDCP

VOLTAGE DIVIDER MODE (0V @ RL; V+ @ RH; measured at RW, unloaded)

INL

(Note 6)

DNL

(Note 5)

ZSerror

(Note 3)

FSerror

(Note 4)

TC

(Note 7)

RESISTOR MODE (Measurements between R

RINL

(Note 11)

RDNL

(Note 10)

Roffset

(Note 9)

TC

(Note 12)

RH to RL Resistance W option 10 kΩ

U option 50 kΩ

to RL Resistance Tolerance -20 +20 %

R

H

RH Terminal Voltage VRL = 0V 0 V+ V
Wiper Resistance V+ = 12.0V, wiper current = V+/R

W

Potentiometer Capacitance 10/10/25 pF

Leakage on DCP Pins Voltage at pin from GND to V+ 0.1 1 µA

Integral Non-Linearity W and U option -1 1 LSB

Differential Non-Linearity W and U option -0.5 0.5 LSB

Zero-Scale Error W option 0 1 7 LSB

U option 0 0.5 2

Full-Scale Error W option -7 -1 0 LSB

U option -2 -0.5 0

Ratiometric Temperature Coefficient DCP register set to 40 hex ±4 ppm/°C

V

and RL with RH not connected, or between RW and RH with RL not connected)

W

Integral Non-Linearity DCP register set between 20 hex and 7F hex;

monotonic over all tap positions

Differential Non-Linearity W and U option -0.5 0.5 MI

Offset DCP Register set to 00 hex, W option 0 1 7 MI

DCP Register set to 00 hex, U option 0 0.5 2

Resistance Temperature Coefficient DCP register set between 20 hex and 7F hex ±45 ppm/°C

R

Temperature Range (Industrial). . . . . . . . . . . . . . . . .-40°C to +85°C

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 13.2V

Wiper current of DCP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

MIN

(Note 15)

TOTAL

-1.0 1.0 MI

TYP

(Note 1)

70 200 Ω

MAX

(Note 15) UNIT

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 8)

(Note 8)

(Note 8)

3

FN8084.1

February 6, 2008

ISL95311

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified.

MIN

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

CC2

I

SB

I

V+

I

LkgDig

t

DCP

Vpor Power-On Recall Voltage V

Ramp VCC Ramp Rate 0.2 V/ms

V

CC

t

D

EEPROM SPECS

SERIAL INTERFACE SPECS

V

V

IH

Hysteresis

V

OL

Cpin A0, A1, SDA, and SCL Pin

f

SCL

t

IN

t

AA

t

BUF

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

t

SU:DAT

VCC Supply Current, Volatile
Write/read

VCC Supply Current, Nonvolatile
Write

VCC Current, Standby V

V+ Bias Current V+ = 13.2V, V
Leakage Current, at Pins SDA, SCL,

A0, and A1 Pins

DCP Wiper Response Time SCL falling edge of last bit of DCP data byte to

Power-Up Delay VCC above Vpor, to DCP initial value register

EEPROM Endurance 200,000 Cycles
EEPROM Retention Temperature ≤ +75°C 50 Years

A0, A1, SDA, and SCL Input Buffer

IL

LOW Voltage
A0, A1, SDA, and SCL Input Buffer

HIGH Voltage
SDA and SCL Input Buffer Hysteresis 0.05*

SDA Output Buffer LOW Voltage,

Sinking 4mA

Capacitance
SCL Frequency 400 kHz

Pulse Width Suppression Time at

SDA and SCL Inputs

SCL Falling E dge to SDA Output Data

Valid

Time the Bus Must be Free Before the

Start of a New Transmission

Clock LOW Time Measured at the 30% of VCC crossing 1300 ns
Clock HIGH Time Measured at the 70% of VCC crossing 600 ns
START Condition Set-up Time SCL rising edge to SDA falling edge; both

STAR T Condition Hold Time From SDA falling edge crossing 30% of VCC to

Input Data Set-up Time From SDA exiting the 30% to 70% of VCC

f

= 400kHz; SDA = Open; (for I2C, active,

SCL

read, and volatile write states only)
f

= 400kHz; SDA = Open; (for I2C, active,

SCL

nonvolatile write states only)

= +5.5V, I2C interface in standby state 5 µA

CC

= +3.6V, I2C interface in standby state 2 µA

V

CC

= +5.5V 1 µA

CC

Voltage at pin from GND to V

wiper change

range at which memory recall occurs 1.5 1.8 2.6 V

CC

recall completed, and I
state

Any pulse narrower than the max spec is
suppressed

SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of V

SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of V
the following START condition

crossing 70% of V

SCL falling edge crossing 70% of V

window, to SCL rising edge crossing 30% of
V

CC

CC

CC

2

C Interface in standby

window

CC

during

CC

CC

(Note 15)

-10 10 µA

-0.3 0.3*

0.7*
V

CC

V

CC

00.4V

1300 ns

600 ns

600 ns

100 ns

TYP

(Note 1)

10 pF

MAX

(Note 15) UNIT

V

VCC+

1mA

3mA

1µs

3ms

V

CC

V

0.3
V

50 ns

900 ns

4

FN8084.1

February 6, 2008