The ISL9440CEVAL1Z evaluation board features the
ISL9440C. The ISL9440C is quad-output controller that
integrates three PWM synchronous buck controllers and one
low-dropout linear regulator controller. The ISL9440C offers
programmable soft-start, independent enable functions and
integrates OV/OC/OT protection. The current mode control
architecture and internal compensation network keep
peripheral component counts minimized. 600kHz switching
frequency can minimize inductor size while the strong gate
driver is able to deliver 12A to each PWM channel.
Table 1 shows the difference in terms of ISL944xx family
features.
The ISL9440CEVAL1Z is easy to set up to evaluate the
performance of the ISL9440C. Please refer to the “Electrical
Specifications” for typical performance summary.
SOFT-STARTING
TIME
(ms)
1
FIGURE 1. ISL9440CEVAL1Z EVALUATION BOARD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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| Intersil (and design) is a registered trademark of Intersil Americas Inc.
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Copyright Intersil Americas Inc. 2009. All Rights Reserved
Page 2
Application Note 1482
Electrical SpecificationsRecommended operation conditions unless otherwise noted. Refer to schematic and typical
performance curves.
PARAMETERTEST CONDITIONSMINTYPMAXUNITS
V
IN
V
10.971.001.03V
OUT
23.253.323.4V
V
OUT
V
34.855.05.15V
OUT
V
42.432.502.57V
OUT
PWM1 Rated CurrentVIN =12V , TA = +25°C, No forced airflow, All three PWM
PWM2 Rated Current67A
PWM3 Rated Current45A
LDO Rated CurrentR7 = 0Ω, R4 is not populated0.81.0A
V
1 Peak-to-Peak RippleV
OUT
V
2 Peak-to-Peak Ripple59.6mV
OUT
V
3 Peak-to-Peak Ripple66.5mV
OUT
All outputs are in regulation6.01216V
67A
outputs are fully loaded
= 12V, All three PWM outputs are fully loaded,
IN
Oscilloscope is with full bandwidth
19.8mV
P-P
P-P
P-P
What’s Inside
The Evaluation Board Kit contains the following materials:
• The ISL9440CEVAL1Z
• The ISL9440B, ISL9440C datasheet
• This EVAL KIT document
Recommended Equipment
The following materials are recommended to perform
testing:
• 0V to 20V Power Supply with at least 10A Source Current
Capability
• Three Electronic Loads Capable of Sinking Current up to 7A
• Digital Multimeters (DMMs)
• 100MHz Quad-Trace Oscilloscope
• Signal Generator (for load transient tests)
Quick Test Guide
1. Ensure that the circuit is correctly connected to the supply
and electronic loads prior to applying any power. Please
refer to Figure 2 for proper set-up.
2. Connect Jumpers J3, J4 and J5 in the ENx positions.
3. Turn on the power supply
4. Adjust input voltage VIN within the sp ecified range and
observe output voltage. The output voltage variation
should be within 3%.
5. Adjust load current within the specified range and
observe output voltage. The output voltage variation
should be within 3%.
6. Use oscilloscope to observe output voltage ripple and
Phase node ringing. For accurate measurement, refer to
Figure 3 for proper test set-up.
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Page 3
Application Note 1482
V
+
_
A
+ VIN -
V
V
V
Vo2
Vo3
Vo1
_
+
_
+
+ -
_
+
+ -
Io2
A
Io3
Io1
A
LOADLOADLOAD
_
+
FIGURE 2. PROPER TEST SET-UP
OUTPUT CAP
OUTPUT CAP
OUTPUT CAP
OR MOSFET
OR MOSFET
OR MOSFET
FIGURE 3. PROPER PROBE SET-UP TO MEASURE OUTPUT
RIPPLE AND PHASE NODE RINGING
Load Transient Circuit Set-up
1. Select a SOIC8 N-Channel MOSFET with VDSS
breakdown > 20V.
2. Install the load transient circuit as indicated on the
schematic. Refer to Figure 4 for detail.
A
3. R27, R22 and R25 are 10kΩ resistors for discharging the
MOSFET gates.
4. R26, R23 and R24 are current sensing resistors to
monitor the load step. For accurate measurement, please
use 5% tolerance sensing resistor or better. To alleviate
thermal stress, use 0.1Ω or smaller resistance. The
resistance of the sensing resistors sets the current scale
on the oscilloscope.
5. Apply pulse square waveform across R27, R22 or R25.
The duty cycle of the pulse waveform should be small
(<5%) to limit thermal stress on current sensing resistor
and the MOSFETs (M8, M6 or M7)
6. The amplitude of the clock sets the current step
amplitude. Adjust the clock amplitude and slew rate to set
the current step and slew rate.
7. Monitor overshoot and undershoot at corresponding
output.
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Page 4
Application Note 1482
.
OPT. LOAD TRAN.
OPT
M8
R26 OPT
FIGURE 4. LOAD TRANSIENT CIRCUIT FOR PWM1
Typical Evaluation Board Performance CurvesV
90
VIN = 9VDC
85
80
75
70
65
60
EFFICIENCY (%)
55
50
45
40
08
VIN = 16VDC
1234567
FIGURE 5. PWM1 EFFICIENCY vs LOAD (V
VIN = 12VDC
LOAD CURRENT (A)
= 1.0V)FIGURE 6. PWM2 EFFICIENCY vs LOAD (VO = 3.3V)
O
R27
OPT
= 12V, Unless Otherwise Noted.
IN
100
VIN = 9VDC
95
90
85
80
75
70
EFFICIENCY (%)
65
60
55
50
081234567
VIN = 16VDC
VIN = 12VDC
LOAD CURRENT (A)
100
VIN = 9VDC
95
90
VIN = 12VDC
LOAD CURRENT (A)
EFFICIENCY (%)
85
80
75
70
65
60
55
50
0246531
VIN = 16VDC
FIGURE 7. PWM3 EFFICIENCY vs LOAD (V
4
V
(AC), 10mV/DIV
OUT1
500n
s
= 5.0V)FIGURE 8. PWM1 OUTPUT RIPPLE UNDER MAX LOAD
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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Page 9
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ISL9440CEVAL1Z PCB Layout
FIGURE 15. TOP COMPONENTS
FIGURE 16. TOP LAYER
Application Note 1482
Page 10
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FIGURE 17. SECOND LAYER (SOLID GROUND)
FIGURE 18. THIRD LAYER
ISL9440CEVAL1Z PCB Layout (Continued)
Application Note 1482
Page 11
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FIGURE 19. BOTTOM LAYER (MIRRORED)
FIGURE 20. BOTTOM COMPONENTS (MIRRORED)
ISL9440CEVAL1Z PCB Layout (Continued)
Application Note 1482
Page 12
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