intersil ISL9200 DATA SHEET

®
ISL9200
Data Sheet October 4, 2005
Charging System Safety Circuit
The ISL9200 is an integrated circuit (IC) optimized to provide a Li-ion battery redundant safety protection from failures of a charging system. The IC monitors the input voltage, the battery voltage, and the charge current. When any of the three parameters exceeds its limit, the IC turns off an internal P-channel MOSFET to remove the power from the charging system. In addition to the above protected parameters, the IC also monitors its own internal temperature and turns off the P-channel MOSFET when the die temperature exceeds 140°C. Together with the battery charger IC and the protection module in a battery pack, the charging system using the ISL9200 has triple-level protection and is two-fault tolerant.
The IC is designed to turn on the internal PFET slowly to avoid inrush current at power-up but will turn off the PFET quickly when input overvoltage is detected, in order to remove the power before any damage occurs. The ISL9200 has a logic warning output to indicate the fault and an enable input to allow the system to remove the input power.
Ordering Information
PAR T
PAR T #
ISL9200IRZ* (Note)
ISL9200EVAL1 ISL9200 Evaluation Board
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
MARKING
00Z
TEMP.
RANGE (°C) PACKAGE
-40 to 85 12 Ld 4x3 DFN (Pb-free)
PKG.
DWG. #
L12.4x3
Typical Application Circuit
FN9241.0
Features
• Fully Integrated Protection Circuit for Three Protection Var iable s
- User Programmable Overcurrent Protection Threshold
- Input Overvoltage Protection in Less Than 1µs
- Battery Overvoltage Protection
• High Immunity of False Triggering Under Transients
• High Accuracy Protection Thresholds
• Warning Output to Indicate the Occurrence of Faults
• Enable Input
• Thermal Enhanced DFN Package
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Cell Phones
• Digital Still Cameras
• PDAs and Smart Phones
• Portable Instruments
• Desktop Chargers
Related Literature
• Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)”
• Technical Brief TB379 “Thermal Characterization of Packaged Semiconductor Devices”
• Technical Brief TB389 “PCB Land Pattern Design and Surface Mount Guidelines for QFN Packages”
Pinout
ISL9200 (4x3 DFN)
TOP VIEW
INPUT
R
C
ILIM
VIN
VIN
1
ISL9200
ILIM
GND
OUT
VB
EN
WRN
1
ISL6292
BATTERY
CHARGER
R
VB
BATTERY
PAC K
+
NOTE: EPAD must be electrically connected to the GND pin.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
1
2
VIN
3
GND
4
WRN
NC
5
NC EN
6 7
Copyright © Intersil Americas Inc. 2005. All Rights Reserved.
EPAD
NC
12
11
OUT
10
OUT
9
ILIM
VB
8
ISL9200
Absolute Maximum Ratings (Reference to GND) Thermal Information
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 30V
Output and VB Pin (OUT, VB) (Note 1) . . . . . . . . . . . . . . . -0.3 to 7V
Other Pins (ILIM, WRN
, EN) . . . . . . . . . . . . . . . . . . . . . -0.3 to 5.5V
ESD Rating
Human Body Model (Per JESD22-A114-B) . . . . . . . . . . . . .3000V
Machine Model (Per EIA/JESD22 A115-A) . . . . . . . . . . . . . .200V
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
Supply Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3V to 6.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The maximum voltage rating for the VB pin under continuous operating conditions is 5.5V. All other pins are allowed to operate continuously at the absolute maximum ratings.
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
2. θ
JA
Tech Brief TB379.
, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
3. θ
JC
Electrical Specifications Typical values are tested at VIN = 5V and 25°C Ambient Temperature, maximum and minimum values are
guaranteed over the recommended operating conditions, unless otherwise noted.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
POWER-ON RESET
Rising VIN Threshold V
POR Hysteresis - 100 - mV
VIN Bias Current I
VIN Bias Current When disabled 30 60 100 µA
PROTECTIONS
Input Overvoltage Protection (OVP) V
Input OVP Hysteresis - 60 100 mV
Input OVP Falling Threshold 6.55 - - V
Input OVP Propagation Delay --1µs
Overcurrent Protection I
Overcurrent Protection Blanking Time BT
Battery Overvoltage Protection Threshold V
Battery OVP Threshold Hysteresis 75 - mV
Battery OVP Falling Threshold 4.225 - - V
Battery OVP Blanking Time BT
VB Pin Leakage Current V
Over Temperature Protection Rising Threshold 140 - °C
Over Temperature Protection Falling Threshold - 90 - °C
LOGIC
Input Logic HIGH 1.5 - - V
EN
EN Input Logic LOW --0.4V
EN Internal Pull Down Resistor 100 200 400 k
WRN Output Logic Low Sink 5mA current - 0.35 0.8 V
WRN Output Logic High Leakage Current - - 1 µA
POWER MOSFET
On Resistance R
POR
VIN
OVP
OCP
OCP
BOVP
BOVP
DS(ON)
When enabled 0.75 0.9 1.05 mA
VVB = 3V, R
= 4.4V - 20 nA
VB
Measured at 500mA, 4.3V < V
Thermal Resistance (Notes 2, 3) θ
(°C/W) θJC (°C/W)
JA
4x3 DFN Package . . . . . . . . . . . . . . . . 41 3.5
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
2.4 2.58 2.7 V
6.65 6.8 7.0 V
= 25k 0.93 1.0 1.07 A
ILIM
- 170 - µs
4.325 4.4 4.475 V
180 - µs
< 6.5V - 250 450 m
IN
2
FN9241.0
October 4, 2005
ISL9200
Pin Descriptions
VIN (Pins 1, 2)
The input power source. The VIN can withstand 30V input.
GND (Pin 3)
System ground reference.
WRN (Pin 4)
WRN is an open-drain logic output that turns LOW when any protection event occurs.
NC (Pins 5, 6, 12)
No connection and must be left floating.
EN (Pin 7)
Enable input. Pull this pin to low or leave it floating to enable the IC and force it to high to disable the IC.
Typical Applications
INPUT
R
C
ILIM
1
VIN
ILIM
GND
ISL9200
OUT
VB
EN
WRN
ISL6292
BATTERY
CHARGER
R
VB
BATTERY
PACK
VB (Pin 8)
Battery voltage monitoring input. This pin is connected to the battery pack positive terminal via an isolation resistor.
ILIM (Pin 9)
Overcurrent protection threshold setting pin. Connect a resistor between this pin and GND to set the OCP threshold.
OUT (Pins 10, 11)
Output pin.
EPAD
The exposed pad at the bottom of the DFN package for enhancing thermal performance. Must be electrically connected to the GND pin.
PART DESCRIPTION
R
ILIM
R
VB
+
C1 1µF/16V X5R ceramic capacitor
25k
200k to 1M
Block Diagram
INPUT
VIN
OUT
Q
1
Q
2 Q
POR
PRE-REG
WRN
1. 2V
REF
Q
CP1
4
R
1
R
2
GND
FET
DRIV ER
LOGIC
CP2
CP3
Q
5
R
5
EN
3
EA
0.8V
R
3
R
4
ILIM
VB
BUF
I SL6292
BATT ERY
CHARGE R
R
ILIM
R
VB
+
FIGURE 1. BLOCK DIAGRAM
3
FN9241.0
October 4, 2005
ISL9200
Typical Operating Performance The test conditions for the Typical Operating Performance are: V
R
= 25.5kΩ, RVB = 200kΩ, Unless Otherwise Noted.
ILIM
VIN (1V/div)
OUT (1V/div)
Load Current
(200mA/div)
Time: 5ms/div
FIGURE 2. CAPTURED WAVEFORMS FOR POWER-UP. THE
OUTPUT IS LOADED WITH A 10 RESISTOR
Time: 200ms/div
VIN (2V/div)
FIGURE 3. CAPTURED WAVEFORMS WHEN THE INPUT
WRN (5V/div)
VOLTAGE STEPS FROM 6.5V TO 10.5V
VIN (2V/div)
= 5V, TA = 25°C,
IN
VIN (2V/div)
OUT (2V/div)
Time: 2µs/div
OUT (2V/div)
WRN (5V/div)
FIGURE 4. CAPTURED WAVEFORMS WHEN THE INPUT
GRADUALLY RISES TO THE INPUT OVERVOLTAGE THRESHOLD
VIN (2V/div)
ILIM (1V/div)
WRN (5V/div)
OUT (2V/div)
Time: 500µs/div
OUT (2V/div)
WRN (5V/div)
FIGURE 5. TRANSIENT WHEN THE INPUT VOLTAGE STEPS
FROM 7.5V TO 6.5V
Time: 20s/div
Time: 5ms/div
VIN (1V/div)
VB (1V/div)
OUT (1V/div)
WRN (5V/div)
FIGURE 6. TRANSIENT WAVEFORMS WHEN INPUT STEPS
FROM ZERO TO 9V
4
FIGURE 7. BATTERY OVERVOLTAGE PROTECTION. THE IC
IS LATCHED OFF AFTER 16 COUNTS OF PROTECTION. VB VOLTAGE VARIES BETWEEN
4.3V TO 4.5V
FN9241.0
October 4, 2005
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