intersil ISL90842 DATA SHEET

®
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Quad Digitally Controlled Variable Resistors
Data Sheet January 16, 2006
Low Noise, Low Power I2C® Bus, 256 Taps
The ISL90842 integrates four digitally controlled potentiometers (DCP) configured as variable resistors on a monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the
2
I
C bus interface. Each potentiometer has an associated Wiper Register (WR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper.
The DCPs can be used as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing.
FN8096.1
Features
• Four variable resistors in one package
• 256 resistor taps - 0.4% resolution
•I2C serial interface
• Wiper resistance: 70 typical @ 3.3V
• Standby current <5µA max
• Power supply: 2.7V to 5.5V
•50kΩ, 10kΩ total resistance
• 14 Lead TSSOP
• Pb-free plus anneal available (RoHS compliant)
Pinout
ISL90842
(14 LEAD TSSOP)
TOP VIEW
RW0
RH3
RW3
SCL
SDA
GND
RW2
RH2
1
2
3
4
5
6
7
14
RH0
13
VCC
12
A1
11
A0
10
RH1
9
RW1
8
Ordering Information
PART NUMBER PART MARKING
ISL90842UIV1427Z (Notes 1 & 2) 90842UI27Z 50K -40 to +85 14 Ld TSSOP (Pb-Free)
ISL90842WIV1427Z (Notes 1 & 2) 90842WI27Z 10K -40 to +85 14 Ld TSSOP (Pb-Free)
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-TK” suffix for Tape and Reel.
1
RESISTANCE OPTION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
()
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
TEMP RANGE
(°C) PACKAGE
Functional Diagram
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SCL
ISL90842
V
CC
R
H0
R
H1
R
H2
R
H3
Block Diagram
SDA
SCL
A1
A0
SDA
A0
A1
I2C INTERFACE
I2C
INTERFACE
GND R
POWER-UP,
INTERFACE,
CONTROL
AND STATUS
R
L
LOGIC
W0
R
L
V
CC
R
W1
WR3
WR2
WR1
WR0
R
L
R
W2
DCP3
DCP2
DCP1
DCP0
R
L
R
W3
R
H3
R
W3
*
R
H2
R
W2
*
R
H1
R
W1
*
R
H0
R
W0
*
GND
PINS OF EACH DCP ARE LEFT FLOATING
* THE R
L
Pin Descriptions
TSSOP PIN SYMBOL DESCRIPTION
1 RH3 “High” terminal of DCP3
2 RW3 “Wiper” terminal of DCP3
2
3SCLI
4 SDA Serial data I/O for the I
5 GND Device ground pin
6 RW2 “Wiper” terminal of DCP2
7 RH2 “High” terminal of DCP2
8 RW1 “Wiper” terminal of DCP1
9 RH1 “High” terminal of DCP1
10 A0 Device address for the I
11 A1 Device address for the I
12 VCC Power supply pin
13 RH0 “High” terminal of DCP0
14 RW0 “Wiper” terminal of DCP0
C interface clock
2
C interface
2
C interface
2
C interface
2
FN8096.1
January 16, 2006
ISL90842
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Absolute Maximum Ratings Recommended Operating Conditions
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any digital interface pin
with respect to GND . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
CC
Voltage at any DCP pin with
respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300°C
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
I
W
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level B at +85°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV Human Body Model
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Specifications Over recommended operating conditions unless otherwise stated.
SYMBOL PARAMETER TEST CONDITIONS MIN
R
TOTAL
R
C
H/CL/CW
I
LkgDCP
RESISTOR MODE (Measurements between R
RINL
(Note 5)
RDNL
(Note 4)
Roffset
(Note 3)
R
MATCH
(Note 6)
TC
(Note 7)
RH to RW resistance W option, wiper counter = 00h 10 k
U option, wiper counter = 00h 50 k
to RW resistance tolerance Wiper counter = 00h -20 +20 %
R
H
Wiper resistance VCC = 3.3V @ 25°C, wiper current =
W
Potentiometer capacitance (Note 15) 10/10/25 pF
Leakage on DCP pins (Note 15) Voltage at pin from GND to V
Integral non-linearity DCP register set between 20 hex and FF
Differential non-linearity -0.5 0.5 MI
Offset U option 0 1 7 MI
DCP to DCP matching Any two DCPs at the same tap position with
Resistance temperature coefficient DCP register set between 20 hex and FF hex ±45 ppm/°C
R
V
i and RHi, i = 0, 1, 2 or 3)
W
hex; monotonic over all tap positions
W option 0 0.5 2 MI
the same terminal voltages
+0.3
CC
CC
CC/RTOTAL
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
V
CC
Power rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
Wiper current of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA
TYP
(NOTE 1) MAX UNIT
70 200
CC
-1 1 MI
-2 2 MI
0.1 1 µA
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN
I
CC1
I
SB
I
LkgDig
VCC supply current (volatile write/ read)
VCC current (standby) V
Leakage current, at pins A0, A1, SDA, and SCL
f
= 400kHz; SDA = Open; (for I2C, active,
SCL
read and write states)
= +5.5V, I2C interface in standby state 5 µA
CC
= +3.6V, I2C interface in standby state 2 µA
V
CC
Voltage at pin from GND to V
CC
3
TYP
(NOTE 1) MAX UNIT
1mA
-10 10 µA
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January 16, 2006
ISL90842
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Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS MIN
t
DCP
(Note 8)
DCP wiper response time SCL falling edge of last bit of DCP data byte
to wiper change
SERIAL INTERFACE SPECS
V
A1, A0, SDA, and SCL input buffer
IL
-0.3 0.3*V
LOW voltage
V
IH
Hysteresis
(Note 8)
V
OL
(Note 8)
Cpin
(Note 8)
f
SCL
t
IN
(Note 8)
t
AA
(Note 8)
t
BUF
(Note 8)
A1, A0, SDA, and SCL input buffer HIGH voltage
SDA and SCL input buffer hysteresis 0.05*
SDA output buffer LOW voltage, sinking 4mA
A1, A0, SDA, and SCL pin capacitance
SCL frequency 400 kHz
Pulse width suppression time at SDA and SCL inputs
SCL falling edge to SDA output data valid
Time the bus must be free before the start of a new transmission
Any pulse narrower than the max spec is suppressed
SCL falling edge crossing 30% of V SDA exits the 30% to 70% of V
SDA crossing 70% of V condition, to SDA crossing 70% of V
during a STOP
CC
window
CC
CC
CC
, until
0.7*V
V
CC
00.4V
1300 ns
during the following START condition
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
Clock LOW time Measured at the 30% of VCC crossing 1300 ns
Clock HIGH time Measured at the 70% of VCC crossing 600 ns
START condition setup time SCL rising edge to SDA falling edge; both
crossing 70% of V
CC
START condition hold time From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of V
CC
Input data setup time From SDA exiting the 30% to 70% of VCC
600 ns
600 ns
100 ns window, to SCL rising edge crossing 30% of V
CC
Input data hold time From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of V
CC
0ns
window
t
SU:STO
t
HD:STO
t
DH
(Note 8)
t
R
STOP condition hold time From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of V
STOP condition hold time for read, or volatile only write
From SDA rising edge to SCL falling edge. Both crossing 70% of V
CC
Output data hold time From SCL falling edge crossing 30% of V
until SDA enters the 30% to 70% of V window
SDA and SCL rise time From 30% to 70% of V
CC
CC
CC
CC
(Note 8)
t
(Note 8)
Cb
(Note 8) Capacitive loading of SDA or SCL Total on-chip and off-chip 10 400 pF
Rpu
(Note 8)
SDA and SCL fall time From 70% to 30% of V
F
SDA and SCL bus pull-up resistor off­chip
Maximum is determined by t For Cb = 400pF, max is about 2~2.5k
CC
and t
R
F
600 ns
600 ns
0ns
,
20 +
0.1 * Cb
20 +
0.1 * Cb
1k
For Cb = 40pF, max is about 15~20k
TYP
(NOTE 1) MAX UNIT
s
CC
VCC+0.3 V
10 pF
50 ns
900 ns
250 ns
250 ns
CC
V
V
4
FN8096.1
January 16, 2006
ISL90842
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Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS MIN
t
SU:A
t
HD:A
A1 and A0 setup time Before START condition 600 ns
A1 and A0 hold time After STOP condition 600 ns
TYP
(NOTE 1) MAX UNIT
SDA vs SCL Timing
SCL
t
SU:STA
(INPUT TIMING)
(OUTPUT TIMING)
SDA
SDA
A0 and A1 Pin Timing
SCL
SDA IN
A0, A1
t
HD:STA
t
F
START
t
SU:DAT
t
SU:A
t
HIGH
CLK 1
t
LOW
t
HD:DAT
t
R
t
SU:STO
t
t
DH
AA
STOP
t
HD:A
t
BUF
NOTES:
1. Typical values are for T
|R
2. MI =
3. Roffset = R
4. RDNL = (R
5. RINL = [R
6. R
MATCH
7. for i = 32 to 255, T = -40°C to 85°C. Max ( ) is the maximum value of the resistance and Min ( ) is the
TC
– R
255
0
/ MI, when measuring between RW and RH.
255
– R
i
i-1
– (MI • i) – R0] / MI, for i = 32 to 255.
i
= (R
– R
i,x
Max Ri()Min Ri()[]
------------------------------------------------------------ --- -
R
Max Ri()Min Ri()+[]2
= 25°C and 3.3V supply voltage.
A
| / 255. R
and R0 are the measured resistances for the DCP register set to FF hex and 00 hex, respectively.
255
) / MI, for i = 32 to 255.
) / MI, for i = 0 to 255, x = 0 to 3 and y = 0 to 3.
i,y
---------------- -
×=
125°C
6
10
minimum value of the resistance over the temperature range.
8. This parameter is not 100% tested.
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FN8096.1
January 16, 2006
Typical Performance Curves
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ISL90842
160
140
VCC=2.7, T=-40°C
120
100
80
60
40
WIPER RESISTANCE (Ω)
VCC=5.5, T=-40°C
20
0
0 50 100 150 200 250
VCC=2.7, T=+85°C
VCC=5.5, T=+25°C
TAP POSITION (DECIMAL)
VCC=2.7, T=+25°C
VCC=5.5, T=+85°C
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[I(R
) = V
W
0.3
0.2
0.1
0
DNL (LSB)
-0.1
-0.2
-0.3 32 82 132 182 232
V
VCC=5.5, T=+85°C
/ R
CC
=5.5, T=+25°C
CC
VCC=2.7, T=-40°C
TAP POSITION (DECIMAL)
] FOR 50k (U)
TOTAL
=5.5, T=-40°C
V
CC
VCC=2.7, T=+25°C
VCC=2.7, T=+85°C
1.8
1.6
1.4
1.2
(µA)
CC
1
0.8
0.6
STANDBY I
0.4
0.2
0
2.7 3.2 3.7 4.2 4.7 5.2
+25°C
FIGURE 2. STANDBY I
0.5
0.3
0.1
-0.1
INL (LSB)
-0.3
-0.5 32 82 132 182 232
=2.7, T=+85°C
V
CC
VCC=5.5, T=+25°C
-40°C
(V)
V
CC
vs Vcc
CC
VCC=2.7, T=+25°C
VCC=5.5, T=-40°C
VCC=5.5, T=+85°C
TAP POSITION (DECIMAL)
+85°C
VCC=2.7,
T=-40°C
FIGURE 3. DNL vs TAP POSITION FOR 50k (U) FIGURE 4. INL vs TAP POSITION FOR 50k (U)
1.5
1
2.7V
0.5
CHANGE (%)
5.5V
0
TOTAL
-0.5
-1
END TO END R
-1.5
-40 -20 20 40 60 80
FIGURE 5. END TO END R
0
TEMPERATURE (°C)
% CHANGE vs
TOTAL
35
25
15
5
TC (ppm/°C)
-5
-15
-25 32 82 132 182 232
TAP POSITION (DECIMAL)
FIGURE 6. TC IN ppm
TEMPERATURE
6
FN8096.1
January 16, 2006
Typical Performance Curves (Continued)
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ISL90842
INPUT
OUTPUT
TAP POSITION = MID POINT R
=9.4K
TOTAL
FIGURE 7. FREQUENCY RESPONSE (2.2MHz) FIGURE 8. LARGE SIGNAL SETTLING TIME
Principles of Operation
The ISL90842 is an integrated circuit incorporating four DCPs with their associated registers, and an I interface providing direct communication between a host and the DCPs.
DCP Description
Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer. The R intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WR). Each DCP has its own WR. When the WR of a DCP contains all zeroes (WR<7:0>: 00h), its wiper terminal (R
) is closest to its RL terminal. When the WR of a
W
DCP contains all ones (WR<7:0>: FFh), its wiper terminal (R
) is furthest from the RH terminal. As the value of the
W
WR increases from all zeroes (00h) to all ones (255 decimal), the wiper moves monotonically from the position furthest from R
H
the resistance between R monotonically. Note that the R not connected (left floating).
While the ISL90842 is being powered up, all four WRs are reset to 80h (128 decimal), which locates R position which yields a rheostat setting that is about 1/2 of R
TOTAL
.
The WRs can be read or written directly using the I interface as described in the following sections. The I interface Address Byte has to be set to 00h, 01h, 02h, and 03h to access the WR of DCP0, DCP1, DCP2, and DCP3, respectively.
pin of each DCP is connected to
W
to a position closer to RH. At the same time,
and RW decreases
H
terminals for all four pots are
L
2
C serial
roughly at a
W
2
C serial
2
C
SCL
SIGNAL AT WIPER (WIPER UNLOADED MOVEMENT FROM ffh TO 00h)
I2C Serial Interface
The ISL90842 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL90842 operates as a slave device in all applications.
All communication over the I sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 9). On power-up of the ISL90842 the SDA pin is in the input mode.
2
All I
C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL90842 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure 9). A START condition is ignored during the power-up of the device.
2
All I
C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 9). A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode.
An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the
2
C interface is conducted by
receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 10).
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FN8096.1
January 16, 2006
ISL90842
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The ISL90842 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL90842 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 01010 as the five MSBs, and the following two bits matching the logic values present at pins A1 and A0. The LSB is the Read/Write
SCL
SDA
START DATA DATA STOP
FIGURE 9. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
bit. Its value is
STABLE CHANGE
“1” for a Read operation, and “0” for a Write operation (See Table 1).
TABLE 1. IDENTIFICATION BYTE FORMAT
Logic values at pins A1, and A0 respectively
01010A1A0R/W
(MSB) (LSB)
DATA
STABLE
81 9
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
SIGNALS FROM
SIGNAL AT SDA
SIGNALS FROM
HIGH IMPEDANCE
START ACK
FIGURE 10. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
S
THE MASTER
THE ISL90842
T A
IDENTIFICATION
R T
BYTE
00011
ADDRESS
BYTE
000 0A0A100000
A C K
A C K
FIGURE 11. BYTE WRITE SEQUENCE
DATA
BYTE
HIGH IMPEDANCE
S T
O
P
A C K
8
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SIGNALS
FROM THE
MASTER
SIGNAL AT SDA
SIGNALS FROM
THE SLAVE
S T A
IDENTIFICATION
R
BYTE WITH
T
R/W
00011
ADDRESS
=0
A C K
BYTE
0000 000 A1A0
A C K
FIGURE 12. READ SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL90842 responds with an ACK. At this time, the device enters its standby state (See Figure 11).
Read Operation
A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 12). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W Address Byte, a second START, and a second Identification byte with the R/W
bit set to “1”. After each of the three bytes, the ISL90842 responds with an ACK. Then the ISL90842 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a STOP condition) following the last bit of the last Data Byte (See Figure 12).
bit set to “0”, an
S T A
IDENTIFICATION
R
BYTE WITH
T
R/W
010110A1A0
A
A
C
C
K
=1
A C
FIRST READ
K
DATA BYTE
K
LAST READ
DATA BYTE
S T O P
The Data Bytes are from the registers indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 03h the pointer “rolls over” to 00h, and the device continues to output data for each ACK received.
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Packaging Information
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ISL90842
14-Lead Plastic, TSSOP, Package Code V14
.025 (.65) BSC
0° - 8°
.0075 (.19) .0118 (.30)
.193 (4.9) .200 (5.1)
.019 (.50) .029 (.75)
Detail A (20X)
.169 (4.3) .177 (4.5)
.041 (1.05)
.002 (.05) .006 (.15)
.010 (.25)
Gage Plane
Seating Plane
.252 (6.4) BSC
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN8096.1
January 16, 2006
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