intersil ISL90841 DATA SHEET

®

www.BDTIC.com/Intersil

Quad Digitally Controlled Potentiometers (XDCP™)

ISL90841

Data Sheet February 8, 2006

Low Noise, Low Power I2C® Bus, 256 Taps

The ISL90841 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.

The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the

2

I

C bus interface. Each potentiometer has an associated
Wiper Register (WR) that can be directly written to and read
by the user. The contents of the WR controls the position of
the wiper.

All four potentiometers have one terminal tied to GND. The
DCPs can be used as a resistor divider or as two-terminal
variable resistors in a wide variety of applications including
control, parameter adjustments, and signal processing.

FN8094.1

Features

• Four potentiometers in one package

• 256 resistor taps - 0.4% resolution

•I2C serial interface

• Wiper resistance: 70Ω typical @ 3.3V

• Standby current <5µA max

• Power supply: 2.7V to 5.5V

•50kΩ, 10kΩ total resistance

• 14 Lead TSSOP

• Pb-free plus anneal available (RoHS compliant)

Pinout

ISL90841

(14 LEAD TSSOP)

TOP VIEW

RW0

RH3

RW3

SCL

SDA

GND

RW2

RH2

1

2

3

4

5

6

7

14

RH0

13

VCC

12

A1

11

A0

10

RH1

9

RW1

8

Ordering Information

RESISTANCE OPTION

PART NUMBER PART MARKING

ISL90841UIV1427Z (Notes 1 & 2) 90841UI27Z 50K -40 to +85 14 Ld TSSOP (Pb-Free)

ISL90841WIV1427Z (Notes 1 & 2) 90841WI27Z 10K -40 to +85 14 Ld TSSOP (Pb-Free)

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “-TK” to suffix for Tape and Reel.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

(Ω)

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

TEMP RANGE

(°C) PACKAGE

Functional Diagram

www.BDTIC.com/Intersil

SCL

ISL90841

V

CC

R

H0

R

H1

R

H2

R

H3

Block Diagram

SDA

SCL

A1

A0

SDA

A0

A1

I2C INTERFACE

I2C

INTERFACE

GND R

POWER-UP,

INTERFACE,

CONTROL

AND STATUS

LOGIC

W0

R

W1

V

CC

WR3

WR2

WR1

WR0

R

W2

DCP3

DCP2

DCP1

DCP0

R

W3

R

H3

R

W3

R

H2

R

W2

R

H1

R

W1

R

H0

R

W0

GND

Pin Descriptions

TSSOP PIN SYMBOL DESCRIPTION

1 RH3 “High” terminal of DCP3

2 RW3 “Wiper” terminal of DCP3

2

3SCLI

4 SDA Serial data I/O for the I2C interface

5 GND Device ground pin

6 RW2 “Wiper” terminal of DCP2

7 RH2 “High” terminal of DCP2

8 RW1 “Wiper” terminal of DCP1

9 RH1 “High” terminal of DCP1

10 A0 Device address for the I

11 A1 Device address for the I2C interface

12 VCC Power supply pin

13 RH0 “High” terminal of DCP0

14 RW0 “Wiper” terminal of DCP0

C interface clock

2

C interface

2

FN8094.1

February 8, 2006

ISL90841

www.BDTIC.com/Intersil

Absolute Maximum Ratings Recommended Operating Conditions

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any digital interface pin

with respect to GND . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V

V

CC

Voltage at any DCP pin with

respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300°C

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level B at +85°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV Human Body Model

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

R

C

H/CL/CW

I

LkgDCP

VOLTAGE DIVIDER MODE (V

INL

(Note 6)

DNL

(Note 5)

ZSerror
(Note 3)

FSerror
(Note 4)

V

MATCH

(Note 7)

TC

(Note 8)

RESISTOR MODE (Measurements between R

RINL

(Note 12)

RDNL

(Note 11)

Roffset

(Note 10)

R

MATCH

(Note 13)

TC

(Note 14)

RH to GND resistance W option 10 kΩ

U option 50 kΩ

to GND resistance tolerance -20 +20 %

R

H

Wiper resistance VCC = 3.3V @ 25°C, wiper current =

W

Potentiometer capacitance (Note 15) 10/10/25 pF

Leakage on DCP pins (Note 15) Voltage at pin from GND to V

@ RHi; measured at RWi, unloaded; i = 0, 1, 2, or 3)

CC

Integral non-linearity -1 1 LSB

Differential non-linearity Monotonic over all tap positions -0.5 0.5 LSB

Zero-scale error W option 0 1 7 LSB

Full-scale error W option -7 -1 0 LSB

DCP to DCP matching Any two DCPs at same tap position, same

Ratiometric temperature coefficient DCP register set to 80 hex ±4 ppm/°C

V

Integral non-linearity DCP register set between 20 hex and FF

Differential non-linearity -0.5 0.5 MI

Offset W option 0 1 7 MI

DCP to DCP matching Any two DCPs at the same tap position with

Resistance temperature coefficient DCP register set between 20 hex and FF hex ±45 ppm/°C

R

V

U option 0 0.5 2

U option -2 -1 0

voltage at all RH terminals

i and RHi. i = 0, 1, 2 or 3)

W

hex; monotonic over all tap positions

U option 0 0.5 2 MI

the same terminal voltages

+0.3

CC

CC

CC/RTOTAL

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

V

CC

Power rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper current of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA

TYP

(NOTE 1) MAX UNIT

70 200 Ω

CC

-2 2 LSB

-1 1 MI

-2 2 MI

0.1 1 µA

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 9)

(Note 9)

(Note 9)

(Note 9)

(Note 9)

3

FN8094.1

February 8, 2006

ISL90841

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

SB

I

LkgDig

VCC supply current (volatile
write/read)

VCC current (standby) V

Leakage current, at pins A0, A1, SDA,
and SCL

t

DCP

(Note 15)

DCP wiper response time SCL falling edge of last bit of DCP data byte

SERIAL INTERFACE SPECS

V

V

Hysteresis

A1, A0, SDA, and SCL input buffer

IL

LOW voltage

A1, A0, SDA, and SCL input buffer

IH

HIGH voltage

SDA and SCL input buffer hysteresis 0.05*

(Note 15)

V

OL

(Note 15)

Cpin

(Note 15)

f

SCL

t

IN

(Note 15)

t

AA

(Note 15)

t

BUF

(Note 15)

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

t

HD:STO

SDA output buffer LOW voltage,
sinking 4mA

A1, A0, SDA, and SCL pin
capacitance

SCL frequency 400 kHz

Pulse width suppression time at SDA
and SCL inputs

SCL falling edge to SDA output data
valid

Time the bus must be free before the
start of a new transmission

Clock LOW time Measured at the 30% of VCC crossing 1300 ns

Clock HIGH time Measured at the 70% of VCC crossing 600 ns

START condition setup time SCL rising edge to SDA falling edge; both

START condition hold time From SDA falling edge crossing 30% of VCC

Input data setup time From SDA exiting the 30% to 70% of VCC

Input data hold time From SCL rising edge crossing 70% of VCC

STOP condition setup time From SCL rising edge crossing 70% of VCC,

STOP condition hold time for read, or
volatile only write

t

DH

(Note 15)

t

R

(Note 15)

Output data hold time From SCL falling edge crossing 30% of V

SDA and SCL rise time From 30% to 70% of V

f

= 400kHz; SDA = Open; (for I2C, active,

SCL

read and write states)

= +5.5V, I2C interface in standby state 5 µA

CC

V

= +3.6V, I2C interface in standby state 2 µA

CC

Voltage at pin from GND to V

CC

-10 10 µA

to wiper change

-0.3 0.3*V

0.7*V

V

CC

00.4V

Any pulse narrower than the max spec is
suppressed

SCL falling edge crossing 30% of V
SDA exits the 30% to 70% of V

SDA crossing 70% of V
condition, to SDA crossing 70% of V

during a STOP

CC

during the following START condition

window

CC

CC

CC

, until

1300 ns

600 ns

crossing 70% of V

CC

600 ns

to SCL falling edge crossing 70% of V

CC

100 ns
window, to SCL rising edge crossing 30% of
V

CC

0ns
to SDA entering the 30% to 70% of V
window

CC

600 ns

to SDA rising edge crossing 30% of V

From SDA rising edge to SCL falling edge;
both crossing 70% of V

CC

until SDA enters the 30% to 70% of V

CC

CC

CC

600 ns

,

0ns

window

CC

20 +

0.1 * Cb

TYP

(NOTE 1) MAX UNIT

1mA

1µs

CC

CC

VCC+0.3 V

10 pF

50 ns

900 ns

250 ns

V

V

4

FN8094.1

February 8, 2006