intersil ISL90841 DATA SHEET

®

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Quad Digitally Controlled Potentiometers (XDCP™)

ISL90841

Data Sheet February 8, 2006

Low Noise, Low Power I2C® Bus, 256 Taps

The ISL90841 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.

The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the

2

I

C bus interface. Each potentiometer has an associated
Wiper Register (WR) that can be directly written to and read
by the user. The contents of the WR controls the position of
the wiper.

All four potentiometers have one terminal tied to GND. The
DCPs can be used as a resistor divider or as two-terminal
variable resistors in a wide variety of applications including
control, parameter adjustments, and signal processing.

FN8094.1

Features

• Four potentiometers in one package

• 256 resistor taps - 0.4% resolution

•I2C serial interface

• Wiper resistance: 70Ω typical @ 3.3V

• Standby current <5µA max

• Power supply: 2.7V to 5.5V

•50kΩ, 10kΩ total resistance

• 14 Lead TSSOP

• Pb-free plus anneal available (RoHS compliant)

Pinout

ISL90841

(14 LEAD TSSOP)

TOP VIEW

RW0

RH3

RW3

SCL

SDA

GND

RW2

RH2

1

2

3

4

5

6

7

14

RH0

13

VCC

12

A1

11

A0

10

RH1

9

RW1

8

Ordering Information

RESISTANCE OPTION

PART NUMBER PART MARKING

ISL90841UIV1427Z (Notes 1 & 2) 90841UI27Z 50K -40 to +85 14 Ld TSSOP (Pb-Free)

ISL90841WIV1427Z (Notes 1 & 2) 90841WI27Z 10K -40 to +85 14 Ld TSSOP (Pb-Free)

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “-TK” to suffix for Tape and Reel.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

(Ω)

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

TEMP RANGE

(°C) PACKAGE

Functional Diagram

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SCL

ISL90841

V

CC

R

H0

R

H1

R

H2

R

H3

Block Diagram

SDA

SCL

A1

A0

SDA

A0

A1

I2C INTERFACE

I2C

INTERFACE

GND R

POWER-UP,

INTERFACE,

CONTROL

AND STATUS

LOGIC

W0

R

W1

V

CC

WR3

WR2

WR1

WR0

R

W2

DCP3

DCP2

DCP1

DCP0

R

W3

R

H3

R

W3

R

H2

R

W2

R

H1

R

W1

R

H0

R

W0

GND

Pin Descriptions

TSSOP PIN SYMBOL DESCRIPTION

1 RH3 “High” terminal of DCP3

2 RW3 “Wiper” terminal of DCP3

2

3SCLI

4 SDA Serial data I/O for the I2C interface

5 GND Device ground pin

6 RW2 “Wiper” terminal of DCP2

7 RH2 “High” terminal of DCP2

8 RW1 “Wiper” terminal of DCP1

9 RH1 “High” terminal of DCP1

10 A0 Device address for the I

11 A1 Device address for the I2C interface

12 VCC Power supply pin

13 RH0 “High” terminal of DCP0

14 RW0 “Wiper” terminal of DCP0

C interface clock

2

C interface

2

FN8094.1

February 8, 2006

ISL90841

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Absolute Maximum Ratings Recommended Operating Conditions

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any digital interface pin

with respect to GND . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V

V

CC

Voltage at any DCP pin with

respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300°C

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level B at +85°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV Human Body Model

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

R

C

H/CL/CW

I

LkgDCP

VOLTAGE DIVIDER MODE (V

INL

(Note 6)

DNL

(Note 5)

ZSerror
(Note 3)

FSerror
(Note 4)

V

MATCH

(Note 7)

TC

(Note 8)

RESISTOR MODE (Measurements between R

RINL

(Note 12)

RDNL

(Note 11)

Roffset

(Note 10)

R

MATCH

(Note 13)

TC

(Note 14)

RH to GND resistance W option 10 kΩ

U option 50 kΩ

to GND resistance tolerance -20 +20 %

R

H

Wiper resistance VCC = 3.3V @ 25°C, wiper current =

W

Potentiometer capacitance (Note 15) 10/10/25 pF

Leakage on DCP pins (Note 15) Voltage at pin from GND to V

@ RHi; measured at RWi, unloaded; i = 0, 1, 2, or 3)

CC

Integral non-linearity -1 1 LSB

Differential non-linearity Monotonic over all tap positions -0.5 0.5 LSB

Zero-scale error W option 0 1 7 LSB

Full-scale error W option -7 -1 0 LSB

DCP to DCP matching Any two DCPs at same tap position, same

Ratiometric temperature coefficient DCP register set to 80 hex ±4 ppm/°C

V

Integral non-linearity DCP register set between 20 hex and FF

Differential non-linearity -0.5 0.5 MI

Offset W option 0 1 7 MI

DCP to DCP matching Any two DCPs at the same tap position with

Resistance temperature coefficient DCP register set between 20 hex and FF hex ±45 ppm/°C

R

V

U option 0 0.5 2

U option -2 -1 0

voltage at all RH terminals

i and RHi. i = 0, 1, 2 or 3)

W

hex; monotonic over all tap positions

U option 0 0.5 2 MI

the same terminal voltages

+0.3

CC

CC

CC/RTOTAL

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

V

CC

Power rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper current of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA

TYP

(NOTE 1) MAX UNIT

70 200 Ω

CC

-2 2 LSB

-1 1 MI

-2 2 MI

0.1 1 µA

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 9)

(Note 9)

(Note 9)

(Note 9)

(Note 9)

3

FN8094.1

February 8, 2006

ISL90841

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Operating Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

SB

I

LkgDig

VCC supply current (volatile
write/read)

VCC current (standby) V

Leakage current, at pins A0, A1, SDA,
and SCL

t

DCP

(Note 15)

DCP wiper response time SCL falling edge of last bit of DCP data byte

SERIAL INTERFACE SPECS

V

V

Hysteresis

A1, A0, SDA, and SCL input buffer

IL

LOW voltage

A1, A0, SDA, and SCL input buffer

IH

HIGH voltage

SDA and SCL input buffer hysteresis 0.05*

(Note 15)

V

OL

(Note 15)

Cpin

(Note 15)

f

SCL

t

IN

(Note 15)

t

AA

(Note 15)

t

BUF

(Note 15)

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

t

HD:STO

SDA output buffer LOW voltage,
sinking 4mA

A1, A0, SDA, and SCL pin
capacitance

SCL frequency 400 kHz

Pulse width suppression time at SDA
and SCL inputs

SCL falling edge to SDA output data
valid

Time the bus must be free before the
start of a new transmission

Clock LOW time Measured at the 30% of VCC crossing 1300 ns

Clock HIGH time Measured at the 70% of VCC crossing 600 ns

START condition setup time SCL rising edge to SDA falling edge; both

START condition hold time From SDA falling edge crossing 30% of VCC

Input data setup time From SDA exiting the 30% to 70% of VCC

Input data hold time From SCL rising edge crossing 70% of VCC

STOP condition setup time From SCL rising edge crossing 70% of VCC,

STOP condition hold time for read, or
volatile only write

t

DH

(Note 15)

t

R

(Note 15)

Output data hold time From SCL falling edge crossing 30% of V

SDA and SCL rise time From 30% to 70% of V

f

= 400kHz; SDA = Open; (for I2C, active,

SCL

read and write states)

= +5.5V, I2C interface in standby state 5 µA

CC

V

= +3.6V, I2C interface in standby state 2 µA

CC

Voltage at pin from GND to V

CC

-10 10 µA

to wiper change

-0.3 0.3*V

0.7*V

V

CC

00.4V

Any pulse narrower than the max spec is
suppressed

SCL falling edge crossing 30% of V
SDA exits the 30% to 70% of V

SDA crossing 70% of V
condition, to SDA crossing 70% of V

during a STOP

CC

during the following START condition

window

CC

CC

CC

, until

1300 ns

600 ns

crossing 70% of V

CC

600 ns

to SCL falling edge crossing 70% of V

CC

100 ns
window, to SCL rising edge crossing 30% of
V

CC

0ns
to SDA entering the 30% to 70% of V
window

CC

600 ns

to SDA rising edge crossing 30% of V

From SDA rising edge to SCL falling edge;
both crossing 70% of V

CC

until SDA enters the 30% to 70% of V

CC

CC

CC

600 ns

,

0ns

window

CC

20 +

0.1 * Cb

TYP

(NOTE 1) MAX UNIT

1mA

1µs

CC

CC

VCC+0.3 V

10 pF

50 ns

900 ns

250 ns

V

V

4

FN8094.1

February 8, 2006

ISL90841

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Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN

t

(Note 15)

Cb

SDA and SCL fall time From 70% to 30% of V

F

CC

20 +

0.1 * Cb

Capacitive loading of SDA or SCL Total on-chip and off-chip 10 400 pF

(Note 15)

Rpu

(Note 15)

SDA and SCL bus pull-up resistor off­chip

Maximum is determined by t
For Cb = 400pF, max is about 2~2.5kΩ

and t

R

F

1kΩ

For Cb = 40pF, max is about 15~20kΩ

t

SU:A

t

HD:A

A1 and A0 setup time Before START condition 600 ns

A1 and A0 hold time After STOP condition 600 ns

TYP

(NOTE 1) MAX UNIT

SDA vs SCL Timing

250 ns

SCL

t

SU:STA

(INPUT TIMING)

(OUTPUT TIMING)

SDA

SDA

A0 and A1 Pin Timing

SCL

SDA IN

A0, A1

t

HD:STA

t

F

START

t

SU:DAT

t

SU:A

t

HIGH

CLK 1

t

LOW

t

HD:DAT

t

R

t

SU:STO

t

t

DH

AA

STOP

t

HD:A

t

BUF

5

FN8094.1

February 8, 2006

ISL90841

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NOTES:

1. Typical values are for T

2. LSB: [V(R

W)255

incremental voltage when changing from one tap to an adjacent tap.

3. ZS error = V(R

4. FS error = [V(R

5. DNL = [V(R

6. INL = V(R

7. V

MATCH

8. for i = 16 to 240 decimal, T = -40°C to 85°C. Max( ) is the maximum value of the wiper

TC

V

|R

9. MI =

10. Roffset = R
Roffset = R

11. RDNL = (R

12. RINL = [R

13. R

MATCH

14. for i = 32 to 255, T = -40°C to 85°C. Max( ) is the maximum value of the resistance and Min ( ) is the

TC

R

W)0

W)255

– V(RW)

W)i

– i - LSB – V(RW) for i = 1 to 255.

W)i

= [V(RWx)i – V(RWy)i]/LSB, for i = 0 to 255, x = 0 to 3 and y = 0 to 3.

Max V RW()

()Min V RW()

------------------------------------------------------------- ---------------------------------

()Min V RW()

Max V RW()

– R

255

0

/MI, when measuring between R

0

/MI, when measuring between R

255

– R

i

i-1

– (MI • i) – R0]/MI, for i = 32 to 255.

i

= (R

– R

i,x

Max Ri()Min Ri()–[]

------------------------------------------------------------ --- -

Max Ri()Min Ri()+[]2⁄

15. This parameter is not 100% tested.

= 25°C and 3.3V supply voltage.

A

– V(RW)0]/255. V(RW)

/LSB.

and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the

255

– VCC]/LSB.

]/LSB-1, for i = 1 to 255. i is the DCP register setting.

i-1

|/255. R

()–

i

()+[]2⁄

i

and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.

255

i

i

6

10

---------------- -

×=

125°C

and GND.

W

and RH.

W

)/MI, for i = 32 to 255.

)/MI, for i = 0 to 255, x = 0 to 3 and y = 0 to 3.

i,y

---------------- -

×=

125°C

6

10

minimum value of the resistance over the temperature range.

voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

Typical Performance Curves

160

140

VCC=2.7, T=-40°C

120

100

80

60

40

WIPER RESISTANCE (Ω)

20

VCC=5.5, T=-40°C

0

0 50 100 150 200 250

FIGURE 1. WIPER RESISTANCE vs TAP POSITION

[I(R

W

) = V

VCC=2.7, T=+85°C

VCC=5.5, T=+25°C

TAP POSITION (DECIMAL)

/ R

CC

TOTAL

VCC=2.7, T=+25°C

] FOR 50kΩ (U)

VCC=5.5, T=+85°C

1.8

1.6

1.4

1.2

(µA)

CC

1

0.8

0.6

STANDBY I

0.4

0.2

0

2.7 3.2 3.7 4.2 4.7 5.2

+25°C

FIGURE 2. STANDBY I

-40°C

V

CC

(V)

CC

vs V

+85°C

CC

6

FN8094.1

February 8, 2006

Typical Performance Curves (Continued)

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ISL90841

0.2

0.15

VCC=2.7, T=+25°C

0.1

0.05

0

DNL (LSB)

-0.05

-0.1

-0.15

VCC=2.7, T=+85°C

-0.2
0 50 100 150 200 250

VCC=5.5, T=-40°C

VCC=5.5, T=+25°C

TAP POSITION (DECIMAL)

VCC=2.7, T=-40°C

VCC=5.5, T=+85°C

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

0.4

0.35

0.3

0.25

ZSerror (LSB)

2.7V

0.3

VCC=5.5, T=-40°C

0.2

0.1

0

INL (LSB)

-0.1
V

=2.7, T=+85°C

CC

-0.2

0.3
0 50 100 150 200 250

=2.7, T=-40°C

V

CC

V

=2.7, T=+25°C

CC

TAP POSITION (DECIMAL)

VCC=5.5, T=+85°C

VCC=5.5, T=+25°C

FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

0

-0.2

VCC=5.5V

-0.4

-0.6

FSerror (LSB)

VCC=2.7V

0.2

0.15

-40 -20 20 40 60 80

0

TEMPERATURE (°C)

5.5V

-0.8

-1

-40 -20 20 40 60 80

0

TEMPERATURE (°C)

FIGURE 5. ZSerror vs TEMPERATURE FOR 50kΩ (U) FIGURE 6. FSerror vs TEMPERATURE FOR 50kΩ (U)

0.3

0.2
V

=5.5, T=+25°C

CC

0.1

0

DNL (LSB)

-0.1
V

=5.5, T=+85°C

CC

-0.2

-0.3

32 82 132 182 232

VCC=2.7, T=-40°C

VCC=5.5, T=-40°C

TAP POSITION (DECIMAL)

VCC=2.7, T=+25°C

VCC=2.7, T=+85°C

FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR

50kΩ (U)

0.5

VCC=2.7, T=+25°C

0.3

0.1

V

=2.7, T=+85°C

CC

-0.1

INL (LSB)

-0.3

=5.5, T=+25°C

V

-0.5

CC

32 82 132 182 232

TAP POSITION (DECIMAL)

VCC=5.5, T=-40°C

VCC=5.5, T=+85°C

VCC=2.7,

FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR

50kΩ (U)

T=-40°C

7

FN8094.1

February 8, 2006

Typical Performance Curves (Continued)

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ISL90841

1.5

1

2.7V

0.5

CHANGE (%)

5.5V

0

TOTAL

-0.5

-1

END TO END R

-1.5

-40 -20 20 40 60 80

FIGURE 9. END TO END R

TEMPERATURE FOR 10kΩ (W)

35

25

15

5

TC (ppm/°C)

-5

0

TEMPERATURE (°C)

% CHANGE vs

TOTAL

20

10

0

TC (ppm/°C)

-10

-20
32 82 132 182 232

TAP POSITION (DECIMAL)

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

INPUT

OUTPUT

-15

-25
32 82 132 182 232

TAP POSITION (DECIMAL)

TAP POSITION = MID POINT

=9.4K

R

TOTAL

FIGURE 11. TC FOR RHEOSTAT MODE IN ppm FIGURE 12. FREQUENCY RESPONSE (2.2MHz)

SIGNAL AT WIPER (WIPER UNLOADED)

WIPER MOVEMENT MID POINT
FROM 80h TO 7fh

SCL

SIGNAL AT WIPER
(WIPER UPLOADED
MOVEMENT FROM
ffh TO 00h

FIGURE 13. MIDSCALE GLITCH, CODE 80h to 7Fh (WIPER 0) FIGURE 14. LARGE SIGNAL SETTLING TIME

8

FN8094.1

February 8, 2006

Principles of Operation

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The ISL90841 is an integrated circuit incorporating four
DCPs with their associated registers, and an I
interface providing direct communication between a host
and the potentiometers.

DCP Description

Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (R
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). Each DCP has its own WR.
When the WR of a DCP contains all zeroes (WR<7:0>: 00h),
its wiper terminal (R
When the WR of a DCP contains all ones (WR<7:0>: FFh),
its wiper terminal (R
As the value of the WR increases from all zeroes (00h) to all
ones (255 decimal), the wiper moves monotonically from the
position closest to GND to the closest to R
time, the resistance between R
monotonically, while the resistance between R
decreases monotonically.

While the ISL90841 is being powered up, all four WRs are
reset to 80h (128 decimal), which locates R
center between GND and R

The WRs can be read or written directly using the I2C serial
interface as described in the following sections. The I
interface Address Byte has to be set to 00h, 01h, 02h, and
03h to access the WR of DCP0, DCP1, DCP2, and DCP3
respectively

and GND). The RW pin of each DCP is

H

) is closest to its “Low” terminal (GND).

W

) is closest to its “High” terminal (RH).

W

and GND increases

W

.

H

2

C serial

. At the same

H

and RW

H

roughly at the

W

2

C

ISL90841

2

All I

C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL90841 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 15). A START condition is ignored during the power­up of the device.

2

All I

C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 15). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.

An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).

The ISL90841 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL90841 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation

A valid Identification Byte contains 01010 as the five MSBs,
and the following two bits matching the logic values present
at pins A1 and A0. The LSB is the Read/Write
“1” for a Read operation, and “0” for a Write operation (See
Table 1).

TABLE 1. IDENTIFICATION BYTE FORMAT

Logic values at pins A1 and A0 respectively

bit. Its value is

I2C Serial Interface

The ISL90841 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL90841
operates as a slave device in all applications.

All communication over the I
sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 15). On power-up of the ISL90841 the SDA pin is in
the input mode.

2

C interface is conducted by

9

01010A1A0R/W

(MSB) (LSB)

FN8094.1

February 8, 2006

SCL

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SDA

ISL90841

SCL FROM

MASTER

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

SIGNALS FROM

START DATA DATA STOP

STABLE CHANGE

DATA

STABLE

FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS

81 9

HIGH IMPEDANCE

START ACK

FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER

WRITE

S

THE MASTER

T
A

IDENTIFICATION

R
T

BYTE

ADDRESS

BYTE

DATA

BYTE

HIGH IMPEDANCE

S
T
O
P

SIGNALS

FROM THE

MASTER

SIGNAL AT SDA

SIGNALS FROM

THE SLAVE

SIGNAL AT SDA

SIGNALS FROM

THE ISL90841

S

T

A

IDENTIFICATION

R

BYTE WITH

T

R/W

00011

0

10

00011

00000

000 0

A0A1

A
C
K

A
C
K

A
C
K

FIGURE 17. BYTE WRITE SEQUENCE

S
T
A

IDENTIFICATION

ADDRESS

=0

A0A1

A
C
K

BYTE

0000 00

R
T

A
C
K

BYTE WITH

R/W

=1

01011

0

A0A1

A
C

FIRST READ

K

DATA BYTE

A
C
K

A
C
K

LAST READ

DATA BYTE

S
T
O
P

FIGURE 18. READ SEQUENCE

FN8094.1

February 8, 2006

Write Operation

www.BDTIC.com/Intersil

A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90841 responds with an ACK. At this time, the device
enters its standby state (See Figure 17).

Read Operation

A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W
Address Byte, a second START, and a second Identification
byte with the R/W
the ISL90841 responds with an ACK. Then the ISL90841
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
STOP condition) following the last bit of the last Data Byte
(See Figure 18).

The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 03h the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.

bit set to “1”. After each of the three bytes,

bit set to “0”, an

ISL90841

11

FN8094.1

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Packaging Information

www.BDTIC.com/Intersil

ISL90841

14-Lead Plastic, TSSOP, Package Code V14

.025 (.65) BSC

0° - 8°

.0075 (.19)
.0118 (.30)

.193 (4.9)
.200 (5.1)

.019 (.50)
.029 (.75)

Detail A (20X)

.169 (4.3)
.177 (4.5)

.041 (1.05)

.002 (.05)
.006 (.15)

.010 (.25)

Gage Plane

Seating Plane

.252 (6.4) BSC

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

12

FN8094.1

February 8, 2006