intersil ISL90810 DATA SHEET

®

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ISL90810

Single Digitally Controlled Potentiometer (XDCP™)

Data Sheet November 10, 2006

Low Noise/Low Power/I2C Bus/256 Taps

The ISL90810 integrates a digitally controlled potentiometer
(XDCP) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the

2

I

C bus interface. Each potentiometer has an associated
Wiper Register (WR) that can be directly written to and read
by the user. The contents of the WR controls the position of
the wiper. When powered on the ISL90810’s wiper will
always commence at mid-scale (128 tap position).

The DCP can be used as three-terminal potentiometer or as
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.

FN8234.2

Features

• 256 resistor taps - 0.4% resoluti o n

2

•I

C serial interface with write/read capability

• Power-on preset to mid-scale (128 tap position)

• Wiper resistance: 70Ω typical @ 3.3V

• Standby current 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ, 10kΩ total resistance

• 8 Ld MSOP

• Pb-free plus anneal available (RoHS compliant)

Pinout

ISL90810

(8 LD MSOP)

TOP VIEW

NC

SCL

SDA

GND

1
2
3
4

8

V

CC

7

RH

6

RL
RW

5

Ordering Information

PART NUMBER PART MARKING R

ISL90810WIU8 AJL 10 -40 to +85 8 Ld MSOP M8.118
ISL90810WIU8Z* (Note) DEN 10 -40 to +85 8 Ld MSOP (Pb-free) M8.118
ISL90810WAU8Z* (Note) 810WA 10 -40 to +105 8 Ld MSOP (Pb-free) M8.118
ISL90810UIU8 AJK 50 -40 to +85 8 Ld MSOP M8.118
ISL90810UIU8Z* (Note) DEM 50 -40 to +85 8 Ld MSOP (Pb-free) M8.118
ISL90810UAU8Z* (Note) 810UA 50 -40 to +105 8 Ld MSOP (Pb-free) M8.118
*Add "-TK" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

(kΩ) TEMP RANGE (°C) PACKAGE PKG. DWG#

TOTAL

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

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ISL90810

VCC

RH

SDA

SCL

Pin Descriptions

MSOP

PIN SYMBOL DESCRIPTION

1 NC No connection

2

2SCLI
3 SDA Serial data I/O for the I2C interface
4 GND Ground
5 RW “Wiper” terminal of the DCP
6 RL “Low” terminal of the DCP
7 RH “High” terminal of the DCP
8V

CC

C interface clock

Power supply

I2C AND

CONTROL

WIPER

REGISTER

GND

Equivalent Circuitry

R

H

10pF

RL

RW

R

TOTAL

C

H

C

W

25pF

R

W

C

L

10pF

R

L

2

FN8234.2

November 10, 2006

ISL90810

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at Any Digital Interface Pin

With Respect to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V

CC

Voltage at Any DCP Pin With

Respect to V

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A @ +105°C

ESD

HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV

MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied .

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

JA

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

R

W

C

H/CL/CW

I

LkgDCP

VOLTAGE DIVIDER MODE (0V @ RL; V

(Note 7) Integral Non-Linearity -1 1 LSB (Note 3)

INL

DNL

(Note 6) Differential Non-Linearity Monotonic over all tap positions W option -0.75 +0.75 LSB (Note 3)

ZSerror (Note 4) Zero-Scale Error W option 0 1 7 LSB

FSerror

(Note 5) Full-Scale Error W option -7 -1 0 LSB (Note 3)

TC

(Notes 8, 14) Ratiometric Temperature Coefficient DCP Register set to 80 hex ±4 ppm/°C

V

RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)

RINL

(Note 12) Integral Non-Linearity DCP register set between 20 hex and FF hex.

(Note 6) Differential Non-Linearity DCP register set between 20 hex

RDNL

(Note 10) Offset W option 0 1 7 MI (Note 9)

Roffset

TC

R

(Notes 13, 14)

. . . . . . . . . . . . . . . . . . . .-0.3V to VCC+0.3V

SS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

SS

RH to RL Resistance W, U versions respectively 10, 50 kΩ
R

to RL Resistance Tolerance -20 +20 %

H

Wiper resistance VCC = 3.3V @ +25°C

Potentiometer Capacitance
(Note 14, Equivalent circuitry)

Leakage on DCP pins (Note 14) Voltage at pin from GND to V

Resistance Temperature Coefficient DCP register set between 20 hex and FF hex ±35 ppm/°C

@ RH; measured at RW, unloaded)

CC

Wiper current = V

U option 0 0.5 2

U option -2 -0.5 0

Monotonic over all tap positions

and FF hex. Monotonic over all tap
positions

U option 0 0.5 2 MI

CC

Thermal Resistance (Typical, Note 1) θ
8 Ld MSOP Package 130

Maximum Junction Temperature (Plastic Package . . . . . . . . +150°C

Recommended Operating Conditions

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Automotive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

V

CC

Power Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

TYP

(Notes 2) MAX UNIT

70 200 Ω

CC/RTOTAL

10/10/25 pF

CC

U option -0.5 +0.5 LSB

-1 1 MI (Note 9)

W option -0.75 +0.75 MI (Note 9)
U option -0.5 +0.5 MI

0.1 1 µA

(°C/W)

JA

(Note 3)
(Note 3)

(Note 9)

(Note 9)

3

FN8234.2

November 10, 2006

ISL90810

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

SB

VCC Supply Current
(Volatile Write/Read)

VCC Current (Standby) V

f

= 400kHz; SDA = Open; (for I2C, Active,

SCL

Read and Volatile Write States only)

= +5.5V, I2C Interface in Standby State,

CC

Temperature range from -40°C to +85°C

= +5.5V, I2C Interface in Standby State,

V

CC

Temperature range from -40°C to +105°C
V

= +3.6V, I2C Interface in Standby State,

CC

Temperature range from -40°C to +85°C
V

= +3.6V, I2C Interface in Standby State,

CC

Temperature range from -40°C to +105°C

I

LkgDig

t

(Note 14) DCP Wiper Response Time SCL falling edge of last bit of DCP Data Byte to

DCP

Leakage Current at Pins SDA and
SCL

Voltage at pin from GND to V

CC

wiper change

Vpor Power-On Recall Voltage Minimum V

Ramp VCC Ramp Rate 0.2 V/ms

V

CC

(Note 14) Power-Up Delay VCC above Vpor, to DCP Initial V a lue Register

t

D

recall completed, and I

at which memory recall occurs 1.8 2.6 V

CC

2

C Interface in standby state

SERIAL INTERFACE SPECIFICATIONS

V

IL

V

IH

Hysteresis

SDA, and SCL Input Buffer LOW
Voltage

SDA, and SCL Input Buffer HIGH
Voltage

SDA and SCL Input Buffer Hysteresis 0.05*

0.7*V

(Note 14)

V

(Note 14) SDA Output Buffer LOW Voltage,

OL

(Note 14) SDA, and SCL Pin Capacitance 10 pF

Cpin

f

SCL

(Note 14) Pulse Width Suppression Time at

t

IN

t

(Note 14) SCL Falling Edge to SDA Output Data

AA

t

(Note 14) Time the Bus Must be Free Before the

BUF

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

Sinking 4mA

SCL Frequency 400 kHz

Any pulse narrower than the max spec is

SDA and SCL Inputs

suppressed.
SCL falling edge crossing 30% of VCC, until SDA

Valid

exits the 30% to 70% of V

window.

CC

SDA crossing 70% of VCC during a STOP

Start of a New Transmission

condition, to SDA crossing 70% of V
the following START condition.

CC

during

Clock LOW Time Measured at the 30% of VCC crossing. 1300 ns
Clock HIGH Time Measured at the 70% of VCC crossing. 600 ns
START Condition Setup Time SCL rising edge to SDA falling edge. Both

crossing 70% of V

CC

.

START Condition Hold Time From SDA falling edge crossing 30% of VCC to

SCL falling edge crossing 70% of V

CC

.

Input Data Setup Time From SDA exiting the 30% to 70% of VCC

window, to SCL rising edge crossing 30% of V

CC

Input Data Hold Time From SCL rising edge crossing 70% of VCC to

SDA entering the 30% to 70% of V

window.

CC

STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to

SDA rising edge crossing 30% of V

CC

.

(Note 1) MAX UNITS

20 100 µA

25µA

28µA

0.8 2 µA

0.8 5 µA

-10 10 µA

-0.3 0.3*V

CC

V

CC

VCC+0.3 V

00.4V

1300 ns

600 ns

600 ns

100 ns

0ns

600 ns

1µs

3ms

V

CC

V

50 ns

900 ns

4

FN8234.2

November 10, 2006

ISL90810

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

t

HD:STO

(Note 14) Output Data Hold Time From SCL falling edge crossing 30% of VCC, until

t

DH

t

(Note 14) SDA and SCL Rise Time From 30% to 70% of V

R

STOP Condition Hold Time for Read,
or Volatile Only Write

From SDA rising edge to SCL falling edge. Both
crossing 70% of V

SDA enters the 30% to 70% of V

CC

.

window.

CC

CC

0.1 * Cb

t

(Note 14) SDA and SCL Fall Time From 70% to 30% of V

F

(Note 14) Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF

Cb

(Note 14) SDA and SCL Bus Pull-Up Resistor

Rpu

Off-Chip

Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2~2.5kΩ.

CC

0.1 * Cb

For Cb = 40pF, max is about 15~20kΩ

SDA vs SCL Timing

t

F

t

HIGH

t

LOW

t

R

(Note 1) MAX UNITS

600 ns

0ns

20 +

20 +

1kΩ

250 ns

250 ns

SCL

(INPUT TIMING)

(OUTPUT TIMING)

SDA

SDA

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

t

t

AA

DH

t

BUF

NOTES:

2. Typical values are for T

3. LSB: [V(RW)
incremental voltage when changing from one tap to an adjacent tap.

255

4. ZS error = V(RW)

5. FS error = [V(RW)

6. DNL = [V(RW)

7. INL = (V(RW)

8. for i = 16 to 240 decimal, T = -40°C to +105°C. Max( ) is the maximum value of the wiper

TC

V

9. MI =

|R

Roffset = R

10. Roffset = R

11. RDNL = (R

12. RINL = [R

13. for i = 32 to 255, T = -40°C to +105°C. Max( ) is the maximum value of the resistance and Min ( ) is the

TC

R

– V(RW)

i

– i • LSB – V(RW)0)/LSB, for i = 1 to 255.

i

Max V RW()

()Min V RW()

--------------------------------------------------------------------------------------------- -

Max V RW()

()Min V RW()

– R

255

|/255. R

0

/MI, when measuring between RW and RL.

0

/MI, when measuring between RW and RH.

255

– R

i

i-1

– (MI • i) – R0]/MI, for i = 32 to 255.

i

Max Ri()Min Ri()–[]

--------------------------------------------------------------- -

Max Ri()Min Ri()+[]2⁄

= +25°C and 3.3V supply voltage.

A

– V(RW)0]/255. V(RW)

/LSB.

0

– VCC]/LSB.

255

]/LSB-1, for i = 1 to 255. i is the DCP register setting.

i-1

i

()+[]2⁄

i

and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.

255

255

()–

i

)/MI, for i = 32 to 255.

6

10

---------------- -

×=

145°C

and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the

6

10

i

---------------- -

×=

145°C

voltage and Min ( ) is the m inimu m va lue of th e wip er vo lt age ov er t he te mper atur e ra nge.

minimum value of the resistance over the temperature range.

14. This parameter is not 100% tested.

5

FN8234.2

November 10, 2006

Typical Performance Curves

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ISL90810

160

140

Vcc = 2.7, T = -40°C

120

100

80

60

40

WIPER RESISTANCE (Ω)

20

Vcc = 5.5, T = -40°C

0

0 50 100 150 200 250

TAP POSITION (DECIMAL)

Vcc = 2.7, T = +85°C

Vcc = 2.7, T = +25°C

Vcc = 5.5, T = +85°C

Vcc = 5.5, T = +25°C

FIGURE 1. WIPER RESISTANCE vs TAP POSITION

[I(RW) = V

0.2

0.15

0.1

0.05

-0.05

DNL (LSB)

-0.1

-0.15

-0.2

Vcc = 2.7, T = +25°C

0

Vcc = 2.7, T = +85°C

0 50 100 150 200 250

/Rtotal] FOR 50kΩ (U)

CC

Vcc = 5.5, T = -40°C

Vcc = 5.5, T = +25°C

Vcc = 5.5, T = +85°C

TAP POSITION (DECIMAL)

Vcc = 2.7, T = -40°C

FIGURE 3. DNL vs TAP POSITION IN VOL TAGE DIVIDER

MODE FOR 10kΩ (W)

1.8

1.6

1.4

1.2

(µA)

1.0

CC

0.8

0.6

STANDBY I

0.4

0.2

0.0

2.7 3.2 3.7 4.2 4.7 5.2

FIGURE 2. STANDBY I

0.3

Vcc = 5.5, T = -40°C

0.2

0.1

0

INL (LSB)

Vcc = 2.7, T = +85°C

-0.1

-0.2

-0.3
0 50 100 150 200 250

-40°C

+25°C

V

(V)

CC

CC

Vcc = 2.7, T = -40°C

Vcc = 2.7, T = +25°C

TAP POSITION (DECIMAL)

+85°C

vs V

CC

Vcc = 5.5, T = +85°C

Vcc = 5.5, T = +25°C

FIGURE 4. INL vs TAP POSITION IN VOLT AGE DIVIDER

MODE FOR 10kΩ (W)

0.4

0.35

0.3

0.25

ZSerror (LSB)

0.2

0.15

-40-200 20406080

2.7V

5.5V

TEMPERATURE (°C)

FSerror (LSB)

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

0

-1

-40

FIGURE 5. ZSerror vs TEMPERATURE FIGURE 6. FSerror vs TEMPERATURE

6

-20

Vcc = 5.5V

Vcc = 2.7V

0

20 40 60 80

TEMPERATURE (°C)

FN8234.2

November 10, 2006

Typical Performance Curves (Continued)

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ISL90810

0.3

0.2

0.1

0

DNL (LSB)

-0.1

-0.2

-0.3
32 82 132 182 232

Vcc = 5.5, T = +25°C

Vcc = 5.5, T = +85°C

Vcc = 2.7, T = -40°C

TAP POSITION (DECIMAL)

Vcc = 2.7, T = +25°C

Vcc = 2.7, T = +85°C

Vcc = 5.5, T = -40°C

FIGURE 7. DNL vs T AP POSITION IN RHEOSTAT MODE FOR

50kΩ (U)

1.50

1.00

0.50

CHANGE (%)

5.5V

0.00

TOTAL

-0.50

-1.00

END TO END R

-1.50

-40-200 20406080

FIGURE 9. END TO END R

2.7V

TEMPERATURE (°C)

TEMPERATURE

% CHANGE vs

TOTAL

0.5

0.4

0.3

0.2

0.1

0

-0.1

INL (LSB)

-0.2

-0.3

-0.4

Vcc = 2.7, T = +85°C

-0.5
32 82 132 182 232

Vcc = 5.5, T = +25°C

TAP POSITION (DECIMAL)

Vcc = 5.5, T = +85°C

Vcc = 2.7, T = +25°C

Vcc = 5.5, T = -40°C

Vcc = 2.7, T = -40°C

FIGURE 8. INL vs TAP POSITION IN RHEOSTA T MODE FOR

50kΩ (U)

20

10

0

TC (ppm/°C)

-10

-20

32 82 132 182 232

TAP POSITION (DECIMAL)

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

35

25

15

5

TC (ppm/°C)

-5

-15

-25
32 57 82 107 132 157 182 207 232

TAP POSITION (DECIMAL)

FIGURE 11. TC FOR RHEOSTAT MODE IN ppm

Tap Position = Mid Point
R

TOTAL

FIGURE 12. FREQUENCY RESPONSE (2.2MHz)

7

OUTPUT

= 9.4K

INPUT

FN8234.2

November 10, 2006

Typical Performance Curves (Continued)

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ISL90810

Signal at Wiper (Wiper Unloaded)

Wiper Movement Mid Point
From 80h to 7fh

FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)

Principles of Operation

The ISL90810 is an integrated circuit incorporating one DCP
with its associated registers, and an I
providing direct communication between a host and the
potentiometer.

DCP Description

The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). When the WR of the DCP
contains all zeroes (WR[7:0]: 00h), its wiper terminal (RW) is
closest to its “Low” terminal (RL). When the WR of the DCP
contains all ones (WR[7:0]: FFh), its wiper terminal (RW) is
closest to its “High” terminal (RH). As the value of the WR
increases from all zeroes (0 decimal) to all ones (255
decimal), the wiper moves monotonically from the position
closest to RL to the closest to RH. At the same time, the
resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.

While the ISL90810 is being powered up, The WR is reset to
80h (128 decimal), which locates RW roughly at the center
between RL and RH.

The WR can be read or written to directly using the I
interface as described in the following sections. The I
interface Address Byte has to be set to 00hex to access the
WR.

2

C serial interface

2

C serial

2

C

SCL

Signal at Wiper
(Wiper Unloaded Movement
From ffh to 00h)

FIGURE 14. LARGE SIGNAL SETTLING TIME

I2C Serial Interface

The ISL90810 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL90810
operates as a slave device in all applications.

All communication over the I
sending the MSB of each byte of data first.

2

C interface is conducted by

Protocol Conventions

Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 15). On power-up of the ISL90810 the SDA pin is in
the input mode.

2

All I

C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL90810 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 15). A START condition is ignored during the power­up for the device.

2

All I

C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 15) A STOP condition at the end of
a read operation, or at the end of a write operation places
the device in its standby mode.

An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).

8

FN8234.2

November 10, 2006

ISL90810

www.BDTIC.com/Intersil

The ISL90810 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL90810 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.

A valid Identification Byte contains 0101000 as the seven
MSBs. The LSB is the Read/Write

bit. Its value is “1” for a

Read operation, and “0” for a Write operation (See Table 1)
The address byte is set to 00h and follows the identification

byte. Read and write operations always point to address
00h, indicating the WR for the device.

TABLE 1. IDENTIFICATION BYTE FORMAT

0 101000R/W

(MSB) (LSB)

Write Operation

A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90810 responds with an ACK. At this time the device
enters its standby state (See Figure 17).

Data Protection

A valid Identification Byte. Address Byte, and total number of
SCL pulses act as a protection for the registers. During a
Write sequence, the Data Byte is loaded into an internal shift
register as it is received. The Data Byte is transferred to the
Wiper Register (WR) at the falling edge of the SCL pulse
that loads the last bit (LSB) of the Data Byte.

Read Operation

A Read operation consists of a three byte instruction
followed by one Data Byte (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the identification byte with the R/W bit set to "0", an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to "1". After each of the three bytes,
the ISL90810 responds with an ACK. The the ISL90810
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
ACK

and a STOP condition) following the last bit of the Data

Byte (See Figure 18).

SCL

SDA

SCL FROM

MASTER

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

START DATA DATA STOP

FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS

HIGH IMPEDANCE

START ACK

FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER

STABLE CHANGE

DATA

STABLE

81 9

HIGH IMPEDANCE

9

FN8234.2

November 10, 2006

SIGNALS FROM

www.BDTIC.com/Intersil

THE MASTER

S
T
A

IDENTIFICATION

R
T

BYTE

ISL90810

WRITE

ADDRESS

BYTE

DATA
BYTE

S
T
O
P

SIGNAL AT SDA

SIGNALS FROM

SIGNALS

FROM THE

MASTER

SIGNAL AT SDA

SIGNALS FROM

THE SLAVE

THE ISL90810

S
T

A

IDENTIFICATION

R

BYTE WITH

T

00011

00011

FIGURE 17. BYTE WRITE SEQUENCE

ADDRESS

=0

R/W

000 0000 00

A
C
K

FIGURE 18. READ SEQUENCE

BYTE

000000000000

A
C
K

S
T
A

IDENTIFICATION
R
T

0

0

A
C
K

01011

0

A
C
K

BYTE WITH

R/W

=1

000

A
C
K

A
C
K

DATA BYTE

S

A

T

C

O

K

P

10

FN8234.2

November 10, 2006

ISL90810

www.BDTIC.com/Intersil

Mini Small Outline Plastic Packages (MSOP)

N

EE1

INDEX

AREA

AA1A2

-H-

SIDE VIEW

12

TOP VIEW

b

e

D

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

.

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only.

-B-

0.20 (0.008) A

GAUGE

PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING
PLANE

a

0.20 (0.008) C

- H -

B

4X θ

C

D

4X θ

L1

C

L

E

1

END VIEW

R1

R

L

C

-B-

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.010 0.014 0.25 0.36 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.026 BSC 0.65 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N8 87

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

05

α

o

o

0

15

o

o

6

o

5

o

0

15

o

o

6

Rev. 2 01/03

NOTESMIN MAX MIN MAX

-

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

11

FN8234.2

November 10, 2006