intersil ISL90810 DATA SHEET

®

www.BDTIC.com/Intersil

ISL90810

Single Digitally Controlled Potentiometer (XDCP™)

Data Sheet November 10, 2006

Low Noise/Low Power/I2C Bus/256 Taps

The ISL90810 integrates a digitally controlled potentiometer
(XDCP) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the

2

I

C bus interface. Each potentiometer has an associated
Wiper Register (WR) that can be directly written to and read
by the user. The contents of the WR controls the position of
the wiper. When powered on the ISL90810’s wiper will
always commence at mid-scale (128 tap position).

The DCP can be used as three-terminal potentiometer or as
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.

FN8234.2

Features

• 256 resistor taps - 0.4% resoluti o n

2

•I

C serial interface with write/read capability

• Power-on preset to mid-scale (128 tap position)

• Wiper resistance: 70Ω typical @ 3.3V

• Standby current 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ, 10kΩ total resistance

• 8 Ld MSOP

• Pb-free plus anneal available (RoHS compliant)

Pinout

ISL90810

(8 LD MSOP)

TOP VIEW

NC

SCL

SDA

GND

1
2
3
4

8

V

CC

7

RH

6

RL
RW

5

Ordering Information

PART NUMBER PART MARKING R

ISL90810WIU8 AJL 10 -40 to +85 8 Ld MSOP M8.118
ISL90810WIU8Z* (Note) DEN 10 -40 to +85 8 Ld MSOP (Pb-free) M8.118
ISL90810WAU8Z* (Note) 810WA 10 -40 to +105 8 Ld MSOP (Pb-free) M8.118
ISL90810UIU8 AJK 50 -40 to +85 8 Ld MSOP M8.118
ISL90810UIU8Z* (Note) DEM 50 -40 to +85 8 Ld MSOP (Pb-free) M8.118
ISL90810UAU8Z* (Note) 810UA 50 -40 to +105 8 Ld MSOP (Pb-free) M8.118
*Add "-TK" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

(kΩ) TEMP RANGE (°C) PACKAGE PKG. DWG#

TOTAL

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

www.BDTIC.com/Intersil

ISL90810

VCC

RH

SDA

SCL

Pin Descriptions

MSOP

PIN SYMBOL DESCRIPTION

1 NC No connection

2

2SCLI
3 SDA Serial data I/O for the I2C interface
4 GND Ground
5 RW “Wiper” terminal of the DCP
6 RL “Low” terminal of the DCP
7 RH “High” terminal of the DCP
8V

CC

C interface clock

Power supply

I2C AND

CONTROL

WIPER

REGISTER

GND

Equivalent Circuitry

R

H

10pF

RL

RW

R

TOTAL

C

H

C

W

25pF

R

W

C

L

10pF

R

L

2

FN8234.2

November 10, 2006

ISL90810

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at Any Digital Interface Pin

With Respect to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V

CC

Voltage at Any DCP Pin With

Respect to V

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A @ +105°C

ESD

HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV

MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied .

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

JA

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

R

W

C

H/CL/CW

I

LkgDCP

VOLTAGE DIVIDER MODE (0V @ RL; V

(Note 7) Integral Non-Linearity -1 1 LSB (Note 3)

INL

DNL

(Note 6) Differential Non-Linearity Monotonic over all tap positions W option -0.75 +0.75 LSB (Note 3)

ZSerror (Note 4) Zero-Scale Error W option 0 1 7 LSB

FSerror

(Note 5) Full-Scale Error W option -7 -1 0 LSB (Note 3)

TC

(Notes 8, 14) Ratiometric Temperature Coefficient DCP Register set to 80 hex ±4 ppm/°C

V

RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)

RINL

(Note 12) Integral Non-Linearity DCP register set between 20 hex and FF hex.

(Note 6) Differential Non-Linearity DCP register set between 20 hex

RDNL

(Note 10) Offset W option 0 1 7 MI (Note 9)

Roffset

TC

R

(Notes 13, 14)

. . . . . . . . . . . . . . . . . . . .-0.3V to VCC+0.3V

SS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

SS

RH to RL Resistance W, U versions respectively 10, 50 kΩ
R

to RL Resistance Tolerance -20 +20 %

H

Wiper resistance VCC = 3.3V @ +25°C

Potentiometer Capacitance
(Note 14, Equivalent circuitry)

Leakage on DCP pins (Note 14) Voltage at pin from GND to V

Resistance Temperature Coefficient DCP register set between 20 hex and FF hex ±35 ppm/°C

@ RH; measured at RW, unloaded)

CC

Wiper current = V

U option 0 0.5 2

U option -2 -0.5 0

Monotonic over all tap positions

and FF hex. Monotonic over all tap
positions

U option 0 0.5 2 MI

CC

Thermal Resistance (Typical, Note 1) θ
8 Ld MSOP Package 130

Maximum Junction Temperature (Plastic Package . . . . . . . . +150°C

Recommended Operating Conditions

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Automotive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

V

CC

Power Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

TYP

(Notes 2) MAX UNIT

70 200 Ω

CC/RTOTAL

10/10/25 pF

CC

U option -0.5 +0.5 LSB

-1 1 MI (Note 9)

W option -0.75 +0.75 MI (Note 9)
U option -0.5 +0.5 MI

0.1 1 µA

(°C/W)

JA

(Note 3)
(Note 3)

(Note 9)

(Note 9)

3

FN8234.2

November 10, 2006

ISL90810

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

SB

VCC Supply Current
(Volatile Write/Read)

VCC Current (Standby) V

f

= 400kHz; SDA = Open; (for I2C, Active,

SCL

Read and Volatile Write States only)

= +5.5V, I2C Interface in Standby State,

CC

Temperature range from -40°C to +85°C

= +5.5V, I2C Interface in Standby State,

V

CC

Temperature range from -40°C to +105°C
V

= +3.6V, I2C Interface in Standby State,

CC

Temperature range from -40°C to +85°C
V

= +3.6V, I2C Interface in Standby State,

CC

Temperature range from -40°C to +105°C

I

LkgDig

t

(Note 14) DCP Wiper Response Time SCL falling edge of last bit of DCP Data Byte to

DCP

Leakage Current at Pins SDA and
SCL

Voltage at pin from GND to V

CC

wiper change

Vpor Power-On Recall Voltage Minimum V

Ramp VCC Ramp Rate 0.2 V/ms

V

CC

(Note 14) Power-Up Delay VCC above Vpor, to DCP Initial V a lue Register

t

D

recall completed, and I

at which memory recall occurs 1.8 2.6 V

CC

2

C Interface in standby state

SERIAL INTERFACE SPECIFICATIONS

V

IL

V

IH

Hysteresis

SDA, and SCL Input Buffer LOW
Voltage

SDA, and SCL Input Buffer HIGH
Voltage

SDA and SCL Input Buffer Hysteresis 0.05*

0.7*V

(Note 14)

V

(Note 14) SDA Output Buffer LOW Voltage,

OL

(Note 14) SDA, and SCL Pin Capacitance 10 pF

Cpin

f

SCL

(Note 14) Pulse Width Suppression Time at

t

IN

t

(Note 14) SCL Falling Edge to SDA Output Data

AA

t

(Note 14) Time the Bus Must be Free Before the

BUF

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

Sinking 4mA

SCL Frequency 400 kHz

Any pulse narrower than the max spec is

SDA and SCL Inputs

suppressed.
SCL falling edge crossing 30% of VCC, until SDA

Valid

exits the 30% to 70% of V

window.

CC

SDA crossing 70% of VCC during a STOP

Start of a New Transmission

condition, to SDA crossing 70% of V
the following START condition.

CC

during

Clock LOW Time Measured at the 30% of VCC crossing. 1300 ns
Clock HIGH Time Measured at the 70% of VCC crossing. 600 ns
START Condition Setup Time SCL rising edge to SDA falling edge. Both

crossing 70% of V

CC

.

START Condition Hold Time From SDA falling edge crossing 30% of VCC to

SCL falling edge crossing 70% of V

CC

.

Input Data Setup Time From SDA exiting the 30% to 70% of VCC

window, to SCL rising edge crossing 30% of V

CC

Input Data Hold Time From SCL rising edge crossing 70% of VCC to

SDA entering the 30% to 70% of V

window.

CC

STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to

SDA rising edge crossing 30% of V

CC

.

(Note 1) MAX UNITS

20 100 µA

25µA

28µA

0.8 2 µA

0.8 5 µA

-10 10 µA

-0.3 0.3*V

CC

V

CC

VCC+0.3 V

00.4V

1300 ns

600 ns

600 ns

100 ns

0ns

600 ns

1µs

3ms

V

CC

V

50 ns

900 ns

4

FN8234.2

November 10, 2006