intersil ISL9007 DATA SHEET

®

www.BDTIC.com/Intersil

ISL9007

Datasheet March 27, 2008

High Current LDO with Low IQ and High
PSRR

ISL9007 is a high performance LDO that delivers a
continuous 400mA of load current. It has a low standby
current and high PSRR and is stable with output capacitance
of 1µF to 10µF with an ESR of up to 200mΩ.

The ISL9007 has a very high PSRR of 75dB and output
noise less than 30µV

. When coupled with a no load

RMS

quiescent current of 50µA (typical), and 1µA (max) shutdown
current, the ISL9007 is an ideal choice for portable wireless
equipment.

The ISL9007 comes in fixed voltage options of 3.3V, 2.85V,

2.8V, and 2.5V with ±1.8% output voltage accuracy
over-temperature, line and load. Other output voltage
options may be available upon request.

Pinout

ISL9007

(8 Ld MSOP)

TOP VIEW

VO

NC

1

2

8

VIN

7

VIN

FN9218.1

Features

• High performance LDO with 400mA continuous output

• Excellent transient response to large current steps

• Excellent load regulation: <0.1% voltage change across
full range of load current

• Very high PSRR: 75dB @ 1kHz

• Wide input voltage capability: 2.3V to 6.5V

• Very low quiescent current: 50µA

• Low dropout voltage: typically 200mV @ 400mA

• Low output noise: typically 30µV

• Stable with 1µF to 10µF ceramic capacitors

• Shutdown pin turns off LDO for 1µA (max) standby current

• Soft-start to limit input current surge during enable

• Current limit and overheat protection

• ±1.8% accuracy over all operating conditions

• 8 Ld MSOP package

• -40°C to +85°C operating temperature range

• Pb-free (RoHS compliant)

@ 100µA (2.5V)

RMS

NC

NC

3

45

SD

6

GND

Applications

• PDAs, Cell Phones and Smart Phones

• Portable Instruments, MP3 Players

• Handheld Devices, including Medical Handhelds

Ordering Information

PART NUMBER

(Notes 1, 2) PART MARKING

ISL9007IUNZ* 007NZ 3.3 -40 to +85 8 Ld MSOP M8.118
ISL9007IUKZ* 007KZ 2.85 -40 to +85 8 Ld MSOP M8.118
ISL9007IUJZ* 007JZ 2.8 -40 to +85 8 Ld MSOP M8.118
ISL9007IUFZ* 007FZ 2.5 -40 to +85 8 Ld MSOP M8.118

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.

2. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

3. For other output voltages, contact Intersil Marketing.

VO VOLTAGE (V)

(Note 3) TEMP RANGE (°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2005, 2008. All Rights Reserved.

ISL9007

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V

VO Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V

Recommended Operating Conditions

Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . .2.3V to 6.5V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

4. θ

JA

Tech Brief TB379.

5. For θ

Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature

DC CHARACTERISTICS

Supply Voltage V
Ground Current I
Shutdown Current I
UVLO Threshold V

Regulation Voltage Accuracy Initial accuracy at V

Maximum Output Current I
Internal Current Limit I
Drop-out Voltage (Note 7) V

Thermal Shutdown Temperature T

AC CHARACTERISTICS

Ripple Rejection (Note 6) I

Output Noise Voltage (Note 6) I

DEVICE START-UP CHARACTERISTICS

Device Enable Time t

LDO Soft-start Ramp Rate t

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

range of the device as follows:

= -40°C to +85°C; VIN = (VO+ 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF.

T

A

PARAMETER SYMBOL TEST CONDITIONS

IN

Quiescent condition: IO = 0µA 50 70 µA

DD

DDS

V

MAX

V

T

SSR

@ +25°C 0.1 1.0 µA

UV+

UV-

= VO+ 0.5V, IO = 10mA, TJ = +25°C -0.7 +0.7 %

IN

V

= VO+ 0.5V to 5.5V, IO = 10µA to 400mA, TJ = +25°C -0.8 +0.8 %

IN

= VO+ 0.5V to 5.5V , IO = 10µA to 400mA, TJ = -40°C to

V

IN

+125°C
Continuous 400 mA

LIM
DO1IO
DO2IO
SD+

SD-

EN

= 400mA; 2.5V ≤ VO ≤ 2.8V 250 400 mV
= 400mA; 2.8V < V

= 10mA, VIN = 2.8V (min), VO = 1.8V

O

@ 1kHz 75 dB
@ 10kHz 60 dB
@ 100kHz 40 dB

= 100µA, VO = 1.5V, TA = +25°C

O

BW = 10Hz to 100kHz

Time from assertion of the ENx pin to when the output
voltage reaches 95% of the VO (nom)

Slope of linear portion of LDO output voltage ramp during
start-up

O

Thermal Resistance (Typical, Notes 4, 5) θ

8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 157

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

MIN

(Note 8) TYP

2.3 6.5 V

1.9 2.1 2.3 V

1.6 1.8 2.0 V

-1.8 +1.8 %

470 540 750 mA

200 325 mV
145 °C
110 °C

250 500 µs

MAX

(Note 8) UNITS

40 µV

30 60 µs/V

(°C/W)

JA

RMS

2

FN9218.1

March 27, 2008

ISL9007

www.BDTIC.com/Intersil

Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature

range of the device as follows:

= -40°C to +85°C; VIN = (VO+ 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF.

T

A

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 8) TYP

MAX

(Note 8) UNITS

SD PIN CHARACTERISTICS

Input Low Voltage V
Input High Voltage V
Input Leakage Current I

IL

Pin Capacitance C

IL
IH

, I

IH

Informative 5 pF

PIN

-0.3 0.4 V

1.4 V

+ 0.3 V

IN

0.1 µA

NOTES:

6. Limits established by characterization and are not production tested.

7. VO-x = 0.98*VO-x(NOM).

8. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.

Typical Performance Curves

0.8
VO = 3.3V

I

(%)

O

-0.2

-0.4

OUTPUT VOLTAGE, V

-0.6

-0.8

0.6

0.4

0.2

-40°C

0.0

+25°C

+85°C

3.8 4.2 6.25.8
INPUT VOLTAGE (V)

FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE

(3.3V OUTPUT)

= 0mA

L

6.63.4 4.6 5.0 5.4

0.10

O

(mA)

VIN = 3.8V
V

+25°C

OUTPUT VOLTAGE CHANGE (%)

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

-0.06

-0.08

-0.10

+85°C

100 200 300 4000

50 150 250 350

LOAD CURRENT - I

FIGURE 2. OUTPUT VOLTAGE vs LOAD CURRENT

= 3.3V

O

-40°C

0.10

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

OUTPUT VOLTAGE (%)

-0.06

-0.08

-0.10

-10 20 50 110-40

-25 5 35 8065 95 125
TEMPERATURE (°C)

VIN = 3.8V
V
I

L

FIGURE 3. OUTPUT VOLTAGE vs TEMPERATURE

= 3.3V

O

= 0mA

3.4

IO = 0mA

3.3

(V)

O

3.2

3.1
IO = 300mA

3.0

OUTPUT VOLTAGE, V

2.9

2.8

3.1 3.6 4.1 4.6 5.1 6.15.6

FIGURE 4. OUTPUT VOLTAGE vs INPUT VOL T AGE

3

IO = 150mA

INPUT VOLTAGE (V)

(3.3V OUTPUT)

VO = 3.3V

March 27, 2008

6.5

FN9218.1

Typical Performance Curves

www.BDTIC.com/Intersil

ISL9007

2.9

IO = 0mA

2.8

2.7
IO = 150mA

2.6

IO = 300mA

2.5

OUTPUT VOLTAGE, VO (V)

2.4

2.3

2.63.13.64.14.65.1 6.1
INPUT VOLTAGE (V)

VO = 2.8V

5.6

FIGURE 5. OUTPUT VOL T AGE vs INPUT VO L TAGE

(2.8V OUTPUT)

350

VO = 3.3V

300

(mV)

DO

250

200

150

100

DROP OUT VOLTAGE, V

50

0

50 100 150 200 250 300 350 4000

OUTPUT LOAD (mA)

+85°C

FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT

+25°C

-40°C

6.5

350

300

(mV)

250

DO

200

VO = 2.8V

150

100

DROP OUT VOLTAGE, V

50

0

50 100 150 200 250 300 350 4000

OUTPUT LOAD (mA)

FIGURE 6. DROPOUT VOLTAGE vs LOAD CURRENT

80

70

60

50

40

GROUND CURRENT (µA)

30

20

3.0 3.5 4.58 5.5 6.0

4.0 5.0 6.5
INPUT VOLTAGE (V)

125°C

+25°C

V

= 3.3V

O

IO = 0µA

FIGURE 8. GROUND CURRENT vs INPUT VOLTAGE

VO = 3.3V

-40°C

200
180
160
140
120
100

GROUND CURRENT (µA)

+85°C

80
60
40
20

0

50 100 150 200 250 4000

LOAD CURRENT (mA)

FIGURE 9. GROUND CURRENT vs LOAD

-40°C

= 3.8V

V

IN

VO = 3.3V

350300

25°C

80

70

60

50

40

GROUND CURRENT (µA)

30

20

-25 5 35 8065 95 125

FIGURE 10. GROUND CURRENT vs TEMPERATURE

4

VIN = 3.8V
V

= 3.3V

O

I

= 0µA

L

-10 20 50 110-40
TEMPERATURE (°C)

FN9218.1

March 27, 2008

Typical Performance Curves

www.BDTIC.com/Intersil

ISL9007

VIN = 5.0V
VO = 3.3V

3

2

(V)V

1

O

V

0

5

(V)

EN

0

100 200 300 400 500 600 700 8000

TIME (µs)

IL = 300mA

C

= 1µF

L

900 1K

4.3V

3.6V

10mV/DIV

400 µs/DIV

VO = 3.3V
I

= 300mA

L

C

= 1µF

L

FIGURE 11. TURN ON/TURN OFF RESPONSE FIGURE 12. LINE TRANSIENT RESPONSE, 3.3V OUTPUT

VO = 2.8V

= 300mA

I

4.2V

3.5V

L

C

= 1µF

L

VO (25mV/DIV)

= 1.8V

V

O

VIN = 2.8V

10mV/DIV

400µs/DIV

FIGURE 13. LINE TRANSIENT RESPONSE, 2.8V OUTPUT

100

90
80
70
60
50

PSRR (dB)

40
30
20
10

0

0.1 1 10 100 1k
FREQUENCY (Hz)

VIN = 3.5V

= 2.5V

V

O

I

= 10mA

O

= 1µF

C

L

FIGURE 15. PSRR vs FREQUENCY

300mA

I

100µA

LOAD

100µs/DIV

FIGURE 14. LOAD TRANSIENT RESPONSE

10

1

0.1
VIN = 3.6V

V

= 1.8V

O

I

= 10mA

LOAD

C

= 1µF

0.01

SPECTRAL NOISE DENSITY (µV/√Hz)

0.001

IN

= 1µF

C

L

10 100 1k 10k 100k 1M

FREQUENCY (Hz)

FIGURE 16. SPECTRAL NOISE DENSITY vs FREQUENCY

5

FN9218.1

March 27, 2008

ISL9007

www.BDTIC.com/Intersil

Pin Descriptions

PIN

NUMBER PIN NAME DESCRIPTION

1 VO LDO Output:

Connect capacitor of value 1µF to 10µF to
GND (1µF recommended)

2, 3, 4 NC No Connection

5 GND GND is the connection to system ground.

Connect to PCB Ground plane.

6 SD LDO Shutdown. When this signal goes

high, the LDO is turned off.

7 VIN Supply Voltage/LDO Input:

8 VIN Supply Voltage/LDO Input:

Connect a 1µF capacitor to GND.

Connect a 1µF capacitor to GND.

Typical Application

VIN (3.0V TO 6.5V)

SHUTDOWN

ON

ISL9007

8

VIN

7

OFF

C1

C1, C2: 1µF X5R CERAMIC CAPACITOR

VIN

6

SD

VO

GND

1

5

C2

VOUT

Block Diagram

VIN

VIN

SD

UVLO

CONTROL

LOGIC

BANDGAP AND
TEMPERATURE

SHORT CIRCUIT,

THERMAL PROTECTION,

SOFT-START

+

-

SENSOR

VO

GND

Functional Description

The ISL9007 contains all circuitry required to implement a
high performance LDO. High performance is achieved
through a circuit that delivers fast transient response to
varying load conditions. In a quiescent cond iti o n, the
ISL9007 adjusts its biasing to achieve the lowest standby
current consumption.

The device also integrates current limit protection, smart
thermal shutdown protection, and soft-start. Smart thermal
shutdown protects the device against overheating. Soft-start
minimize start-up input current surges without causing
excessive device turn-on time.

Power Control

The ISL9007 has a shutdown pin (SD) to control power to
the LDO output. When SD is high, the device is in shutdown
mode. In this condition, all on-chip circuits are off, and the
device draws minimum current, typically less than 0.1µA.
When the SD pin goes low, the device first polls the output of
the UVLO detector to ensure that VIN voltage is at least 2.1V
(typical). Once verified, the device initiates a start-up
sequence. During the start-up sequence, trim settings are
first read and latched. Then, sequentially, the bandgap,
reference voltage and current generation circuitry turn-on.
Once the references are stable, the LDO powers up.

During operation, whenever the VIN voltage drops below
about 1.84V, the ISL9007 immediately disables both LDO
outputs. When VIN rises back above 2.1V (assuming the SD
pin is low), the device re-initiates its start-up sequence and
LDO operation will resume automatically.

6

FN9218.1

March 27, 2008

ISL9007

www.BDTIC.com/Intersil

Reference Generation

The reference generation circuitry includes a trimmed
bandgap, a trimmed voltage reference divider, a trimmed
current reference generator, and an RC noise filter.

The bandgap generates a zero temperature coefficient (TC)
voltage for the regulator reference and other voltage
references required for current generation and
over-temperature detection.

A current generator provides references required for
adaptive biasing as well as references for LDO output
current limit and thermal shutdown determination.

LDO Regulation and Programmable Output Divider

The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9000 provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1µF to 10µF output
capacitor that has a tolerance better than 20% and ESR less
than 200mΩ. The design is performance-optimized for a 1µF
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7µF is not recommended as LDO
performance improvement is minimal.

Overheat Detection

The bandgap outputs a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about +145°C, the LDO
momentarily shuts down until the die cools sufficiently. In the
overheat condition, if the LDO sources more than 50mA it
will be shut off. Once the die temperature falls back below
about +110°C, the disabled LDO is re-enabled and soft-start
automatically takes place.

Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge. The
ISL9007 provides short-circuit protection by limiting the
output current to about 500mA.

The LDO uses an independently trimmed 1V reference as its
input. An internal resistor divider drops the LDO output
voltage down to 1V . This is compared to the 1V reference for
regulation. The resistor division ratio is programmed in the
factory to one of the following output voltages: 3.3, 2.85V,

2.8V, and 2.5V.

7

FN9218.1

March 27, 2008

ISL9007

www.BDTIC.com/Intersil

Mini Small Outline Plastic Packages (MSOP)

N

EE1

INDEX

AREA

AA1A2

-H-

SIDE VIEW

12

TOP VIEW

b

e

D

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

.

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only.

-B-

0.20 (0.008) A

GAUGE

PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING
PLANE

a

0.20 (0.008) C

- H -

B

4X θ

C

D

4X θ

L1

C

L

E

1

END VIEW

R1

R

L

C

-B-

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 ­A1 0.002 0.006 0.05 0.15 ­A2 0.030 0.037 0.75 0.95 -

b 0.010 0.014 0.25 0.36 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.026 BSC 0.65 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6
L1 0.037 REF 0.95 REF -

N8 87
R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

0 5

α

o

o

0

15

o

o

6

o

5

o

0

15

o

o

6

Rev. 2 01/03

NOTESMIN MAX MIN MAX

-

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

8

FN9218.1

March 27, 2008