intersil ISL9003A DATA SHEET

®

www.BDTIC.com/Intersil

ISL9003A

Data Sheet March 11, 2008

Low Noise LDO with Low IQ and High
PSRR

ISL9003A is a high performance single low noise, high
PSRR LDO that delivers a continuous 150mA of load
current. It has a low standby current and is stable with 1µF of
MLCC output capacitance with an ESR of up to 200mΩ.

The ISL9003A has a very high PSRR of 90dB and output
noise is 20µV

(typical). When coupled with a no load

RMS

quiescent current of 31µA (typical), and 0.5µA shutdown
current, the ISL9003A is an ideal choice for portable wireless
equipment.

The ISL9003A comes in many fixed voltage options with
±1.8% output voltage accuracy over temperature, line and
load. Other output voltage options are available on request.

Pinouts

ISL9003A

(5 LD SC-70)

TOP VIEW

VIN

GND

EN

1

2

354

VO

CBYP

FN6299.3

Features

• High performance LDO with 150mA continuous output

• Excellent transient response to large current steps

• Excellent load regulation:
<0.1% voltage change across full range of load current

• Very high PSRR: >90dB @ 1kHz

• Wide input voltage capability: 2.3V to 6.5V

• Extremely low quiescent current: 31µA

• Low dropout voltage: typically 200mV @ 150mA

• Low output noise: typically 20µV

• Stable with 1µF to 4.7µF ceramic capacitors

• Shutdown pin turns off LDO with 1µA (max) standby
current

• Soft-start limits input current surge during enable

• Current limit and overheat protection

• ±1.8% accuracy over all operating conditions

• 5 Ld SC-70 package or 6 Ld µTDFN package

• -40°C to +85°C operating temperature range

• Pb-free (RoHS compliant)

@ 100µA (1.5V)

RMS

ISL9003A

(6 LD 1.6x1.6 µTDFN)

TOP VIEW

VO

GND

CBYP

1
2
3

6
5

4

VIN
NC5
EN

Applications

• PDAs, cell phones and smart phones

• Portable instruments, MP3 players

• Handheld devices including medical handhelds

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2006, 2008. All Rights Reserved.

ISL9003A

www.BDTIC.com/Intersil

Ordering Information

V

VOLTAGE

PART NUMBER

(Note 1) PART MARKING

ISL9003AIENZ-T (Note 3) CBK 3.30 -40 to +85 5 Ld SC-70 P5.049
ISL9003AIEMZ-T (Note 3) CBJ 3.00 -40 to +85 5 Ld SC-70 P5.049
ISL9003AIEKZ-T (Note 3) CCE 2.85 -40 to +85 5 Ld SC-70 P5.049
ISL9003AIEJZ-T (Note 3) CCD 2.80 -40 to +85 5 Ld SC-70 P5.049
ISL9003AIEHZ-T (Note 3) CCC 2.75 -40 to +85 5 Ld SC-70 P5.049
ISL9003AIEFZ-T (Note 3) CCB 2.50 -40 to +85 5 Ld SC-70 P5.049
ISL9003AIECZ-T (Note 3) CBY 1.80 -40 to +85 5 Ld SC-70 P5.049
ISL9003AIEBZ-T (Note 3) CBW 1.50 -40 to +85 5 Ld SC-70 P5.049
ISL9003AIRUBZ-T (Note 3) L 1.50 -40 to +85 6 Ld µTDFN L6.1.6x1.6A
ISL9003AIRUCZ-T (Note 4) G 1.80 -40 to +85 6 Ld µTDFN L6.1.6x1.6A
ISL9003AIRUFZ-T (Note 4) F 2.50 -40 to +85 6 Ld µTDFN L6.1.6x1.6A
ISL9003AIRURZ-T (Note 4) M2 2.60 -40 to +85 6 Ld µTDFN L6.1.6x1.6A
ISL9003AIRUHZ-T (Note 4) H 2.75 -40 to +85 6 Ld µTDFN L6.1.6x1.6A
ISL9003AIRUJZ-T (Note 4) J 2.80 -40 to +85 6 Ld µTDFN L6.1.6x1.6A
ISL9003AIRUKZ-T (Note 4) K 2.85 -40 to +85 6 Ld µTDFN L6.1.6x1.6A
ISL9003AIRUMZ-T (Note 4) M 3.00 -40 to +85 6 Ld µTDFN L6.1.6x1.6A
ISL9003AIRUNZ-T (Note 4) N 3.30 -40 to +85 6 Ld µTDFN L6.1.6x1.6A

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. For other output voltages, contact Intersil Marketing.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.

4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020..

O

(V)

(Note 2)

TEMP. RANGE

(°C)

PACKAGE

Tape and Reel

(Pb-Free)

PKG.

DWG. NUMBER

2

FN6299.3

March 11, 2008

ISL9003A

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V

V

Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V

O

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + 0.3V)

Recommended Operating Conditions

Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . .2.3V to 6.5V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTE:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

5. θ

JA

6. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

Thermal Resistance θ

5 Ld SC-70 Package (Note 5) . . . . . . . . . . . . . . . . . 231

6 Ld µTDFN Package (Note 6) . . . . . . . . . . . . . . . . 125

Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C

Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Electrical Specifications Unless otherwise noted, all parameters are guaran teed over the operational sup ply voltage and temperat ure range of

the device as follows: T
C

= 1µF; C

O

PARAMETER SYMBOL TEST CONDITIONS

DC CHARACTERISTICS

Supply Voltage V
Ground Current I

Shutdown Current I
UVLO Threshold V

Regulation Voltage Accuracy Initial accuracy at V

Maximum Output Current I
Internal Current Limit I
Drop-out Voltage (Note 8) V

Thermal Shutdown Temperature T

AC CHARACTERISTICS

Ripple Rejection (Note 7) I

Output Noise Voltage (Note 7) V

IN

DD

DDS

UV+

V

UV-

MAX

LIM
DO1IO

V

DO2IO

V

DO3IO
SD+

T

SD-

BYP

Output Enabled; IO = 0µA; V
Output Enabled; I

V

= VO + 0.5V to 6.5V, IO = 10µA to150mA, TJ = +25°C -0.8 +0.8 %

IN

= VO + 0.5V to 6.5V, IO = 10µA to 150mA, TJ = -40°C to

V

IN

+125°C
Continuous 150 mA

= 150mA; VO < 2.5V 300 500 mV
= 150mA; 2.5V ≤ VO ≤ 2.8V 250 400 mV
= 150mA; 2.8V < V

= 10mA, VIN = 2.8V(min), VO = 1.8V, C

O

@ 1kHz 90 dB
@ 10kHz 70 dB
@ 100kHz 50 dB

= 1.5V, TA = +25°C, C

O

BW = 10Hz to 100kHz, I
BW = 10Hz to 100kHz, IO = 10mA 30 µV

= -40°C to +85°C; V

A

= 0.01µF

= 0µA; Full voltage range 57 µA

O

= VO + 0.5V, IO = 10mA, TJ = +25°C -0.7 +0.7 %

IN

O

BYP

O

= (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN=1µF;

IN

MIN

(Note 9) TYP

2.3 6.5 V

< 4.2V 31 40 µA

IN

1.9 2.1 2.3 V

1.6 1.8 2.0 V

-1.8 +1.8 %

175 265 355 mA

= 0.1µF

BYP

= 0.1µF

= 100µA 20 µV

(Note 9) UNITS

0.5 1.2 µA

200 325 mV
140 °C
110 °C

MAX

(°C/W)

JA

RMS
RMS

3

FN6299.3

March 11, 2008

ISL9003A

www.BDTIC.com/Intersil

Electrical Specifications Unless otherwise noted, all parameters are guaran teed over the operational sup ply voltage and temperat ure range of

the device as follows: T

= 1µF; C

C

O

BYP

PARAMETER SYMBOL TEST CONDITIONS

DEVICE START-UP CHARACTERISTICS

Device Enable tIme t

Time from assertion of the EN pin to when the output voltage

EN

reaches 95% of the V

LDO Soft-start Ramp Rate t

Slope of linear portion of LDO output voltage ramp during start-up 30 60 µs/V

SSR

EN PIN CHARACTERISTICS

Input Low Voltage V
Input High Voltage V
Input Leakage Current I
Pin Capacitance C

IL

IH

, I

IL

IH

Informative 5 pF

PIN

NOTES:

7. Limits established by characterization and are not production tested.
= 0.98 * VO(NOM); Valid for VO greater than 1.85V.

8. V

O

9. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested

= -40°C to +85°C; V

A

= 0.01µF (Continued)

(nom).

O

= (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN=1µF;

IN

MIN

(Note 9) TYP

MAX

(Note 9) UNITS

250 500 µs

-0.3 0.4 V

1.4 V

IN

0.1 µA

+ 0.3 V

Typical Performance Curves

0.8
VO = 3.3V

= 0mA

+85°C

-40°C

I

LOAD

(%)

O

-0.2

-0.4

OUTPUT VOLTAGE, V

-0.6

-0.8

0.6

0.4

0.2

+25°C

0.0

3.8 4.2 6.25.8
INPUT VOLTAGE (V)

FIGURE 1. OUTPUT VOLT AGE vs INPUT VOL T AGE

(3.3V OUTPUT)

6.63.4 4.6 5.0 5.4

0.2

0.1

0.0

-0.1

-0.2

-0.3

OUTPUT VOLTAGE CHANGE (%)

-0.4

3.3 3.8 4.3 4.8 5.3 5.8 6.3

IO = 0mA

IO = 75mA

I

= 150mA

O

INPUT VOLTAGE (V)

VO = 3.3V
+25°C

FIGURE 2. OUTPUT VOLT AGECHANGE (%) vs INPUT

VOLTAGE (3.3V OUTPUT)

4

FN6299.3

March 11, 2008

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

ISL9003A

1.0

-40°C

VIN = 3.8V
V

= 3.3V

O

+25°C

+85°C

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

OUTPUT VOLTAGE CHANGE (%)

-0.8

-1.0
0 25 50 75 100 125 150 175

LOAD CURRENT - IO (mA)

FIGURE 3. OUTPUT VOLTAGE vs LOAD CURRENT

3.4

3.3

3.2

3.1

(V)

O

3.0

2.9

2.8

2.7

2.6

OUTPUT VOLTAGE, V

2.5

2.4

2.3

2.6 3.1 3.6 4.1 4.6 5.1 5.6 6.1 6.6

IO = 0mA

IO = 75mA

IO = 150mA

INPUT VOLTAGE (V)

VO = 3.3V
+25°C

FIGURE 5. DROPOUT VOL TAGE vs INPUT VOLTAGE

(3.3V OUTPUT)

0.10

= 150mA

I

O

VIN = 3.8V
V

= 3.3V

O

55

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

OUTPUT VOLTAGE (%)

-0.06

-0.08

-0.10

IO = 0mA

IO = 75mA

-25 0 25 85-40
TEMPERATURE (°C)

FIGURE 4. OUTPUT VOLTAGE vs TEMPERATURE

2.9

2.8

(V)

O

2.7

2.6

2.5

OUTPUT VOLTAGE, V

2.4

2.3

IO = 0mA

IO = 75mA

IO = 150mA

VO = 2.8V
+25°C

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
INPUT VOLTAGE (V)

FIGURE 6. DROPOUT VOLT AG E vs INPUT VOL TAGE

(2.8V OUTPUT)

250

200

(mV)

DO

150

VO = 2.8V

100

50

DROP OUT VOLTAGE, V

0

0 25 50 75 100 125 150 175

OUTPUT LOAD (mA)

VO = 3.3V

FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT

225

VO = 3.3V

200

175

(mV)

DO

150

125

100

75

50

DROP OUT VOLTAGE, V

25

0

FIGURE 8. DROPOUT VOLTAGE vs LOAD CURRENT

5

+85°C

25 50 75 100 125 150 1750

OUTPUT LOAD (mA)

+25°C

-40°C

March 11, 2008

FN6299.3

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

ISL9003A

60

50

40

30

20

GROUND CURRENT (µA)

10

0

1.5 2.0 3.0 4.0 4.5

+85°C

-40°C

2.5 3.5 5.0
INPUT VOLTAGE (V)

V

IO = 0µA

FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE

100

90

80

70

60

50

GROUND CURRENT (µA)

40

30

20

-30 -10 10 4030 50 70

IL = 150mA

IL = 75mA

IL = 0mA

-20 0 20 60-40
TEMPERATURE (°C)

+25°C

= 3.3V

O

6.05.5 6.5

VIN = 3.8V
V

= 3.3V

O

80 90

140

120

100

80

+85°C

60

40

GROUND CURRENT (µA)

20

-40°C

0

25 50 75 100 1250

LOAD CURRENT (mA)

FIGURE 10. GROUND CURRENT vs LOAD

3

2

(V)V

1

O

V

0

5

(V)

EN

0

100 200 300 400 500 600 700 8000

TIME (µs)

FIGURE 11. GROUND CURRENT vs TEMPERATURE FIGURE 12. TURN ON/TURN OFF RESPONSE

V

= 3.8V

IN

VO = 3.3V

VIN = 5.0V
VO = 3.3V
IL = 150mA
C

= 1µF

L

900 1000

+25°C

175150

VO = 3.3V
I

= 150mA

LOAD

C

= 1µF

LOAD

C

= 0.01µF

BYP

4.3V

3.6V

10mV/DIV

400µs/DIV

4.2V

3.5V

10mV/DIV

FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT

6

400µs/DIV

VO = 2.8V

= 150mA

I

LOAD

= 1µF

C

LOAD

C

= 0.01µF

BYP

FN6299.3

March 11, 2008

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

= 3.3V

V

O

VIN = 3.8V

I

100mA

100µA

FIGURE 15. LOAD TRANSIENT RESPONSE FIGURE 16. PSRR vs FREQUENCY

LOAD

VO (10mV/DIV)

1.0 ms/DIV

2.000

1.000

ISL9003A

110

100

90

10mA

80
70
60

PSRR (dB)

50
40
30
20
10

50mA

VIN = 3.9V
V

= 1.8V

O

= 0.1µF

C

BYP

= 1µF

C

LOAD

0.1k 1k 10k 100k 1M
FREQUENCY (Hz)

0.100

VIN = 3.9V

= 1.8V

V

O

C

= 0.1µF

BYP

C

= 1µF

IN

= 1µF

C

LOAD

10 100 1k 10k 100k 1M

FREQUENCY (Hz)

SPECTRAL NOISE DENSITY (μV/√Hz)

0.010

0.001

100μA

10mA

FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY

7

FN6299.3

March 11, 2008

Pin Description

www.BDTIC.com/Intersil

ISL9003A

5 LD SC-70

PIN

NUMBER

16V

6 LD µTDFN

PIN

NUMTBER PIN NAME DESCRIPTION

Supply Voltage/LDO Input. Connect a 1µF capacitor to GND.

IN

2 2 GND GND is the connection to system ground. Connect to PCB Ground plane.
3 4 EN Output Enable. When this signal goes high, the LDO is turned on.
4 3 CBYP Reference Bypass Capacitor Pin. Optionally connect capacitor of value 0.01µF to 1µF between this pin

and GND to tune in the desired noise and PSRR performance.

51V

LDO Output. Connect a 1µF capacitor of value to GND.

O

- 5 NC No Connect.

Typical Application

V

(2.3V TO 5V)

IN

ENABLE

OFF

ON

ISL9003A (SC-70)

1

V

IN

2

GND

3

EN

C1 C2

VO

CBYP

5

4

C3

V

OUT

C1, C2: 1µF X5R CERAMIC CAPACITOR

C3: 0.1µF X5R CERAMIC CAPACITOR

ISL9003A (µTDFN)

C3

1

V

O

2

GND

3

CBYP

V

OUT

C2

V
NC

EN

6

IN

5

4

C1

V

(2.3V TO 5V)

IN

ENABLE

ON

OFF

C1, C2: 1µF X5R CERAMIC CAPACITOR

C3: 0.1µF X5R CERAMIC CAPACITOR

8

FN6299.3

March 11, 2008

Block Diagram

www.BDTIC.com/Intersil

ISL9003A

V

IN

SHORT CIRCUIT,

THERMAL PROTECTION,

GND

SD

UVLO

CONTROL

LOGIC

BANDGAP AND
TEMPERATURE

SENSOR

Functional Description

The ISL9003A contains all circuitry required to implement a
high performance LDO. High performance is achieved
through a circuit that delivers fast transient response to
varying load conditions. In a quiescent condition, the
ISL9003A adjusts its biasing to achieve the lowest standby
current consumption.

The device also integrates current limit protection, smart
thermal shutdown protection, and soft-start. Smart Thermal
shutdown protects the device against overheating. Soft-start
minimizes start-up input current surges without causing
excessive device turn-on time.

Power Control

The ISL9003A has an enable pin, (EN), to control power to
the LDO output. When EN is low, the device is in shutdown
mode. In this condition, all on-chip circuits are off, and the
device draws minimum current, typically less than 0.3
When the EN pin goes high, the device first polls the output
of the UVLO detector to ensure that VIN voltage is at least

2.1V (typical). Once verified, the device initiates a start-up
sequence. During the start-up sequence, trim settings are
first read and latched. Then, sequentially, the bandgap,
reference voltage and current generation circuitry turn-on.
Once the references are stable, the LDO powers-up.

During operation, whenever the VIN voltage drops below
about 1.84V, the ISL9003A immediately disables the LDO
output. When VIN rises back above 2.1V (assuming the EN
pin is high), the device re-initiates its start-up sequence and
LDO operation resumes automatically.

µA.

SOFT-START

+

-

VOLTAGE AND

REFERENCE

GENERATOR

V

O

1.0V

0.94V

0.9V
GND

CBYP

Reference Generation

The reference generation circuitry includes a trimmed
bandgap, a trimmed voltage reference divider, a trimmed
current reference generator, and an RC noise filter . The filter
includes the external capacitor connected to the CBYP pin.
A 0.01

µF capacitor connected CBYP implements a 100Hz

lowpass filter, and is recommended for most high
performance applications. For the lowest noise application, a

0.1

µF or greater CBYP capacitor should be used. This filters

the reference noise to below the 10Hz to 1kHz frequency
band, which is crucial in many noise-sensitive applications.

The bandgap generates a zero temperature coefficient (TC)
voltage for the regulator reference and other voltage
references required for current generation and over­temperature detection.

A current generator provides references required for
adaptive biasing as well as references for LDO output
current limit and thermal shutdown determination.

LDO Regulation and Programmable Output Divider

The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9003A provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1µF to 4.7µF output
capacitor that has a toleranc e better than 2 0% and ESR less
than 200m
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7µF is not recommended as LDO
performance improvement is minimal. Soft-start circuitry
integrated into each LDO limits the initial ramp-up rate to

Ω. The design is performance-optimized for a 1µF

9

FN6299.3

March 11, 2008

ISL9003A

www.BDTIC.com/Intersil

about 30µs/V to minimize current surge. The ISL9003A
provides short-circuit protection by limiting the output current
to about 265mA (typ).

The LDO uses an independently trimmed 1V reference as its
input. An internal resistor divider drops the LDO output
voltage down to 1V . This is compared to the 1V reference for
regulation. The resistor division ratio is programmed in the
factory.

Overheat Detection

The bandgap outputs a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about +140°C, the LDO
momentarily shuts down until the die cools sufficiently. In the
overheat condition, if the LDO sources more than 50mA it
will be shut off. Once the die temperature falls back below
about +110°C, the disabled LDO is re-enabled and soft-start
automatically takes place.

10

FN6299.3

March 11, 2008

ISL9003A

www.BDTIC.com/Intersil

Small Outline Transistor Plastic Packages (SC70-5)

E

A2

A

SEATING

PLANE

D

e1

123

e

C

L

0.20 (0.008) M

PLATING

4X θ1

C

4X θ1

C

WITH

L

C

c

BASE METAL

45

C

b

A1

0.10 (0.004) C

b

b1

R1

L

α

L1

L

R

VIEW C

C

L

SEATING

PLANE

-C-

c1

GAUGE PLANE

L2

E1

P5.049

5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.031 0.043 0.80 1.10 -

A1 0.000 0.004 0.00 0.10 -

A2 0.031 0.039 0.80 1.00 -

b 0.006 0.012 0.15 0.30 -

b1 0.006 0.010 0.15 0.25

c 0.003 0.009 0.08 0.22 6

c1 0.003 0.009 0.08 0.20 6

C

D 0.073 0.085 1.85 2.15 3

E 0.071 0.094 1.80 2.40 -

E1 0.045 0.053 1.15 1.35 3

e 0.0256 Ref 0.65 Ref -

e1 0.0512 Ref 1.30 Ref -

L 0.010 0.018 0.26 0.46 4

L1 0.017 Ref. 0.420 Ref. -

L2 0.006 BSC 0.15 BSC

o

α

0

o

8

o

0

N5 55

R 0.004 - 0.10 -

R1 0.004 0.010 0.15 0.25

NOTES:

1. Dimensioning and tolerances per ASME Y14.5M-1994.

2. Package conforms to EIAJ SC70 and JEDEC MO-203AA.

3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.

4. Footlength L measured at reference to gauge plane.

5. “N” is the number of terminal positions.

6. These Dimensions apply to the flat section of the lead between

0.08mm and 0.15mm from the lead tip.

7. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only.

o

8

NOTESMIN MAX MIN MAX

-

Rev. 3 7/07

VIEW C

0.4mm

0.75mm

2.1mm

0.65mm

TYPICAL RECOMMENDED LAND PATTERN

11

FN6299.3

March 11, 2008

ISL9003A

www.BDTIC.com/Intersil

Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)

PIN 1

REFERENCE

2X

0.15 C

2X

6X

E

64

13

0.15 C
TOP VIEW

46

D2

31

BOTTOM VIEW

0.10 C

0.08 C

SIDE VIEW

1.00 REF

CO.2

E2

A

B

D

e

L

DAP SIZE 1.30 x 0.76

b6X

0.10 CAB

DETAIL A

C

A3

SEATING
PLANE

A

L6.1.6x1.6A

6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

NOTESMIN NOMINAL MAX

A 0.45 0.50 0.55 ­A1 - - 0.05 ­A3 0.127 REF -

A1

b 0.15 0.20 0.25 -

D 1.55 1.60 1.65 4

D2 0.40 0.45 0.50 -

E 1.55 1.60 1.65 4

E2 0.95 1.00 1.05 -

e 0.50 BSC ­L 0.25 0.30 0.35 -

M

Rev. 1 6/06

NOTES:

1. Dimensions are in mm. Angles in degrees.

2. Coplanarity applies to the exposed pad as well as the terminals.
Coplanarity shall not exceed 0.08mm.

3. Warpage shall not exceed 0.10mm.

4. Package length/package width are considered as special
characteristics.

5. JEDEC Reference MO-229.

6. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.

0.127±0.008

0.127 +0.058

-0.008

TERMINAL THICKNESS

A1

DETAIL A

0.25

0.50

1.00

1.00

1.25

0.45

0.30

LAND PATTERN

2.00

6

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

12

FN6299.3

March 11, 2008