intersil ISL9001A DATA SHEET

®

www.BDTIC.com/Intersil

ISL9001A

Data Sheet March 27, 2008

LDO with Low I

SUPPLY

ISL9001A is a high performance Low Dropout linear
regulator capable of sourcing 300mA current. It has a low
standby current and high-PSRR and is stable with output
capacitance of 1µF to 10µF with ESR of up to 200mΩ.

The ISL9001A has a very high PSRR of 90dB and output
noise less than 30µV

RMS

connection of a noise-filtering capacitor for low-noise and
high-PSRR applications. When coupled with a no load
quiescent current of 25µA (typical), and 0.1µA shutdown
current, the ISL9001A is an ideal choice for portable wireless
equipment.

The ISL9001A provides a P
programmable through an external capacitor.

Several different fixed voltage outputs are standard. Output
voltage options for each LDO range from 1.5V to 3.3V . Other
output voltage options may be available upon request.

, High PSRR

. A reference bypass pin allows

signal with delay time

GOOD

Pinout

ISL9001A

(8 LD DFN)

TOP VIEW

VIN

EN

CBYP

CPOR

1
2
3
4

8

VO

7

POR
NC

6

GND

5

FN6433.2

Features

• 300mA high performance LDO

• Excellent transient response to large current steps

• Excellent load regulation: <0.1% voltage change across
full range of load current

• High PSRR: 90dB @ 1kHz

• Wide input voltage capability: 2.3V to 6.5V

• Extremely low quiescent current: 25µA

• Low dropout voltage: typically 200mV @ 300mA

• Low output noise: typically 30µV

@ 100µA (1.5V)

RMS

• Stable with 1µF to 10µF ceramic capacitors

• Soft-start to limit input current surge during enable

• Current limit and overheat protection

• Delayed POR, programmable with external capacitor

• ±1.8% accuracy over all operating conditions

• Tiny 2mmx3mm 8 Ld DFN package

• -40°C to +85°C operating temperature range

• Pb-free (RoHS compliant)

Applications

• PDAs, cell phones and smart phones

• Portable instruments, MP3 players

• Handheld devices, including medical handhelds

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2007, 2008. All Rights Reserved

ISL9001A

www.BDTIC.com/Intersil

Ordering Information

PACKAGE

PART NUMBER

(Notes 1, 2) PART MARKING

ISL9001AIRBZ-T EBB 1.5 -40 to +85 8 Ld 2x3 DFN L8.2x3
ISL9001AIRCZ-T EBC 1.8 -40 to +85 8 Ld 2x3 DFN L8.2x3
ISL9001AIRFZ-T EBD 2.5 -40 to +85 8 Ld 2x3 DFN L8.2x3
ISL9001AIRRZ-T EBK 2.6 -40 to +85 8 Ld 2x3 DFN L8.2x3
ISL9001AIRJZ-T EBE 2.8 -40 to +85 8 Ld 2x3 DFN L8.2x3
ISL9001AIRKZ-T EBF 2.85 -40 to +85 8 Ld 2x3 DFN L8.2x3
ISL9001AIRLZ-T EBG 2.9 -40 to +85 8 Ld 2x3 DFN L8.2x3
ISL9001AIRMZ-T EBH 3.0 -40 to +85 8 Ld 2x3 DFN L8.2x3
ISL9001AIRNZ-T EBJ 3.3 -40 to +85 8 Ld 2x3 DFN L8.2x3

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.

2. Please refer to TB347 for details on reel specifications

3. For other output voltages, contact Intersil Marketing.

VO VOLTAGE (V)

(Note 3)

TEMP

RANGE (°C)

Tape and Reel

(Pb-free)

PKG.

DWG. #

2

FN6433.2

March 27, 2008

ISL9001A

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V

VO Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V

Recommended Operating Conditions

Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . .2.3V to 6.5V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

4. θ

JA

Tech Brief TB379.

5. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Thermal Resistance (Notes 4, 5) θ

8 Ld 2x3 DFN Package . . . . . . . . . . . . 69 10

Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C

Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature

range of the device as follows: T
C

=1µF; CO = 1µF.

IN

PARAMETER SYMBOL TEST CONDITIONS

DC CHARACTERISTICS

Supply Voltage V
Ground Current Quiescent condition: I

Shutdown Current I
UVLO Threshold V

Regulation Voltage Accuracy Initial accuracy at VIN = VO + 0.5V , IO = 10mA, TJ = +25°C -0.7 +0.7 %

Maximum Output Current I
Internal Current Limit I
Dropout Voltage (Note 6) V

Thermal Shutdown Temperature T

AC CHARACTERISTICS

Ripple Rejection I

Output Noise Voltage I

IN

I

DD

DDS

UV+

V

UV-

MAX

LIM
DO1IO

V

DO2IO

V

DO3IO
SD+

T

SD-

LDO active 25 32 µA
LDO disabled @ +25°C 0.1 1.0 µA

= VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = +25°C -0.8 +0.8 %

V

IN

= VO + 0.5V to 5.5V, IO = 10µA to 300mA,

V

IN

T

= -40°C to +125°C

J

Continuous 300 mA

= 300mA; VO < 2.5V 300 500 mV
= 300mA; 2.5V ≤ VO ≤ 2.8V 250 400 mV
= 300mA; VO > 2.8V 200 325 mV

= 10mA, VIN = 2.8V (min), VO = 1.8V, C

O

@ 1kHz 90 dB
@ 10kHz 70 dB
@ 100kHz 50 dB

= 100µA, VO = 1.5V, TA = +25°C, C

O

BW = 10Hz to 100kHz

= -40°C to +85°C; VIN = (VO + 0.5V) to 5.5V with a minimum VIN of 2.3V;

A

MIN

(Note 7) TYP

2.3 6.5 V

= 0µA

O

1.9 2.1 2.3 V

1.6 1.8 2.0 V

-1.8 +1.8 %

350 475 600 mA

= 0.1µF

BYP

= 0.1µF

BYP

(°C/W) θJC (°C/W)

JA

MAX

(Note 7) UNITS

145 °C
110 °C

30 µV

RMS

3

FN6433.2

March 27, 2008

ISL9001A

www.BDTIC.com/Intersil

Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature

range of the device as follows: T

=1µF; CO = 1µF. (Continued)

C

IN

PARAMETER SYMBOL TEST CONDITIONS

DEVICE START-UP CHARACTERISTICS

Device Enable Time t

LDO Soft-Start Ramp Rate t

SSR

Time from assertion of the ENx pin to when the output

EN

voltage reaches 95% of the VO (nom)
Slope of linear portion of LDO output voltage ramp during

start-up

EN PIN CHARACTERISTICS

Input Low Voltage V
Input High Voltage V
Input Leakage Current IIL, I
Pin Capacitance C

PIN CHARACTERISTICS

POR

POR Thresholds V

Delay t

POR

POR Pin Output Low Voltage V

Pin Internal Pull-up

POR

POR+

V

POR-

PLH

t

PHL

R

POR

IL
IH

IH

Informative 5 pF

PIN

As a percentage of nominal output voltage 91 94 97 %

C

= 0.01µF 100 200 300 ms

POR

@ IOL = 1.0mA 0.2 V

OL

Resistance

NOTES:

6. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V.

7. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.

= -40°C to +85°C; VIN = (VO + 0.5V) to 5.5V with a minimum VIN of 2.3V;

A

MIN

(Note 7) TYP

MAX

(Note 7) UNITS

250 500 µs

30 60 µs/V

-0.3 0.5 V

1.4 V

+ 0.3 V

IN

0.1 µA

87 90 93 %

25 µs

78 100 180 kΩ

EN

VO

POR

t

EN

V

POR+

V

POR+

<t

PHL

t

PHL

V

POR-

t

PLH

V

POR-

FIGURE 1. TIMING PARAMETER DEFINITION

4

FN6433.2

March 27, 2008

Typical Performance Curves

www.BDTIC.com/Intersil

0.8
VO = 3.3V

0.6

0.4

0.2

-40°C

0.0

-0.2

OUTPUT VOLTAGE, VO (%)

-0.4

-0.6

-0.8

3.8 4.2 6.25.8
INPUT VOLTAGE (V)

+25°C

+85°C

FIGURE 2. OUTPUT VOLTAGE vs INPUT VOL TAGE (3.3V

OUTPUT)

I

LOAD

= 0mA

ISL9001A

6.63.4 4.6 5.0 5.4

0.10

+25°C

(mA)

O

VIN = 3.8V

= 3.3V

V

O

-40°C

-0.02

-0.04

-0.06

OUTPUT VOLTAGE CHANGE (%)

-0.08

-0.10

0.08

0.06

0.04

0.02

0.00

+85°C

100 200 300 4000

50 150 250 350

LOAD CURRENT - I

FIGURE 3. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT

0.10

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

-0.06

OUTPUT VOLTAGE CHANGE (%)

-0.08

-0.10

VIN = 3.8V

V

= 3.3V

O

= 0mA

I

LOAD

-10 20 50 110-40

-25 5 35 8065 95 125
TEMPERATURE (°C)

3.4

IO = 0mA

3.3

3.2
IO = 150mA

3.1

IO = 300mA

3.0

OUTPUT VOLTAGE, VO (V)

2.9

2.8

3.1 3.6 4.1 4.6 5.1 6.15.6
INPUT VOLTAGE (V)

VO = 3.3V

FIGURE 4. OUTPUT VOLTAGE CHANGE vs TEMPERATURE FIGURE 5. OUTPUT VOLTAGE vs INPUT VOL TAGE (3.3V

OUTPUT)

350

300

(mV)

250

DO

200

150

100

DROPOUT VOLTAGE, V

50

VO = 2.8V

VO = 3.3V

OUTPUT VOLTAGE, VO (V)

2.9

2.8

2.7

2.6

2.5

2.4

IO = 0mA

IO = 300mA

VO = 2.8V

IO = 150mA

6.5

2.3

2.6 3.1 3.6 4.1 4.6 5.1 6.1
INPUT VOLTAGE (V)

5.6

FIGURE 6. OUTPUT VOLTAGE vs INPUT VOL TAGE (2.8V

6.5

0

FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT

OUTPUT)

5

50 100 150 200 250 300 350 4000

OUTPUT LOAD (mA)

FN6433.2

March 27, 2008

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

350

VO = 3.3V

300

250

(mV)

DROPOUT VOLTAGE, V

DO

200

+85°C

150

100

50

+25°C

-40°C

ISL9001A

GROUND CURRENT (µA)

40

35

+125°C

30

25

20

15

+25°C

-40°C

VO = 3.3V

0

50 100 150 200 250 300 350 4000

OUTPUT LOAD (mA)

10

3.0 3.5 4.58 5.5 6.0

4.0 5.0 6.5
INPUT VOLTAGE (V)

FIGURE 8. DROPOUT VOLTAGE vs LOAD CURRENT FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE

GROUND CURRENT (µA)

40

35

30

25

20

VIN = 3.8V

= 3.3V

15

10

-10 20 50 110-40

-25 5 35 8065 95 125
TEMPERATURE (°C)

I

LOAD

V

O

= 0µA

200
180
160
140
120
100

GROUND CURRENT (µA)

+85°C

+25°C

80
60
40
20

0

50 100 150 200 250 4000

LOAD CURRENT (mA)

-40°C

= 3.8V

V

IN

VO = 3.3V

350300

FIGURE 10. GROUND CURRENT vs LOAD FIGURE 11. GROUND CURRENT vs TEMPERATURE

VO = 2.85V

= 150mA

I

L

5

4

V

3

VOLTAGE (V)

2

1

0

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 5.0

IN

V

O

POR

TIME (s)

4.0 4.5

3

2

1

VO (V)VEN (V)

0

5

0

0.2 0.4

FIGURE 12. POWER-UP/POWER-DOWN FIGURE 13. TURN-ON/TURN-OFF RESPONSE

6

0.6

0.8 1.0 1.2 1.4 1.60
TIME (ms)

VIN = 5.0V

VO = 2.85V

IL = 150mA

C

= 0.01µF

C

BYP

1.8 2.0

March 27, 2008

= 1µF

L

FN6433.2

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

ISL9001A

4.3V

3.6V

10mV/DIV

400µs/DIV

I

LOAD

C

BYP

VO = 3.3V

= 300mA

C

LOAD

= 0.01µF

= 1µF

4.2V

3.5V

10mV/DIV

400µs/DIV

I

LOAD

C

VO = 2.8V

= 300mA

C

LOAD

BYP

= 0.01µF

FIGURE 14. LINE TRANSIENT RESPONSE, 3.3V OUTPUT FIGURE 15. LINE TR ANSIENT RESPONSE, 2.8V OUTPUT

1000

VO (25mV/DIV)

100

= 1µF

300mA

100µA

10

V

= 3.6V

IN

= 1.8V

V

O

= 10mA

I

LOAD

= 0.1µF

C

1

BYP

C

= 1µF

IN

= 1µF

SPECTRAL NOISE DENSITY (nV/√Hz)

C

LOAD

0.1
10 100 1k 10k 100k 1M

FREQUENCY (Hz)

I

LOAD

100µs/DIV

= 1.8V

V

O

VIN = 2.8V

FIGURE 16. LOAD TRANSIENT RESPONSE FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY

100

90
80
70
60
50

PSRR (dB)

40
30
20
10

0

100 1k 10k 100k 1M

FREQUENCY (Hz)

VIN = 3.6V

V

I

O

C

BYP

C

LOAD

= 1.8V

O

= 10mA

= 0.1µF

= 1µF

FIGURE 18. PSRR vs FREQUENCY

7

FN6433.2

March 27, 2008

ISL9001A

www.BDTIC.com/Intersil

Pin Description

PIN

NUMBER PIN NAME DESCRIPTION

1 VIN Supply Voltage/LDO Input:

Connect a 1µF capacitor to GND.
2 EN LDO Enable.
3 CBYP Reference Bypass Capacitor Pin:

Optionally connect capacitor of value 0.01µF to 0.1µF between this pin and GND to achieve lowest noise and

highest PSRR.
4 CPOR POR Delay Setting Capacitor Pin:

Connect a capacitor between this pin and GND to delay the POR

its specified voltage level. (200ms delay per 0.01µF).
5 GND GND is the connection to system ground. Connect to PCB Ground plane.
6 NC Do not connect.
7POR

Open-drain POR Output (active-low):

Internally connected to VO through 100kΩ resistor.
8 VO LDO Output:

Connect capacitor of value 1µF to 10µF to GND (1µF recommended).

Typical Application

output release after the output reaches 94% of

V

(2.3V TO 5V)

IN

ENABLE

OFF

ON

ISL9001A

1

VIN

2

EN

3

CBYP

C1 C2 C3

4

C4

CPOR

C1, C3: 1µF X5R CERAMIC CAPACITOR

C2: 0.1µF X7R CERAMIC CAPACITOR

C4: 0.01µF X7R CERAMIC CAPACITOR

VO

POR

GND

8

7

5

V

OUT

OK

V

OUT

TOO LOW

V

OUT

(200ms DELAY,
C4 = 0.01µF)

8

FN6433.2

March 27, 2008

Block Diagram

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ISL9001A

VIN

EN

UVLO

CONTROL

LOGIC

BANDGAP AND
TEMPERATURE

SENSOR

SHORT CIRCUIT,

THERMAL PROTECTION,

SOFT-START

+

-

VOLTAGE AND

REFERENCE

GENERATOR

CBYP

GND

1.0V

0.94V

0.9V

1.0V

+

-

CPOR

POR

DELAY

GND

VO

VO

100k

POR

Functional Description

The ISL9001A contains all circuitry required to implement a
high performance LDO. High performance is achieved
through a circuit that delivers fast transient response to
varying load conditions. In a quiescent condition, the
ISL9001A adjusts its biasing to achieve the lowest standby
current consumption.

The device also integrates current limit protection, smart
thermal shutdown protection, and soft-start. Smart thermal
shutdown protects the device against overheating.

Power Control

The ISL9001A has an enable pin (EN) to control power to
the LDO output. When EN is low, the device is in shutdown
mode. During this condition, all on-chip circuits are off, and
the device draws minimum current, typically less than 0.1µA.
When the enable pin is asserted, the device first polls the
output of the UVLO detector to ensure that VIN voltage is at
least about 2.1V. Once verified, the device initiates a start-up
sequence. During the start-up sequence, trim settings are
first read and latched. Then, sequentially, the bandgap,
reference voltage and current generation circuitry power up.
Once the references are stable, a fast-start circuit quickly
charges the external reference bypass capacitor (connected
to the CBYP pin) to the proper operating voltage. Once the
bypass capacitor has been charged, the LDO powers up.

During operation, whenever the VIN voltage drops below
about 1.84V, the ISL9001A immediately disables the LDO
output. When VIN rises back above 2.1V, the device
re-initiates its start-up sequence and LDO operation will
resume automatically.

Reference Generation

The reference generation circuitry includes a trimmed
bandgap, a trimmed voltage reference divider, a trimmed
current reference generator, and an RC noise filter . The filter
includes the external capacitor connected to the CBYP pin.
A 0.01µF capacitor connected CBYP implements a 100Hz
lowpass filter, and is recommended for most high
performance applications. For the lowest noise application, a

0.1µF CBYP capacitor should be used. This filters the
reference noise to below the 10Hz to 1kHz frequency band,
which is crucial in many noise-sensitive applications.

The bandgap generates a zero temperature coefficient (TC)
voltage for the reference divider. The reference divider
provides the regulation reference, POR detection thresholds,
and other voltage references required for current generation
and over-temperature detection.

The current generator outputs references required for
adaptive biasing as well as references for LDO output
current limit and thermal shutdown determination.

9

FN6433.2

March 27, 2008

ISL9001A

www.BDTIC.com/Intersil

LDO Regulation and Programmable Output Divider

The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9001A provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1µF to 10µF output
capacitor that has a tolerance better than 20% and ESR less
than 200mΩ. The design is performance-optimized for a 1µF
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7µF is not recommended as LDO
performance improvement is minimal.

Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge. The
ISL9001A provides short-circuit protection by limiting the
output current to about 425mA.

The LDO uses an independently trimmed 1V reference as its
input. An internal resistor divider drops the LDO output
voltage down to 1V . This is compared to the 1V reference for
regulation. The resistor division ratio is programmed in the
factory.

Power-On Reset Generation

The ISL9001A has a Power-on Reset signal generation
circuit, which indicates that output power is good. The POR
signal is generated as follows.

The power-good state is exited when the LDO output falls
below 90% of the expected output voltage for a period longer
than the PGOOD exit delay time. While power-good is false,
the ISL9001A pulls the POR pin low.

The PGOOD entry and exit delays are determined by the
value of an external capacitor connected to the CPOR pin.
For a 0.01µF capacitor, the entry and exit delays are 200ms
and 25µs respectively. Larger or smaller capacitor values will
yield proportionately longer or shorter delay times. The POR
exit delay should never be allowed to be less than 10µs to
ensure sufficient immunity against transient induced false
POR triggering.

Overheat Detection

The bandgap outputs a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about +140°C, if the LDO is
sourcing more than 50mA, it shuts down until the die cools
sufficiently . Once the die temperature falls back below about
+110°C, the disabled LDO is re-enabled and soft-start
automatically takes place.

A POR comparator continuously monitors the output of the
LDO. The LDO enters a power-good state when the output
voltage is above 94% of the expected output voltage for a
period exceeding the LDO PGOOD entry delay time (see the
following). In the power-good state, the open-drain POR
output is in a high-impedance state. An internal 100kΩ
pull-up resistor pulls the pin up to the LDO output voltage. An
external resistor can be added between the POR
the LDO output for a faster rise time, however, the POR
output should not connect through an external resistor to a
supply greater than the LDO voltage.

output and

10

FN6433.2

March 27, 2008

Dual Flat No-Lead Plastic Package (DFN)

www.BDTIC.com/Intersil

ISL9001A

(DATUM A)

NX (b)

5

INDEX

AREA

SEATING

(DATUM B)

6

INDEX
AREA

NX L

8

A

6

C

PLANE

(A1)

D

TOP VIEW

SIDE VIEW

D2

D2/2

12

N

N-1

e

(Nd-1)Xe

REF.

BOTTOM VIEW

2X

A3

NX b

L8.2x3

ABC0.15

2X

0.15

CB

E

//

A

87

NX k

E2

E2/2

5

0.10

C

L

0.10

0.08

L

C

C

BAMC

8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

NOTESMIN NOMINAL MAX

A 0.80 0.90 1.00 ­A1 - - 0.05 ­A3 0.20 REF -

b 0.20 0.25 0.32 5,8

D 2.00 BSC ­D2 1.50 1.65 1.75 7,8

E 3.00 BSC ­E2 1.65 1.80 1.90 7,8

e 0.50 BSC ­k0.20 - - ­L 0.30 0.40 0.50 8

N82
Nd 4 3

Rev. 0 6/04

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

SECTION "C-C"

FOR EVEN TERMINAL/SIDE

CC

e

TERMINAL TIP

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subs idi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

11

FN6433.2

March 27, 2008