The ISL88731A is a highly integrated Lithium-ion battery
charger controller, programmable over the SMBus system
management bus (SMBus). The ISL88731A is intended to be
used in a smart battery charger (SBC) within a smart battery
system (SBS) that throttles the charge power such that the
current from the AC-adapter is automatically limited. High
efficiency is achieved with a DC/DC synchronous-rectifier buck
converter, equipped with diode emulation for enhanced light
load efficiency and system bus boosting prevention. The
ISL88731A charges one to four Lithium-ion series cells, and
delivers up to 8A charge current. Integrated MOSFET drivers
and bootstrap diode result in fewer components and smaller
implementation area. Low offset current-sense amplifiers
provide high accuracy with 10mΩ sense resistors. The
ISL88731A provides 0.5% end-of-charge battery voltage
accuracy.
The ISL88731A provides a digital output that indicates the
presence of the AC-adapter as well as an analog output which
indicates the adapter current within 4% accuracy.
The ISL88731A is available in a small 5mmx5mm 28 Ld thin
(0.8mm) QFN package. An evaluation kit is available to reduce
design time. The ISL88731A is available in Pb-Free packages.
1. Add “-T*” suffix for tape and reel. Please refer to TB347
reel specifications.
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL88731A
techbrief TB363
PART
MARKING
. For more information on MSL please see
.
TEMP
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
for details on
June 8, 2011
FN6738.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2008, 2009, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
VDDP, ICM, VCC to GND, VDDP to PGND . . . . . . . . . . . . . . . . . . -0.3V to +6V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
SDA/SCL Input Low VoltageVDDSMB = 2.7V to 5.5V0.8V
SDA/SCL Input High VoltageVDDSMB = 2.7V to 5.5V2V
SDA/SCL Input Bias CurrentVDDSMB = 2.7V to 5.5V-11µA
SDA, Output Sink CurrentV
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
= -10°C to +100°C. Boldface limits apply over the operating temperature range, -10°C to +100°C. (Continued)
A
MIN
(Note 6)TYP
= 28V, V
DCON
= -100mA0.91.6Ω
UGATE
= 10mA 1.42.5Ω
UGATE
= +10mA 1.42.5Ω
LGATE
= -100mA 0.91.6Ω
LGATE
falling LGATE to rising UGATE
ICOMP, VCOMP
= 0.4V715mA
SDA
CSON
= V
= 20V02µA
PHASE
355080ns
< 3.5V200300400mV
MAX
(Note 6) UNITS
SMBus Timing SpecificationVDDSMB = 2.7V TO 5.5V
PARAMETERSSYMBOLCONDITIONSMINT YPMAXUNITS
SMBus FrequencyFSMB10100kHz
Bus Free TimeTBUF4.7µs
Start Condition Hold Time from SCLTHD:STA4µs
Start Condition Setup Time from SCLTSU:STA4.7µs
Stop Condition Setup Time from SCLTSU:STO4µs
SDA Hold Time from SCLTHD:DAT300ns
SDA Setup Time from SCLTSU:DAT250ns
SCL Low Timeout (Note 7)TTIMEOUT222530ms
SCL Low PeriodTLOW4.7µs
SCL High PeriodTHIGH4µs
Maximum Charging Period Without a SMBus Write to
ChargeVoltage or ChargeCurrent Register
NOTES:
7. If SCL is low for longer than the specified time, the charger is disabled.
5
140180220s
FN6738.3
June 8, 2011
ISL88731A
Typical Operating Performance DCIN = 20V, 3S2P Li-Battery, T
5.15
5.10
5.05
5.00
VDDP (V)
4.95
4.90
4.85
020406080100
VDDP LOAD CURRENT (mA)
FIGURE 3. VDD LOAD REGULATION
15
10
5
0
-5
ICM ACCURACY (%)
-10
3.23
3.22
3.21
3.20
VREF (V)
3.19
3.18
3.17
050100150200
FIGURE 4. VREF LOAD REGULATION
13.0
12.5
12.0
11.5
11.0
BATTERY VOLTAGE
10.5
ICHG (A)
= +25°C, unless otherwise noted.
A
I VREF (µA)
VCHG (V)
1.0%
0.5%
0.0%
-0.5%
-1.0%
3.5
3.0
2.5
2.0
1.5
1.0
0.5
BATTERY CURRENT
-15
123567
48
ADAPTER CURRENT (A)
FIGURE 5. ICM ACCURACY vs AC-ADAPTER CURRENT
VCOMP
ICOMP
CHARGE
CURRENT
INDUCTOR
CURRENT
FIGURE 7. CHARGE ENABLE
10.0
0 20406080100120140160
TIME (MINUTES)
FIGURE 6. TYPICAL CHARGING VOLTAGE AND CURRENT
ICOMP
VCOMP
CHARGE
CURRENT
INDUCTOR
CURRENT
FIGURE 8. CHARGE DISABLE
0.0
6
FN6738.3
June 8, 2011
ISL88731A
Typical Operating Performance DCIN = 20V, 3S2P Li-Battery, T
UGATE
PHASE
FIGURE 9. SWITCHING WAVEFORMS AT DIODE EMULATION
CSON/
V
BATTERY
LGATE
INDUCTOR
CURRENT
PHASE
FIGURE 10. SWITCHING WAVEFORMS IN CC MODE
= +25°C, unless otherwise noted.
A
UGATE
INDUCTOR
CURRENT
LGATE
CSON/
V
BATTERY
BATTERY
CURRENT
FIGURE 11. BATTERY REMOVAL
ADAPTER
CURRENT
FIGURE 13. LOAD TRANSIENT RESPONSE
SYSTEM
LOAD
BATTERY
VOLTAGE
CHARGE
CURRENT
BATTERY
CURRENT
FIGURE 12. BATTERY INSERTION
100
95
90
85
80
75
70
04 8
16.8V
BATTERY
12.6V
BATTERY
8.4V
BATTERY
4.2V
BATTERY
26
CHARGE CURRENT (A)
FIGURE 14. EFFICIENCY vs CHARGE CURRENT AND BATTERY
VOLTAGE (EFFICIENCY DCIN = 20V)
7
FN6738.3
June 8, 2011
ISL88731A
Functional Pin Descriptions
BOOT
High-Side Power MOSFET Driver Power-Supply Connection.
Connect a 0.1µF capacitor from BOOT to PHASE.
UGATE
High-Side Power MOSFET Driver Output. Connect to the high-side
N-Channel MOSFET gate.
LGATE
Low-Side Power MOSFET Driver Output. Connect to low-side
N-Channel MOSFET. LGATE drives between VDDP and PGND.
PHASE
High-Side Power MOSFET Driver Source Connection. Connect to
the source of the high-side N-Channel MOSFET.
CSOP
Charge Current-Sense Positive Input.
CSON
Charge Current-Sense Negative Input.
CSSP
Input Current-Sense Positive Input.
CSSN
Input Current-Sense Negative Input.
DCIN
Charger Bias Supply Input. Bypass DCIN with a 0.1µF capacitor to
GND.
ACIN
AC-adapter Detection Input. Connect to a resistor divider from the
AC-adapter output.
ACOK
AC Detect Output. This open drain output is high impedance
when ACIN is greater than 3.2V. The ACOK output remains low
when the ISL88731A is powered down. Connect a 10k pull-up
resistor from ACOK to VDDSMB.
PGND
Power Ground. Connect PGND to the source of the low side
MOSFET.
VCC
Power input for internal analog circuits. Connect a 4.7Ω resistor
from VCC to VDDP and a 1µF ceramic capacitor from VCC to
ground.
VDDP
Linear Regulator Output. VDDP is the output of the 5.2V linear
regulator supplied from DCIN. VDDP also directly supplies the
LGATE driver and the BOOT strap diode. Bypass with a 1µF
ceramic capacitor from VDDP to PGND.
ICOMP
Compensation Point for the charging current and adapter current
regulation Loop. Connect 0.01µF to GND. See “Voltage Control
Loop” on page 20 for details of selecting the ICOMP capacitor.
VCOMP
Compensation Point for the voltage regulation loop. Connect
4.7kΩ in series with 0.01µF to GND. See “Voltage Control Loop”
on page 20 for details on selecting VCOMP components.
VFB
Feedback for the Battery Voltage.
VDDSMB
SMBus interface Supply Voltage Input. Bypass with a 0.1µF
capacitor to GND.
SDA
SMBus Data I/O. Open-drain Output. Connect an external pull-up
resistor according to SMBus specifications.
SCL
SMBus Clock Input. Connect an external pull-up resistor
according to SMBus specifications.
GND
Analog Ground. Connect directly to the backside paddle. Connect
to PGND close to the output capacitor.
ICM
Input Current Monitor Output. ICM voltage equals 20 x (V
).
V
CSSN
CSSP
-
VREF
VREF is a reference output pin. It is internally compensated. Do
not connect a decoupling capacitor.
8
Back Side Paddle
Connect the backside paddle to GND.
NC
No Connect. Pins 1, 5, 7 and 14 are not connected.
FN6738.3
June 8, 2011
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