®
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ISL8563E
Data Sheet July 2004
+/-15kV ESD Protected, +3V to +5.5V,
1Microamp, 250kbps, EIA/TIA-562,
EIA/TIA-232 Transmitters/Receivers
The Intersil ISL8563E contains 3.0V to 5.5V powered
transmitters/receivers which meet ElA/TIA-562 and
ElA/TIA-232 specifications, even at V
they provide
±15kV ESD protection (IEC61000-4-2 Air Gap
= 3.0V. Additionally,
CC
and Human Body Model) on transmitter outputs and receiver
inputs (RS-562 pins). Targeted applications are PDAs,
Palmtops, and notebook and laptop computers where the
low operational, and even lower standby, power
consumption is critical. Efficient on-chip charge pumps,
coupled with a manual powerdown function, reduce the
standby supply current to a 1µA trickle. Small footprint
packaging, and the use of small, low value capacitors ensure
board space savings as well. Data rates greater than
250kbps are guaranteed at worst case load conditions. The
ISL8563E is fully compatible with 3.3V only systems, mixed
3.3V and 5.0V systems, and 5.0V only systems.
This product features an improved charge pump which
delivers
±5V transmitter supplies, allowing the use of the
ISL8563E in RS-562 and RS-232 applications. RS-562
applications will benefit from the improved noise immunity
afforded by the
±5V output swing capability.
Table 1 summarizes the features of the device represented
by this data sheet, while Application Note AN9863
summarizes the features of each device comprising the 3V
RS-232 family.
Ordering Information
TEMP.
PAR T N O.
ISL8563ECB 0 to 70 18 Ld SOIC M18.3
ISL8563ECB-T 0 to 70 Tape and Reel M18.3
RANGE (°C) PACKAGE
PKG.
DWG. #
FN6002.2
Features
• ESD Protection for RS-562 I/O Pins to ±15kV (IEC61000)
• Drop in Replacement for MAX563, with Improved Output
Voltage (
±5V) for Enhanced Noise Immunity
• Meets EIA/TIA-562, and EIA/TIA-232 Specifications at 3V
• RS-232 Compatible Outputs at 2.7V
• Latch-Up Free
• On-Chip Voltage Converters Require Only Four External
0.1µF Capacitors
• Receivers Active in Powerdown
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps
• Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . . 4V/µs
• Wide Power Supply Range . . . . . . . Single +3V to +5.5V
• Low Supply Current in Powerdown State. . . . . . . . . . .1µA
Applications
• Any System Requiring RS-562/RS-232 Communication
Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Digital Cameras
- Bar Code Readers
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN9863, “3V to +5.5V, 250K-1Mbps,
RS-232 Transmitters/Receivers”
Pinout
ISL8563E (SOIC)
TOP VIEW
T2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
SHDN
EN
1
C1+
2
3
V+
4
C1-
5
C2+
C2-
6
V-
7
8
OUT
R2
9
IN
Copyright © Intersil Americas Inc. 2001, 2004. All Rights Reserved
18
V
17
CC
GND
16
T1
15
OUT
R1
14
IN
R1
13
OUT
T1
12
IN
T2
11
IN
10
R2
OUT
ISL8563E
www.BDTIC.com/Intersil
TABLE 1. SUMMARY OF FEATURES
PART NUMBER
NO. OF
Tx.
NO. OF
Rx.
NO. OF
MONITOR Rx.
(R
)
OUTB
DATA
RATE
(kbps)
Rx. ENABLE
FUNCTION?
READY
OUTPUT?
MANUAL
POWER-
DOWN?
ISL8563E 2 2 0 250 Yes No Yes No
Pin Descriptions
PIN FUNCTION
AUTOMATIC
POWERDOWN
FUNCTION?
V
CC
System Power Supply Input (3.0V to 5.5V).
V+ Internally Generated Positive Transmitter Supply (+5.5V).
V- Internally Generated Negative Transmitter Supply (-5.5V).
GND Ground Connection.
C1+ External Capacitor (Voltage Doubler) is connected to this lead.
C1- External Capacitor (Voltage Doubler) is connected to this lead.
C2+ External Capacitor (Voltage Inverter) is connected to this lead.
C2- External Capacitor (Voltage Inverter) is connected to this lead.
T
T
OUT
R
R
OUT
EN
SHDN
TTL/CMOS Compatible Transmitter Inputs with pull-up resistors.
IN
±15kV ESD Protected, RS-562/RS-232 level (nominally ±5.5V) transmitter outputs.
±15kV ESD Protected, RS-562/RS-232 compatible receiver inputs.
IN
TTL/CMOS Level Receiver Outputs.
Active Low Receiver Enable Control.
Active Low Input which shuts down transmitters and on-board power supply, to place device in low power mode.
Typical Operating Circuit
+3.3V
TTL/CMOS
LOGIC LEVELS
C
0.1µF
C
0.1µF
T1
T2
R1
OUT
R2
OUT
+
0.1µF
2
1
2
IN
IN
C1+
+
4
C1-
5
C2+
+
6
C2-
400kΩ
12
400kΩ
11
13
10
1
EN
ISL8563E
V
V
CC
V
CC
R
R
CC
17
V+
V-
T
1
T
2
5kΩ
1
5kΩ
2
C
3
0.1µF
+
3
7
C
4
0.1µF
+
15
T1
OUT
8
T2
OUT
IN
IN
RS-562/232
LEVELS
14
R1
9
R2
18
GND
SHDN
16
2
V
CC
ISL8563E
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Absolute Maximum Ratings Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
, EN, SHDN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
T
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
R
IN
Output Voltages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
T
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
R
OUT
Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
T
OUT
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
1. θ
JA
Thermal Resistance (Typical, Note 1) θ
18 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
(°C/W)
JA
Operating Conditions
Temperature Range
ISL8563ECX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Electrical Specifications Test Conditions: V
Typicals are at T
PARAMETER TEST CONDITIONS
RS-562/RS-232 TRANSMITTERS
Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V
Maximum Data Rate R
Input Logic Threshold Low T
Input Logic Threshold High T
Transmitter Pull-Up Input Current T
Output Leakage Current V
Output Resistance V
Output Short-Circuit Current V
RS-562/RS-232 RECEIVERS
Input Voltage Range Full -25 - 25 V
Input Threshold Low V
Input Threshold High V
Input Hysteresis V
Input Resistance Full 3 5 7 kΩ
Output Voltage Low I
Output Voltage High I
Output Leakage Current EN
Input Logic Threshold Low Full - - 0.8 V
EN
EN
Input Logic Threshold High VCC = 3.0V to 5.0V Full 2.4 - - V
POWER SUPPLY
Operating Supply Voltage Full 3.0 - 5.5 V
Supply Current SHDN
= 3kΩ, CL = 1000pF, One Transmitter Switching and
L
Maintaining ±5V Output Swing
IN
IN
IN
= ±12V, VCC = 0V or 3.6V to 5.5V, SHDN = GND Full - - ±10 µA
OUT
= V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Ω
CC
= 0V Full - ±35 ±60 mA
OUT
= 3.3V Full - 1.2 0.6 V
CC
= 5.0V Full - 1.5 0.8 V
V
CC
= 3.3V Full 2.4 1.5 - V
CC
= 5.0V Full 2.4 1.8 - V
V
CC
= 3.0V to 3.6V Full 0.1 0.5 1.0 V
CC
= 3.2mA Full - - 0.4 V
OUT
= -1.0mA Full V
OUT
= V
CC
= V
CC
= 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
CC
= 25°C
A
TEMP
(°C) MIN TYP MAX UNITS
Full 250 500 - kbps
Full - - 0.8 V
VCC = 3.0V to 5.0V Full 2.4 - - V
SHDN = V
SHDN
All Outputs Unloaded Full - 0.5 6.0 mA
All Outputs loaded, R
CC
= GND Full - ±0.01 ±1.0 µA
= 3kΩ 25 - 14 - mA
L
Full - 2 20 µA
Full - ±0.05 ±10 µA
CC
-0.6 V
-0.1 - V
CC
3
ISL8563E
www.BDTIC.com/Intersil
Electrical Specifications Test Conditions: V
Typicals are at T
= 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
CC
= 25°C (Continued)
A
TEMP
PARAMETER TEST CONDITIONS
(°C) MIN TYP MAX UNITS
Supply Current, Powerdown SHDN = GND 25 - 1 10 µA
Full - 1 25 µA
SHDN
Input Leakage Current Full - ±0.01 ±1.0 µA
Input Logic Threshold Low Full - - 0.8 V
SHDN
Input Logic Threshold High VCC = 3.0V to 5.0V Full 2.4 - - V
SHDN
AC CHARACTERISTICS
Transition Region Slew Rate V
= 3.3V, RL = 3kΩ to 7kΩ, Measured From 3V to -3V or
CC
-3V to 3V, C
= 50pF to 2500pF
L
Transmitter Propagation Delay Transmitter Input to
Transmitter Output,
= 1000pF, RL = 3kΩ
C
L
Receiver Propagation Delay Receiver Input to Receiver
Output, C
= 150pF
L
Receiver Output Enable Time Figure 1 t
Receiver Output Disable Time Figure 1 t
Transmitter Output Enable Time Figure 2 t
Transmitter Output Disable Time Figure 2 t
Transmitter Skew t
Receiver Skew t
PHL
PHL
- t
(Note 2) 25 - 100 - ns
PLH
- t
(Note 3) 25 - 100 - ns
PLH
t
(Note 2) Full - 1 3.5 µs
PHL
(Note 2) Full - 1 3.5 µs
t
PLH
(Note 3) Full - 0.3 1.0 µs
t
PHL
(Note 3) Full - 0.3 1.0 µs
t
PLH
ER
DR
ET
DT
25 4 - 30 V/µs
Full - 125 500 ns
Full - 160 500 ns
25 - 17 - µs
25 - 600 - ns
ESD PERFORMANCE
RS-562 Pins (T
, RIN) Human Body Model 25 - ±15 - kV
OUT
IEC61000-4-2 Contact Discharge 25 - ±8-kV
IEC61000-4-2 Air Gap Discharge 25 - ±15 - kV
All Other Pins Human Body Model 25 - ±3-kV
NOTES:
2. Transmitter is measured at the transmitter zero crossing points.
3. Receiver is measured at the receiver 50 percent crossing points.
Test Waveforms
V
INPUT
EN
RECEIVER
OUTPUT
EN
INPUT
RECEIVER
OUTPUT
FIGURE 1. RECEIVER OUTPUT ENABLE AND DISABLE TIMING
CC
t
ER
0.5V
CC
CL = 150pF to GND
= 1kΩ to 0.5V
R
L
0V
V
OH
V
OL
V
V
OH
OL
CC
- 0.1V
+ 0.1V
VCC - 0.6V
+0.4V
CL = 150pF to GND
R
4
0V
V
CC
t
DR
0.5V
CC
= 1kΩ to 0.5V
L
CC
V
CC
V+
V-
0V
0V
CL = 50pF
= 3kΩ
R
L
V
CC
+3.7V
-3.7V
+3.7V
-3.7V
t
0V
ET
t
DT
CL = 50pF
= 3kΩ
R
L
0V
SHDN
INPUT
TRANSMITTER
OUTPUT
INPUT
SHDN
TRANSMITTER
OUTPUT
FIGURE 2. TRANSMITTER OUTPUT ENABLE AND DISABLE
TIMING
ISL8563E
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Detailed Description
The ISL8563E operates from a single +3V to +5.5V supply,
guarantees a 250kbps minimum data rate, requires only four
small external 0.1µF capacitors, features low power
consumption, and meets all ElA/TIA-562 and EIA/TIA-232
specifications. The circuit is divided into three sections: The
charge pump, the transmitters, and the receivers.
(V
= 0V). The receivers’ Schmitt trigger input stage uses
CC
hysteresis (even in powerdown) to increase noise immunity
and decrease errors due to slow input signal transitions.
The ISL8563E inverting receivers disable only when EN
is
driven high. Standard receivers driving powered down
peripherals must be disabled to prevent current flow through
the peripheral’s protection diodes (see Figures 4 and 5).
Charge-Pump
Intersil’s new ISL8563E utilizes regulated on-chip dual
charge pumps as voltage doublers, and voltage inverters to
generate ±5.5V transmitter supplies from a V
supply as
CC
low as 3.0V. This allows these devices to maintain RS-232
compliant output levels over the ±10% tolerance range of
3.3V powered systems. The efficient on-chip power supplies
require only four small, external 0.1µF capacitors for the
voltage doubler and inverter functions over the full V
CC
range. The charge pumps operate discontinuously (i.e., they
turn off as soon as the V+ and V- supplies are pumped up to
the nominal values), resulting in significant power savings.
Transmitters
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-562/232
output levels. Coupled with the on-chip ±5.5V supplies,
these transmitters deliver true RS-562/232 levels over a
wide range of single supply system voltages.
All transmitter outputs disable and assume a high
impedance state when the device enters the powerdown
mode (see Table 2). These outputs may be driven to ±12V
when disabled.
All devices guarantee a 250kbps data rate (V
full load conditions (3kΩ and 1000pF), V
CC
= ±5V) for
OUT
≥ 3.0V, with one
transmitter operating at full speed. Under more typical
conditions of V
≥ 3.3V, RL = 3kΩ, and CL = 250pF, one
CC
transmitter easily operates at 900kbps.
Unused transmitter inputs may be left unconnected because
they will be pulled to V
by the on-chip pull-up resistors.
CC
Forcing the ISL8563E into power down disables the pull-up
resistors to further minimize power.
Receivers
The ISL8563E contains standard inverting receivers that
three-state via the EN
RS-562/232 signals to CMOS output levels and accept
inputs up to ±25V while presenting the required 3kΩ to 7kΩ
input impedance (see Figure 3) even if the power is off
control line. All the receivers convert
V
CC
R
XIN
-25V ≤ V
FIGURE 3. INVERTING RECEIVER CONNECTIONS
RIN
≤ +25V
GND
5kΩ
R
GND ≤ V
XOUT
ROUT
≤ V
CC
Powerdown Functionality
This 3V device requires a nominal supply current of 0.3mA
during normal operation (not in powerdown mode). This is
considerably less than the 5mA to 11mA current required by
5V devices. The already low current requirement drops
significantly when the device enters powerdown mode. In
powerdown, supply current drops to 1µA, because the onchip charge pump turns off (V+ collapses to V
collapses to GND), the transmitter outputs three-state, and
the transmitter input pull-ups disable. This micro-power
mode makes the ISL8563E ideal for battery powered and
portable applications.
Software Controlled (Manual) Powerdown
The ISL8563E, is forced into its low power, stand by state via
a simple shutdown (SHDN
) pin. Driving this pin high enables
normal operation, while driving it low forces the IC into its
powerdown state. Connect SHDN
to VCC if the powerdown
function isn’t needed. Note that all the receiver outputs
remain enabled during shutdown (see Table 2). For the
lowest power consumption during powerdown, the receivers
should also be disabled by driving the EN
next section, and Figures 4 and 5). The time required to exit
powerdown, and resume transmission is less than 30µs.
Receiver ENABLE Control
The device also features an EN input to control the receiver
outputs. Driving EN
placing them in a high impedance state. This is useful to
eliminate supply current, due to a receiver output forward
biasing the protection diode, when driving the input of a
powered down (V
enable input has no effect on transmitters.
high disables all the receiver outputs
= GND) peripheral (see Figure 4). The
CC
, V-
CC
input high (see
TABLE 2. POWERDOWN AND ENABLE LOGIC TRUTH TABLE
INPUT EN INPUT TRANSMITTER OUTPUTS RECEIVER OUTPUTS MODE OF OPERATION
SHDN
L L High-Z Active Manual Powerdown
L H High-Z High-Z Manual Powerdown w/Rcvr. Disabled
H L Active Active Normal Operation
H H Active High-Z Normal Operation w/ Rcvr. Disabled
5
ISL8563E
www.BDTIC.com/Intersil
V
CC
V
CC
V
CC
V
OUT = VCC
Rx
POWERED
DOWN
UART
GND
FIGURE 4. POWER DRAIN THROUGH POWERED DOWN
WAKE-UP
LOGIC
V
CC
POWERED
DOWN
UART
FIGURE 5. DISABLED RECEIVERS PREVENT POWER DRAIN
Tx
PERIPHERAL
TRANSITION
DETECTOR
TO
R
X
T
X
SHDN
= GND, EN = V
SHDN
V
OUT =
= GND
V
R2
T1
CC
HI-Z
OUT
IN
CC
CURRENT
FLOW
OLD
RS-562/232 CHIP
ISL8563E
R2
T1
IN
OUT
Capacitor Selection
The charge pumps operate with 0.1µF (or greater)
capacitors for 3.0V ≤ V
values (by a factor of 2) reduces ripple on the transmitter
outputs and slightly reduces power consumption. C
C
can be increased without increasing C1’s value, however,
4
do not increase C
1
maintain the proper ratios (C
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-.
≤ 5.5V. Increasing the capacitor
CC
, C3, and
2
without also increasing C2, C3, and C4 to
to the other capacitors).
1
Power Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is
adequate. In applications that are particularly sensitive to
power supply noise, decouple V
capacitor of the same value as the charge-pump capacitor C
to ground with a
CC
1
Connect the bypass capacitor as close as possible to the IC.
Operation Down to 2.7V
ISL8563E transmitter outputs meet RS-562 levels (±3.7V), at
the full data rate, with V
as low as 2.7V. RS-562 levels
CC
typically ensure interoperability with RS-232 devices.
Transmitter Outputs When Exiting
Powerdown
Figure 6 shows the response of two transmitter outputs
when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-562/232
levels, with no glitching, ringing, nor undesirable transients.
Each transmitter is loaded with 3kΩ in parallel with 2500pF.
Note that the transmitters enable only when the magnitude
of the supplies exceed approximately 3V.
5V/DIV
2V/DIV
FIGURE 6. TRANSMITTER OUTPUTS WHEN EXITING
SHDN
T1
T2
VCC = +3.3V
C1 - C4 = 0.1µF
TIME (20µs/DIV)
POWERDOWN
High Data Rates
The ISL8563E maintains the RS-232 ±5V minimum
transmitter output voltages even at high data rates. Figure 7
details a transmitter loopback test circuit, and Figure 8
illustrates the loopback test result at 120kbps. For this test,
all transmitters were simultaneously driving RS-232 loads in
parallel with 1000pF, at 120kbps. Figure 9 shows the
loopback results for a single transmitter driving 1000pF and
an RS-232 load at 250kbps. The static transmitters were
also loaded with an RS-232 receiver.
.
6
ISL8563E
www.BDTIC.com/Intersil
V
CC
0.1µF
FIGURE 7. TRANSMITTER LOOPBACK TEST CIRCUIT
5V/DIV.
T1
T1
OUT
R1
OUT
5V/DIV
T1
T1
OUT
+
+
C
C
V
CC
IN
VCC = +3.3V
C1 - C4 = 0.1µF
FIGURE 8. LOOPBACK TEST AT 120kbps
IN
C1+
1
C1-
+
C2+
2
C2-
T
IN
R
OUT
EN
SHDN
V
400kΩ
V
CC
ISL8563E
CC
5µs/DIV.
T
V+
OUT
R
5K
V-
IN
+
C
3
C
4
+
1000pF
Interconnection with 3V and 5V Logic
The ISL8563E directly interfaces with 5V CMOS and TTL
logic families. Nevertheless, with the device at 3.3V, and the
logic supply at 5V, AC, HC, and CD4000 outputs can drive
ISL83563E inputs, but ISL83563E outputs do not reach the
minimum V
for these logic families. See Table 3 for more
IH
information.
TABLE 3. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
SYSTEM
POWER-SUPPLY
VOLTAGE
(V)
3.3 3.3 Compatible with all CMOS families.
5 5 Compatible with all TTL and
5 3.3 Compatible with ACT and HCT
V
CC
SUPPLY
VO LTAG E
(V) COMPATIBILITY
CMOS logic families.
CMOS, and with TTL.
outputs are incompatible with AC,
HC, and CD4000 CMOS inputs.
ISL83563E
±15kV ESD Protection
All pins on Intersil 3V interface devices include ESD
protection structures, but the ISL8XXXE family incorporates
advanced structures which allow the RS-562/232 pins
(transmitter outputs and receiver inputs) to survive ESD
events up to ±15kV. These pins are particularly vulnerable to
ESD damage because they typically connect to an exposed
port on the exterior of the finished product. Simply touching
the port pins, or connecting a cable, can cause an ESD event
that might destroy unprotected ICs. These new ESD
structures protect the device whether or not it is powered up,
protect without allowing any latchup mechanism to activate,
and don’t interfere with RS-562/232 signals as large as ±25V.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge through a 1.5kΩ current limiting resistor,
making the test less severe than the IEC61000 test which
utilizes a 330Ω limiting resistor. The HBM method
determines an ICs ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-562/232 pins on “E” family
devices can withstand HBM ESD events to ±15kV.
R1
OUT
VCC = +3.3V
C1 - C4 = 0.1µF
2µs/DIV
FIGURE 9. LOOPBACK TEST AT 250kbps
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-562/232 pins in this case), and the IC
is tested in its typical application configuration (power
applied) rather than testing each pin-to-pin combination. The
lower current limiting resistor coupled with the larger charge
7
ISL8563E
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storage capacitor yields a test that is much more severe than
the HBM test. The extra ESD protection built into this
device’s RS-562/232 pins allows the design of equipment
meeting level 4 criteria without the need for additional board
level protection on the RS-562/232 port.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
Typical Performance Curves V
6
4
2
1 TRANSMITTER AT 250kbps
1 TRANSMITTER AT 30kbps
0
-2
-4
TRANSMITTER OUTPUT VOLTAGE (V)
-6
1000 2000 3000 4000 50000
LOAD CAPACITANCE (pF)
= 3.3V, TA = 25°C
CC
V
+
OUT
V
-
OUT
repeatable results. The “E” device RS-562/232 pins
withstand ±15kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than ±8kV. All “E” family devices survive ±8kV contact
discharges on the RS-562/232 pins.
25
20
15
-SLEW
SLEW RATE (V/µs)
10
5
0 1000 2000 3000 4000 5000
+SLEW
LOAD CAPACITANCE (pF)
FIGURE 10. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
45
40
35
30
25
20
15
SUPPLY CURRENT (mA)
10
5
0
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
FIGURE 12. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
250kbps
120kbps
20kbps
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
FIGURE 11. SLEW RATE vs LOAD CAPACITANCE
3.5
3.0
2.5
2.0
1.5
1.0
SUPPLY CURRENT (mA)
0.5
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
FIGURE 13. SUPPLY CURRENT vs SUPPLY VOLTAGE
NO LOAD
ALL OUTPUTS STATIC
PROCESS:
Si Gate CMOS
TRANSISTOR COUNT:
338
8
Small Outline Plastic Packages (SOIC)
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ISL8563E
N
INDEX
AREA
123
-AD
e
B
0.25(0.010) C AM BS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
E
-B-
SEATING PLANE
A
-C-
M
0.25(0.010) BM M
H
α
µ
A1
0.10(0.004)
L
h x 45
o
C
M18.3 (JEDEC MS-013-AB ISSUE C)
18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 D 0.4469 0.4625 11.35 11.75 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N18 187
o
α
0
o
8
o
0
o
8
Rev. 0 12/93
NOTESMIN MAX MIN MAX
-
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
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