Datasheet ISL84782 Datasheet (intersil)

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ISL84782

Data Sheet

Ultra Low ON-Resistance, Low-Voltage,
Single Supply, Differential 4 to 1 Analog
Multiplexer

The Intersil ISL84782 device contains precision, bidirectional,
analog switches configured as a differential 4-channel
multiplexer/demultiplexer. It is designed to operate from a
single +1.6V to +3.6V supply. The device has an inhibit pin to
simultaneously open all signal paths.

ON resistance is 0.5Ω with a +3V supply and 0.62Ω with a
single +1.8V supply. Each switch can handle rail to rail
analog signals. The off-leakage current is only 4nA max at
+25°C and 30nA max at +85°C

with a +3.3V supply.

All digital inputs are 1.8V logic-compatible when using a
single +3V supply.

The ISL84782 is a differential 4 to 1 multiplexer device that is
offered in a 16 Ld TSSOP package and a 16 Ld thin QFN
package.

Table 1 summarizes the performance of this family.

TABLE 1. FEATURES AT A GLANCE

ISL84782

Configuration Diff 4:1 Mux

3V R

ON

3V t

ON/tOFF

1.8V R

ON

1.8V t

ON/tOFF

Packages 16 Ld TSSOP, 16 Ld 3x3 Thin QFN

0.5Ω

16ns/13ns

0.62Ω

24ns/16ns

Related Literature

• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”

• Application Note AN557 “Recommended Test Procedures
for Analog Switches”

November 17, 2004

FN6097.3

Features

• Pin Compatible Replacement for the MAX4782 and
MAX4618

• ON Resistance (R

ON

)

- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5Ω

- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.62Ω

•RON Matching Between Channels. . . . . . . . . . . . . . . . 0.12Ω

Flatness Across Signal Range . . . . . . . . . . . . . .0.056Ω

•R

ON

• Single Supply Operation. . . . . . . . . . . . . . . . . +1.6V to +3.6V

• Low Power Consumption (PD). . . . . . . . . . . . . . . . . . <0.2µW

• Fast Switching Action (V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ns

-t

ON

-t

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns

OFF

= +3V)

S

• Guaranteed Break-Before-Make

• High Current Handling Capacity (300mA Continuous)

• Available in 16 Ld 3x3 Thin QFN and 16 Ld TSSOP

• 1.8V CMOS-Logic Compatible (+3V Supply)

• Pb-Free Available (RoHS Compliant) (see Ordering Info)

• ISL84782IR Replaces the ISL43L740IR.

Applications

• Battery Powered, Handheld, and Portable Equipment

- Cellular/Mobile Phones

- Pagers

- Laptops, Notebooks, Palmtops

• Portable Test and Measurement

• Medical Equipment

• Audio and Video Switching

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2004. All Rights Reserved

Pinouts (Note 1)

ISL84782IV (TSSOP)

TOP VIEW

1

A0

2

A2

COMA

3

A3

4

A1

5

INH

6

N.C.

GND

NOTE:

1. Switches Shown for Logic “0” Inputs.

LOGIC

7

8

ISL84782

ISL84782IR (3x3 THIN QFN)

V+

16

B2

15

B1

14

COMB

13

B0

12

B3

11

ADD1

10

ADD0

9

COMA

A3

A1

INH

1

2

3

4

TOP VIEW

A2

A0

V+

1516 14 13

6578

N.C.

GND

ADD0

B2

ADD1

12

B1

11

COMB

10

B0

9

B3

Truth Table

ISL84782

INH ADD0 ADD1 SWITCH ON

1 X X None

00 0 A0, B0

00 1 A1, B1

01 0 A2, B2

01 1 A3, B3

NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V, with a 3V supply.
X = Don’t Care.

Pin Descriptions

PIN FUNCTION

V+ System Power Supply Input (1.6V to 3.6V)

N.C. No Connect. Not internally connected.

GND Ground Connection

INH Digital Control Input. Connect to GND for Normal

Operation. Connect to V+ to turn all switches off.

COMA Analog Switch Channel A Output

COMB Analog Switch Channel B Output

A0-A3 Analog Switch Channel A Input

B0-B3 Analog Switch Channel B Input

ADDx Address Input Pin

Ordering Information

TEMP.

PAR T N O .

RANGE (°C) PACKAGE

ISL84782IV -40 to 85 16 Ld TSSOP M16.173

ISL84782IV-T -40 to 85 16 Ld TSSOP

Tape & Reel

ISL84782IR -40 to 85 16 Ld 3x3 Thin QFN L16.3x3A

ISL84782IR-T -40 to 85 16 Ld 3x3 Thin QFN

Tape & Reel

ISL84782IVZ
(See Note)

ISL84782IVZ-T
(See Note)

-40 to 85 16 Ld TSSOP
(Pb-free)

-40 to 85 16 Ld TSSOP
Tape and Reel
(Pb-free)

ISL84782IRZ
(See Note)

ISL84782IRZ-T
(See Note)

-40 to 85 16 Ld 3x3 Thin QFN
(Pb-free)

-40 to 85 16 Ld 3x3 Thin QFN
Tape and Reel
(Pb-free)

NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020C.

PK G. DW G.

#

M16.173

L16.3x3A

M16.173

M16.173

L16.3x3A

L16.3x3A

2

FN6097.3

November 17, 2004

ISL84782

Absolute Maximum Ratings Thermal Information

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V

Input Voltages

INH, Ax, Bx, ADDx (Note 2) . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V

Output Voltages

COMx (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V

Continuous Current NO or COM . . . . . . . . . . . . . . . . . . . . . ±300mA

Peak Current NO or COM

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA

ESD Rating

HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

2. Signals on Ax, Bx , COMx, ADDx, or INH exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current
ratings.

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3. θ

JA

Thermal Resistance (Typical, Note 3) θ

(°C/W)

JA

16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150

16 Ld 3x3 QFN Thin Package . . . . . . . . . . . . . . . . . 75

Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C

(Lead Tips Only)

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C

Electrical Specifications - 3V Supply Test Conditions: V

Unless Otherwise Specified

PARAMETER TEST CONDITIONS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ON Resistance, R

R

Matching Between Channels,

ON

∆R

ON

Flatness, R

R

ON

Ax or Bx OFF Leakage Current,
I

or I

Ax(OFF)

Bx(OFF)

COM ON Leakage Current, I

DIGITAL INPUT CHARACTERISTICS

Input Voltage High, V

Input Voltage Low, V

Input Current, I

INH

DYNAMIC CHARACTERISTICS

Inhibit Turn-ON Time, t

Inhibit Turn-OFF Time, t

Address Transition Time, t

Break-Before-Make Time, t

ON

FLAT(ON)

INH

INL

, I

, I

INL

ON

ANALOG

COM(ON)

, V

ADDH

, V

ADDL

ADDH

OFF

TRANS

BBM

, I

V+ = 2.7V, I
(See Figure 5)

V+ = 2.7V, I
R

, (Note 6)

ON

V+ = 2.7V, I
(Note 7)

V+ = 3.3V, V

V+ = 3.3V, V

V+ = 3.6V, V

ADDL

V+ = 2.7V, V
(See Figure 1, Note 10)

V+ = 2.7V, V
(See Figure 1, Note 10)

V+ = 2.7V, V
(See Figure 1, Note 10)

V+ = 3.3V, V
(See Figure 3, Note 10)

= 100mA, V

COM

= 100mA, V

COM

= 100mA, V

COM

= 0.3V, 3V, V

COM

= V

COM

= V

INH

Ax or VBx

Ax or VBx

AX or VBX

AX or VBX

AX or VBX

= 0V or V+ (Note 10) Full -0.5 - 0.5 µA

ADD

= 1.5V, RL = 50Ω, CL = 35pF,

= 1.5V, RL = 50Ω, CL = 35pF,

= 1.5V, RL = 50Ω, CL = 35pF,

= 1.5V, RL = 50Ω, CL = 35pF,

= +2.7V to +3.3V, GND = 0V, V

SUPPLY

TEMP

(°C)

= 1.4V, V

INH

(NOTE 5)

MIN TYP

= 0.5V (Notes 4, 8),

INL

(NOTE 5)

MAX UNITS

Full 0 - V+ V

AX or VBX

= 0V to V+,

25 - 0.5 0.75 Ω

Full - - 0.8 Ω

AX or VBX

= Voltage at max

25 - 0.12 0.2 Ω

Full - - 0.2 Ω

AX or VBX

= 0V to V+,

25 - 0.056 0.15 Ω

Full - - 0.15 Ω

AX or VBX

= 3V, 0.3V 25 -4 - 4 nA

Full -30 - 30 nA

= 0.3V, 3V 25 -8 - 8 nA

Full -60 - 60 nA

Full 1.4 - - V

Full - - 0.5 V

25 - 16 25 ns

Full - - 27 ns

25 - 14 23 ns

Full - - 25 ns

25 - 19 28 ns

Full - - 30 ns

25 - 4 - ns

Full 1 - - ns

3

FN6097.3

November 17, 2004

ISL84782

Electrical Specifications - 3V Supply Test Conditions: V

= +2.7V to +3.3V, GND = 0V, V

SUPPLY

= 1.4V, V

INH

= 0.5V (Notes 4, 8),

INL

Unless Otherwise Specified (Continued)

TEMP

PARAMETER TEST CONDITIONS

(°C)

(NOTE 5)

MIN TYP

(NOTE 5)

MAX UNITS

Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - -65 - pC

Input OFF Capacitance, C

COM OFF Capacitance, C

COM ON Capacitance, C

OFF

OFF

COM(ON)

f = 1MHz, V

f = 1MHz, V

f = 1MHz, V

AX or VBX

AX or VBX

AX or VBX

OFF Isolation RL = 50Ω, CL = 35pF, f = 100kHz,

Crosstalk, (Note 9) 25 - -100 - dB

(See Figures 4 and 6)

Total Harmonic Distortion (THD) f = 20Hz to 20kHz, 0.5Vp-p, R

= V

= V

= V

= 0V, (See Figure 7) 25 - 62 - pF

COM

= 0V, (See Figure 7) 25 - 218 - pF

COM

= 0V, (See Figure 7) 25 - 232 - pF

COM

25 - 65 - dB

= 32Ω 25 - 0.02 - %

L

POWER SUPPLY CHARACTERISTICS

Power Supply Range Full 1.6 - 3.6 V

Positive Supply Current, I+ V+ = 3.6V, V

INH

, V

= 0V or V+, Switch On or Off 25 - - 0.05 µA

ADD

Full - - 0.9 µA

NOTES:

= Input voltage to perform proper function.

4. V

IN

5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron

6. R

ON

value.

7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.

8. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.

9. Between any two switches.

10. Guaranteed but not tested.

Electrical Specifications: 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, V

Unless Otherwise Specified

PARAMETER TEST CONDITIONS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ON Resistance, R

R

Matching Between Channels,

ON

∆R

ON)

R

Flatness, R

ON

DIGITAL INPUT CHARACTERISTICS

Input Voltage High, V

Input Voltage Low, V

Input Current, I
I

ADDL

INH

DYNAMIC CHARACTERISTICS

Inhibit Turn-ON Time, t

ON

FLAT(ON)

INH

INL

, I

, I

INL

ON

ANALOG

, V

ADDH

, V

ADDL

ADDH

V+ = 1.8V, I
(See Figure 5)

V+ = 1.8V, I
(See Figure 5)

V+ = 1.8V, I
(See Figure 5)

,

V+ = 1.8V, V

V+ = 1.8V, V
(See Figure 1, Note 10)

= 10.0mA, V

COM

= 10.0mA, V

COM

= 10.0mA, V

COM

, V

INH

Ax or VBx

AX or VBX

AX or VBX

AX or VBX

= 0V or V+ (Note 10) Full -0.5 - 0.5 µA

ADD

= 1.0V,

= 1.0V,

= 0V, 0.9V, 1.6V,

= 1.0V, RL = 50Ω, CL = 35pF,

INH

TEMP

= 1V, V

(°C)

= 0.4V (Notes 4, 8),

INL

MIN

(NOTE 5) TYP

MAX

(NOTE 5) UNITS

Full 0 - V+ V

25 - 0.63 0.85 Ω

Full - - 0.9 Ω

25 - 0.12 - Ω

Full - 0.12 - Ω

25 - 0.14 - Ω

Full - 0.14 - Ω

Full 1 - - V

Full - - 0.4 V

25 - 24 33 ns

Full - - 35 ns

4

FN6097.3

November 17, 2004

ISL84782

Electrical Specifications: 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, V

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS

Inhibit Turn-OFF Time, t

OFF

Address Transition Time, t

TRANS

V+ = 1.8V, V
(See Figure 1, Note 10)

V+ = 1.8V, V

Ax or VBx

AX or VBX

= 1.0V, RL = 50Ω, CL = 35pF,

= 1.0V, RL = 50Ω, CL = 35pF,

(See Figure 1, Note 10)

Break-Before-Make Time, t

BBM

Charge Injection, Q C

V+ = 1.8V, V
(See Figure 3, Note 10)

= 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - -39 - pC

L

AX or VBX

= 1.0V, RL = 50Ω, CL = 35pF,

Test Circuits and Waveforms

tr < 5ns
t

< 5ns

f

90%

V+

LOGIC

INPUT

C

LOGIC
INPUT

VA0, VB0

SWITCH

OUTPUT

0V

V+

0V

t

OFF

50%

90%

t

ON

V

OUT

INH

TEMP

= 1V, V

(°C)

= 0.4V (Notes 4, 8),

INL

MIN

(NOTE 5) TYP

MAX

(NOTE 5) UNITS

25 - 16 25 ns

Full - - 27 ns

25 - 25 34 ns

Full - - 36 ns

25 - 9 - ns

V+

C

A0, B0

A1,A2,B1,
B2,A3,B3

INH

GND

COMA
COMB

ADD0-1

V

OUT

RL

50Ω

C

L

35pF

Logic input waveform is inverted for switches that have the opposite
logic sense.

FIGURE 1A. INHIBIT t

V+

LOGIC

INPUT

SWITCH

OUTPUT

0V

VA0, VB0

VA3, VB3

ON/tOFF

MEASUREMENT POINTS

50%

t

TRANS

V

OUT

10%

0V

t

TRANS

tr < 5ns
t

< 5ns

f

90%

Logic input waveform is inverted for switches that have the opposite
logic sense.

Repeat test for other switches. CL includes fixture and stray
capacitance.

V

OUT

V

=

(NO or NC)

FIGURE 1B. INHIBIT t

V+

A0, B0

A1,A2,B1,
B2,A3,B3

ADD0-1

C

GND

V+

LOGIC

INPUT

C

Repeat test for other switches. C
capacitance.

V

OUT

V

=

(NO or NC)

ON/tOFF

includes fixture and stray

L

R

------------------------------

RLR

+

TEST CIRCUIT

COMA,
COMB

INH

R

------------------------------

RLR

+

L

ON()

L

ON()

V

RL

50Ω

OUT

C

L

35pF

FIGURE 1C. ADDRESS t

MEASUREMENT POINTS

TRANS

5

FIGURE 1. SWITCHING TIMES

FIGURE 1D. ADDRESS t

TEST CIRCUIT

TRANS

FN6097.3

November 17, 2004

Test Circuits and Waveforms (Continued)

ISL84782

V+

C

LOGIC

INPUT

SWITCH

OUTPUT

LOGIC

INPUT

SWITCH

OUTPUT

V

OUT

V+

0V

V

G

R

G

0Ω

CHANNEL
SELECT

Ax, Bx

ADD1
ADD0

GND

COMA,

COMB

INH

V

OUT

OFF

Q = ∆V

OUT

x C

∆V

OFF

OUT

ON

L

Repeat test for other switches.

FIGURE 2A. Q MEASUREMENT POINTS FIGURE 2B. Q TEST CIRCUIT

FIGURE 2. CHARGE INJECTION

V+

V+

0V

0V

t

BBM

tr < 5ns

< 5ns

t

f

90%

C

V+

LOGIC

INPUT

Repeat test for other switches. C

A0-A3
B0-B3

ADD0-1

C

COMA
COMB

INH

GND

includes fixture and stray

L

capacitance.

FIGURE 3A. t

MEASUREMENT POINTS

BBM

FIGURE 3B. t

TEST CIRCUIT

BBM

FIGURE 3. BREAK-BEFORE-MAKE TIME

LOGIC

INPUT

V

OUT

R

50Ω

V

OUT

C

L

1000pF

C

L

L

35pF

V+

10nF

SIGNAL
GENERATOR

Ax or Bx

0V or V+

ADD1

ADD0

ANALYZER

R

L

Off-Isolation is measured between COM and “Off” NO terminal on
each switch.

Signal direction through switch is reversed and worst case values
are recorded.

COMx

GND

INH

CHANNEL
SELECT

FIGURE 4. OFF ISOLATION TEST CIRCUIT FIGURE 5. R

6

RON = V1/100mA

V

X

100mA

V

1

V+

C

Ax or Bx

COMA or
COMB

GND

TEST CIRCUIT

ON

ADD1

ADD0

INH

0V or V+

CHANNEL
SELECT

FN6097.3

November 17, 2004

Test Circuits and Waveforms (Continued)

V+

C

ISL84782

V+

C

SIGNAL
GENERATOR

0V or V+

CHANNEL
SELECT

ANALYZER

R

L

Crosstalk is measured between adjacent channels with one channel
ON and the other channel OFF.

Signal direction through switch is reversed and worst case values
are recorded.

FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. CAPACITANCE TEST CIRCUIT

Ax

ADD1
ADD0

COM

COM

A

Bx

B

GND

INH

50Ω

N.C.

Detailed Description

The ISL84782 analog multiplexer offers precise switching
capability from a single 1.6V to 3.6V supply with low on­resistance (0.5Ω) and high speed operation (t
t

= 13ns). The device is especially well suited for

OFF

portable battery powered equipment thanks to the low
operating supply voltage (1.6V), low power consumption
(0.2µW), low leakage currents (60nA max). High frequency
applications also benefit from the wide bandwidth, and the
very high off isolation and crosstalk rejection.

Supply Sequencing and Overvoltage Protection

With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.

Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.

This method is not applicable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low R
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These

switch, so two small signal

ON

ON

= 16ns,

Ax or Bx

0V or V+

GND

ADD1
ADD0

INH

CHANNEL
SELECT

IMPEDANCE

ANALYZER

COMA or COMB

additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch signal range is
reduced and the resistance may increase, especially at low
supply voltages.

OPTIONAL
PROTECTION
RESISTOR
FOR LOGIC
INPUTS

1kΩ

1kΩ

FIGURE 8. OVERVOLTAGE PROTECTION

ADD

INH

V

NOx

X

OPTIONAL PROTECTION
DIODE

V+

GND

OPTIONAL PROTECTION
DIODE

V

COM

Power-Supply Considerations

The ISL84782 construction is typical of most CMOS analog
switches, in that it has two supply pins: V+ and GND. V+ and
GND drive the internal CMOS switches and set its analog
voltage limits. Unlike switches with a 4V maximum supply
voltage, the ISL84782 4.7V maximum supply voltage
provides plenty of room for the 10% tolerance of 3.6V
supplies, as well as room for overshoot and noise spikes.

The minimum recommended supply voltage is 1.6V but the
part will operate with a supply below 1.5V. It is important to
note that the input signal range, switching times, and on-

7

FN6097.3

November 17, 2004

ISL84782

resistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
curves for details.

V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals.

Logic-Level Thresholds

This device is 1.8V CMOS compatible (0.5V and 1.4V) over
a supply range of 2.0V to 3.6V (see Figure 13). At 3.6V the
V

level is about 1.27V. This is still below the 1.8V CMOS

IH

guaranteed high output minimum level of 1.4V, but noise
margin is reduced.

The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.

High-Frequency Performance

In 50Ω systems, signal response is reasonably flat even past
10MHz with a -3dB bandwidth of 70MHz (see Figure 17).
The frequency response is very consistent over a wide V+
range, and for varying analog signal levels.

An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch’s input to its output. Off Isolation is the
resistance to this feed through, while Crosstalk indicates the

amount of feed through from one switch to another.
Figure 18 details the high Off Isolation and Crosstalk
rejection provided by this family. At 100kHz, Off Isolation is
about 65dB in 50Ω systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.

Leakage Considerations

Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND.
One of these diodes conducts if any analog signal exceeds
V+ or GND.

Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog­signal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.

Typical Performance Curves T

0.75

V+ = 1.65V

0.7

0.65

0.6

(Ω)

ON

R

0.55

0.5

0.45

0.4

FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs

V+ = 1.8V

V+ = 2.7V

V+ = 3V

V+ = 3.6V

01234

SWITCH VOLTAGE

V

COM

(V)

= 25°C, Unless Otherwise Specified

A

I

COM

= 100mA

0.65

0.6

0.55

85°C

(Ω)

0.5

ON

R

0.45

0.4

0.35

00.511.522.53

FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE

25°C

-40°C

V

COM

(V)

I

COM

V+ = 3V

= 100mA

8

FN6097.3

November 17, 2004

ISL84782

Typical Performance Curves T

0.75

0.7

0.65

0.6

(Ω)

ON

0.55

R

0.5

0.45

0.4
0 0.5 1 1.5 2

V

COM

(V)

= 25°C, Unless Otherwise Specified (Continued)

A

-10

V+ = 1.8V

I

COM

85°C

-40°C

= 100mA

25°C

-20

-30

-40

-50

-60

Q (pC)

-70

-80

-90

-100

-110

00.511.522.53

V+ = 1.8V

V

COM

V+ = 3V

(V)

FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE

1.6

1.4

60

50

1.2

(V)

INL

1

AND V

0.8

INH

V

0.6

1 1.5 2 2.5 3 3.5 4 4.5

V

INH

V

INL

V+ (V)

40

(ns)

RANS

t

30

20

10

1 1.5 2 2.5 3 3.5 4 4.5

85°C

-40°C

25°C

V+ (V)

FIGURE 13. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE FIGURE 14. ADDRESS TRANS TIME vs SUPPLY VOLTAGE

25

20

(ns)

OFF

t

15

85°C

25°C

-40°C

(ns)

ON

t

60

50

40

30

20

-40°C

85°C

25°C

10

11.522.533.544.5
V+ (V)

10

1.522.533.544.5

1

V+ (V)

FIGURE 15. INHIBIT TURN - ON TIME vs SUPPLY VOLTAGE FIGURE 16. INHIBIT TURN - OFF TIME vs SUPPLY VOLTAGE

9

FN6097.3

November 17, 2004

ISL84782

Typical Performance Curves T

V+ = 3V

0

GAIN

-10

PHASE

NORMALIZED GAIN (dB)

RL = 50Ω
VIN = 0.2V

0.1 1 10 100

P-P

to 2V

P-P

FREQUENCY (MHz)

= 25°C, Unless Otherwise Specified (Continued)

A

FIGURE 17. FREQUENCY RESPONSE FIGURE 18. CROSSTALK AND OFF ISOLATION

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND (QFN Paddle Connection: To Ground or Float)

0

20

40

60

80

100

PHASE (DEGREES)

0

V+ = 3V

-10

-20

-30

-40

-50

-60

CROSSTALK (dB)

-70

-80

-90

-100
1k 100k 1M 100M 500M10k 10M

ISOLATION

FREQUENCY (Hz)

CROSSTALK

10

20

30

40

50

60

70

80

90

100

110

OFF ISOLATION (dB)

TRANSISTOR COUNT:

228

PROCESS:

Submicron CMOS

10

FN6097.3

November 17, 2004

ISL84782

Thin Shrink Small Outline Plastic Packages (TSSOP)

N

INDEX
AREA

123

-A-

0.05(0.002)

D

SEATING PLANE

e

b

0.10(0.004) C AM BS

E1

-B-

A

-C-

M

0.25(0.010) BM M

E

α

A1

0.10(0.004)

GAUGE

PLANE

0.25

0.010

A2

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.

2. Dimensioning and tolerancing per ANSI Y1 4.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact. (Angles in degrees)

M16.173

16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.043 - 1.10 -

A1 0.002 0.006 0.05 0.15 -

L

A2 0.033 0.037 0.85 0.95 -

b 0.0075 0.012 0.19 0.30 9
c 0.0035 0.008 0.09 0.20 -

D 0.193 0.201 4.90 5.10 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

c

E 0.246 0.256 6.25 6.50 ­L 0.020 0.028 0.50 0.70 6
N16 167

o

α

0

o

8

o

0

o

8

NOTESMIN MAX MIN MAX

-

Rev. 1 2/02

11

FN6097.3

November 17, 2004

ISL84782

Thin Quad Flat No-Lead Plastic Package (TQFN)
Thin Micro Lead Frame Plastic Package (TMLFP)

)

A

6

INDEX

AREA

AREA

2X

2X

SEATING PLANE

(DATUM B)

(DATUM A)

INDEX

AREA

FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE

0.15

6

4X

CC

C

C

4X P

4X P

NX L

e

1
2
3

B

AC0.15

0

8

C

L

D

9

D1

N

TOP VIEW

SIDE VIEW

NX b

D2

D2

N

e
(Nd-1)Xe

REF.

BOTTOM VIEW

NX b

5

L1

TERMINAL TIP

2X

D/2

D1/2

A3

5

0.10 BAMC
7

NX k

2

N

1
2

3

E2/2

SECTION "C-C"

L

10

0.15

C

E1/2

E1

A2

A

A1

8

E2

7
8

9
CORNER
OPTION 4X

A1

A

E/2

9

/ /

0.08

9

(Ne-1)Xe

REF.

C

L

E

B

0.10 C

e

0.152XB

C

L1

C

L

10

L16.3x3A

16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

A 0.70 0.75 0.80 -

A1 - - 0.05 -

A2 - - 0.80 9

A3 0.20 REF 9

b 0.18 0.23 0.30 5, 8

D 3.00 BSC -

D1 2.75 BSC 9

D2 1.35 1.50 1.65 7, 8, 10

E 3.00 BSC -

E1 2.75 BSC 9

E2 1.35 1.50 1.65 7, 8, 10

e 0.50 BSC -

k0.20 - - -

L 0.30 0.40 0.50 8

N162

Nd 4 3

Ne 4 3

P- -0.609

θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.

10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2
and D2 MAX dimension.

NOTESMIN NOMINAL MAX

Rev. 0 6/04

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

12

FN6097.3

November 17, 2004