intersil ISL84780 DATA SHEET

®

ISL84780

Data Sheet

Ultra Low ON-Resistance, Low Voltage,
Single Supply, Quad 2:1 Analog
Multiplexer

The Intersil ISL84780 device is a low ON-resistance, low
voltage, bidirectional, Quad SPDT (Dual DPDT) analog
switch designed to operate from a single +1.6V to +3.6V
supply. Targeted applications include battery-powered
equipment that benefit from low on-resistance, and fast
switching speeds (t
input is 1.8V logic-compatible when using a single +3V supply.

Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This family of parts may be used to
“mux-in” additional functionality while reducing ASIC design
risk. The ISL84780 is offered in small form factor packages,
alleviating board space limitations.

The ISL84780 is a committed Quad SPDT that consists of
four normally open (NO) and four normally closed (NC)
switches. This configuration can also be used as a diff dual 2­to-1 multiplexer/demultiplexer or a quad 2-to1
multiplexer/demultiplexer. The ISL84780 is pin compatible
with the MAX4780.

TABLE 1. FEATURES AT A GLANCE

Number of Switches 4

SW Quad SPDT (Dual DPDT)

3.0V R

3.0V t

ON/tOFF

1.8V R

1.8V t

ON/tOFF

Packages 16Ld 3x3 TQFN, 16Ld TSSOP

ON

ON

ON

= 12ns, t

= 8ns). The digital logic

OFF

ISL84780

0.36Ω

12ns/8ns

0.54Ω

19ns/11ns

October 11, 2004 FN6099.0

Features

• Pin Compatible Replacement for the MAX4780

• ON Resistance (R

ON

)

- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.36Ω

- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.54Ω

•R

Matching between Channels. . . . . . . . . . . . . . . . . 0.13Ω

ON

Flatness Across Signal Range . . . . . . . . . . . . . . . 0.05Ω

•R

ON

• Single Supply Operation . . . . . . . . . . . . . . . . .+1.6V to +3.6V

• Low Power Consumption (PD) . . . . . . . . . . . . . . . . . <0.2µW

• Fast Switching Action

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns

-t

ON

-t

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns

OFF

• Guaranteed Break-Before-Make

• 1.8V Logic Compatible (+3V supply)

• Available in 16 lead 3x3 thin QFN and 16 lead TSSOP

• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV

Applications

• Battery Powered, Handheld, and Portable Equipment

- Cellular/Mobile Phones

- Pagers

- Laptops, Notebooks, Palmtops

• Portable Test and Measurement

• Medical Equipment

• Audio and Video Switching

Related Literature

• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”

• Application Note AN557 “Recommended Test Procedures
for Analog Switches”

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2004. All Rights Reserved

ISL84780

Pinouts (Note 1)

ISL84780 (TSSOP)

TOP VIEW

IN1-2

1

NC1

2

NO1

3

COM1

4

5

NC2

6

NO2

COM2

7

GND

8

ISL84780 (3X3 THIN QFN)

TOP VIEW

NC1

IN1-2

1516 14 13

1

NO1

2

COM1

NC2

3

NO2

4

6578

GND

COM2

NOTE:

1. Switches Shown for Logic “0” Input.

V+

COM3

16

15

14

13

12

11

10

9

IN3-4

NO3

V+

IN3-4

NC4

NO4

COM4

NC3

NO3

COM3

12

11

10

9

NC4

NO4

COM4

NC3

Ordering Information

PART NO.

(BRAND)

ISL84780IR
(780I)

ISL84780IR-T
(780I)

ISL84780IV
(84780IV)

ISL84780IV-T
(84780IV)

TEMP.

RANGE (°C) PACKAGE

-40 to 85 16 Ld 3x3 Thin QFN L16.3x3A

-40 to 85 16 Ld 3x3 Thin QFN
Tape and Reel

-40 to 85 16 Ld TSSOP M16.173

-40 to 85 16 Ld TSSOP
Tape and Reel

Truth Table

LOGIC NC SW NO SW

0ONOFF

1OFFON

NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.

Pin Descriptions

PIN FUNCTION

V+ System Power Supply Input (+1.6V to +3.6V)

GND Ground Connection

IN Digital Control Input

COM Analog Switch Common Pin

NO Analog Switch Normally Open Pin

NC Analog Switch Normally Closed Pin

PKG.

DWG. #

L16.3x3A

M16.173

2

FN6099.0

ISL84780

Absolute Maximum Ratings Thermal Information

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V

Input Voltages

NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)

Output Voltages

COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)

Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA

Peak Current NO, NC, or COM

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA

ESD Rating:

HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV

MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V

CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

2. Signals on NC , NO , IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3. θ

JA

Thermal Resistance (Typical, Note 3) θ

(°C/W)

JA

16 Ld 3x3 TQFN Package . . . . . . . . . . . . . . . . . . . . 75

16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C

(Lead Tips Only)

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C

Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V

Unless Otherwise Specified

PARAMETER TEST CONDITIONS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ON Resistance, R

R

Matching Between Channels,

ON

∆R

ON

Flatness, R

R

ON

NO or NC OFF Leakage Current,
I

NO(OFF)

or I

NC(OFF)

COM ON Leakage Current,
I

COM(ON)

ON

FLAT(ON)

ANALOG

V+ = 2.7V, I
(See Figure 5)

V+ = 2.7V, I
max R

V+ = 2.7V, I
(Note 7)

, (Note 9)

ON

COM

COM

COM

V+ = 3.3V, V

V+ = 3.3V, V

COM

or Floating

= 100mA, VNO or VNC = 0V to V+,

= 100mA, VNO or V

= 100mA, VNO or VNC = 0V to V+

= 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 -3 - 3 nA

COM

= 0.3V, 3V, or VNO or VNC = 0.3V, 3V,

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

ON

V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1, Note 8)

Turn-OFF Time, t

OFF

Break-Before-Make Time Delay, t

Charge Injection, Q C

OFF Isolation R

Crosstalk (Channel-to-Channel) R

V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1, Note 8)

V+ = 3.3V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,

D

(See Figure 3, Note 8)

= 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - -97 - pC

L

= 50Ω, CL = 5pF, f = 100kHz, V

L

(See Figure 4)

= 50Ω, CL = 5pF, f = 100kHz, V

L

(See Figure 6)

Total Harmonic Distortion f = 20Hz to 20kHz, V

NO or NC OFF Capacitance, C

COM ON Capacitance, C

COM(ON)

f = 1MHz, VNO or VNC = V

OFF

f = 1MHz, VNO or VNC = V

COM

TEMP

= Voltage at

NC

= 1V

COM

= 1V

COM

= 2V

, RL = 32Ω 25 - 0.002 - %

P-P

= 0V, (See Figure 7) 25 - 62 - pF

COM

= 0V, (See Figure 7) 25 - 125 - pF

COM

RMS

RMS

,

,

(NOTE 5)

(°C)

Full 0 - V+ V

25 - 0.4 0.6 Ω

Full - - 0.7 Ω

25 - 0.13 0.2 Ω

Full - - 0.2 Ω

25 - 0.05 0.15 Ω

Full - - 0.15 Ω

Full -20 - 20 nA

25 -4 - 4 nA

Full -30 - 30 nA

25 - 12 20 ns

Full - - 25 ns

25 - 8 14 ns

Full - - 17 ns

Full 1 3 - ns

25 - 68 - dB

25 - -98 - dB

= 1.4V, V

INH

MIN TYP

= 0.5V (Notes 4, 6),

INL

(NOTE 5)

MAX UNITS

3

FN6099.0

ISL84780

Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V

= 1.4V, V

INH

= 0.5V (Notes 4, 6),

INL

Unless Otherwise Specified (Continued)

TEMP

PARAMETER TEST CONDITIONS

(°C)

(NOTE 5)

MIN TYP

(NOTE 5)

MAX UNITS

POWER SUPPLY CHARACTERISTICS

Power Supply Range Full 1.6 - 3.6 V

Positive Supply Current, I+ V+ = 3.6V, V

= 0V or V+ 25 - - 0.05 µA

IN

Full - - 1.5 µA

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Input Voltage High, V

Input Current, I

INH

, I

INL

INH

INL

V+ = 3.6V, VIN = 0V or V+ (Note 8) Full -0.5 - 0.5 µA

Full - - 0.5 V

Full 1.4 - - V

NOTES:

4. V

= input voltage to perform proper function.

IN

5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.

7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.

8. Guaranteed not tested.

matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron

9. R

ON

value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4.

Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.65V to +2V, GND = 0V, V

= 1.0V, V

INH

= 0.4V (Note 4, 6),

INL

Unless Otherwise Specified

PARAMETER TEST CONDITIONS

TEMP

(°C)

(NOTE 5)

MIN TYP

(NOTE 5)

MAX UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ON Resistance, R

ON

ANALOG

V+ = 1.8V, I
See Figure 5

= 100mA, VNO or VNC = 0V to V+,

COM

Full 0 - V+ V

25 - 0.54 0.9 Ω

Full - - 1 Ω

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

Turn-OFF Time, t

ON

OFF

Break-Before-Make Time Delay, t

V+ = 1.65V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,
See Figure 1, Note 8

V+ = 1.65V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,
See Figure 1, Note 8

V+ = 2.0V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,

D

25 - 19 25 ns

Full - - 30 ns

25 - 11 17 ns

Full - - 22 ns

Full 1 5 - ns

See Figure 3, Note 8

Charge Injection, Q C

OFF Isolation R

= 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - -52 - pC

L

= 50Ω, CL = 5pF, f = 100kHz, V

L

COM

= 1V

RMS

,

25 - 68 - dB

See Figure 4

Crosstalk (Channel-to-Channel) R

NO or NC OFF Capacitance, C

COM ON Capacitance, C

OFF

COM(ON)

= 50Ω, CL = 5pF, f = 100kHz, V

L

See Figure 6

f = 1MHz, VNO or VNC = V

f = 1MHz, VNO or VNC = V

COM

COM

COM

= 1V

RMS

,

25 - -98 - dB

= 0V, See Figure 7 25 - 62 - pF

= 0V, See Figure 7 25 - 125 - pF

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Input Voltage High, V

Input Current, I

INH

, I

INL

INH

INL

V+ = 2.0V, VIN = 0V or V+ (Note 8) Full -0.05 - 0.05 µA

Full - - 0.4 V

Full 1.0 - - V

4

FN6099.0

Test Circuits and Waveforms

V

INH

LOGIC

INPUT

SWITCH

INPUT

SWITCH

OUTPUT

V

INL

V

NO

0V

t

ON

50%

90%

t

OFF

V

OUT

Logic input waveform is inverted for switches that have the opposite
logic sense.

tr < 5ns

< 5ns

t

f

90%

ISL84780

SWITCH

LOGIC

INPUT

INPUT

NO or NC

IN

Repeat test for all switches. C
capacitance.

V

OUT

V

=

(NO or NC)

V+

C

COM

R

R
50Ω

L

ON()

GND

includes fixture and stray

L

------------------------------

RLR

+

V

OUT

C

L

35pF

L

FIGURE 1A. MEASUREMENT POINTS

SWITCH

OUTPUT

V

OUT

LOGIC

INPUT

ON

Q = ∆V

OUT

∆V

x C

OUT

OFF

L

FIGURE 2A. MEASUREMENT POINTS

FIGURE 1. SWITCHING TIMES

V

ON

INH

V

INL

FIGURE 2. CHARGE INJECTION

FIGURE 1B. TEST CIRCUIT

V+

C

R

G

NO or NC

V

G

GND

COM

IN

LOGIC

INPUT

V

OUT

C

L

FIGURE 2B. TEST CIRCUIT

V+

C

LOGIC
INPUT

SWITCH

OUTPUT

V

OUT

V

INH

V

INL

0V

t

D

FIGURE 3A. MEASUREMENT POINTS

5

V

NX

90%

LOGIC

INPUT

includes fixture and stray capacitance.

C

L

FIGURE 3. BREAK-BEFORE-MAKE TIME

NO

COM

NC

IN

GND

FIGURE 3B. TEST CIRCUIT

R

50Ω

V

OUT

C

L

L

35pF

FN6099.0

Test Circuits and Waveforms (Continued)

ISL84780

SIGNAL
GENERATOR

ANALYZER

FIGURE 4. OFF ISOLATION TEST CIRCUIT FIGURE 5. RON TEST CIRCUIT

SIGNAL
GENERATOR

R

L

0V or V+

NO or NC

COM

NO or NC

IN

1

GND

V+

V+

COM

V+

C

RON = V1/1mA

NO or NC

V

NX

IN

C

0V or V+

50Ω

IMPEDANCE

ANALYZER

1mA

V

1

COM

GND

NO or NC

C

V

or V

INL

IN

V+

IN

INH

C

V

or V

INL

INH

ANALYZER

COM

R

L

NC or NO

GND

N.C.

FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. CAPACITANCE TEST CIRCUIT

Detailed Description

The ISL84780 is a bidirectional, quad single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.6V to 3.6V supply with low on­resistance (0.36Ω) and high speed operation (t
t

= 8ns). The device is especially well suited for portable

OFF

battery-powered equipment due to its low operating supply
voltage (1.6V), low power consumption (5.4µW max), low
leakage currents (30nA max), and the tiny TQFN and TSSOP
packages. The ultra low on-resistance and Ron flatness
provide very low insertion loss and distortion to applications
that require signal reproduction.

Supply Sequencing and Overvoltage Protection

With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal

ON

= 12ns,

COM

GND

voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.

Logic inputs can easily be protected by adding a 1kΩ resistor
in series with the input (See Figure 8). The resistor limits the
input current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.

This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low R

switch, so two small signal

ON

diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (See Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch signal range is
reduced and the resistance may increase, especially at low
supply voltages.

6

FN6099.0

OPTIONAL PROTECTION
DIODE

OPTIONAL
PROTECTION
RESISTOR

IN

X

V

NO or NC

FIGURE 8. OVERVOLTAGE PROTECTION

V+

GND

OPTIONAL PROTECTION
DIODE

V

COM

Power-Supply Considerations

The ISL84780 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL84780 4.7V
maximum supply voltage provides plenty of room for the
10% tolerance of 3.6V supplies, as well as room for
overshoot and noise spikes.

The minimum recommended supply voltage is 1.6V but the
part will operate with a supply below 1.5V. It is important to
note that the input signal range, switching times, and on­resistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
curves for details.

V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.

This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.

ISL84780

High-Frequency Performance

In 50Ω systems, the signal response is reasonably flat even
past 30MHz with a -3dB bandwidth of 104MHz (See
Figure 15). The frequency response is very consistent over a
wide V+ range, and for varying analog signal levels.

An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from the switch input to its output. Off Isolation
is the resistance to this feedthrough, while Crosstalk
indicates the amount of feedthrough from one switch to
another. Figure 16 details the high Off Isolation and
Crosstalk rejection provided by this part. At 100kHz, Off
Isolation is about 68dB in 50Ω systems, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease Off Isolation and
Crosstalk rejection due to the voltage divider action of the
switch OFF impedance and the load impedance.

Leakage Considerations

Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One
of these diodes conducts if any analog signal exceeds V+
or GND.

Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog­signal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.

Logic-Level Thresholds

This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.0V to 3.6V (See Figure 17). At 3.6V
the V

level is about 1.27V. This is still below the 1.8V

IH

CMOS guaranteed high output minimum level of 1.4V, but
noise margin is reduced.

The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.

7

FN6099.0

ISL84780

Typical Performance Curves T

0.55

0.5

V+ = 1.8V

0.45

(Ω)

ON

R

0.4

0.35

0.3
01234

V+ = 2.7V

V+ = 3V

V

COM

(V)

= 25°C, Unless Otherwise Specified

A

I

= 100mA

COM

V+ = 3.6V

FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

(Ω)
R

ON

0.6

85°C

0.55

25°C

0.5

-40°C

0.45

0.4

V+ = 1.8V

I

COM

= 100mA

0.4

85°C

0.35

(Ω)

ON

R

0.3

0.25

00.511.522.53

25°C

-40°C

V

COM

(V)

I

COM

V+ = 3V
= 100mA

FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE

100

50

0

Q (pC)

-50

V+ = 1.8V

V+ = 3V

0.35

0.3

0 0.5 1 1.5 2

V

(V)

COM

-100

-150

00.511.522.53

V

(V)

COM

FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE

50

40

30

(ns)

ON

t

20

10

0

11.522.533.544.5

85°C

-40°C

25°C

V+ (V)

20

15

(ns)

10

OFF

t

5

0

1

85°C

-40°C

1.522.533.544.5

25°C

V+ (V)

FIGURE 13. TURN-ON TIME vs SUPPLY VOLTAGE FIGURE 14. TURN-OFF TIME vs SUPPLY VOLTAGE

8

FN6099.0

ISL84780

Typical Performance Curves T

V+ = 3V

0

GAIN

-20

PHASE

NORMALIZED GAIN (dB)

RL = 50Ω
VIN = 0.2V

1 10 100 600

P-P

to 2V

P-P

FREQUENCY (MHz)

= 25°C, Unless Otherwise Specified (Continued)

A

0
20

40
60
80

100

FIGURE 15. FREQUENCY RESPONSE FIGURE 16. CROSSTALK AND OFF ISOLATION

1.5

1.4

1.3

1.2

1.1

(V)

1

INL

0.9

0.8

AND V

0.7

INH

V

0.6

0.5

0.4

0.3

11.522.533.544.5

V

INH

V

INL

V+ (V)

FIGURE 17. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE

PHASE (DEGREES)

-10
V+ = 3V

-20

-30

-40

-50

-60

-70

CROSSTALK (dB)

-80

-90

-100

-110
1k 100k 1M 100M 500M10k 10M

ISOLATION

CROSSTALK

FREQUENCY (Hz)

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND (QFN Paddle Connection: To Ground or Float)

TRANSISTOR COUNT:

228

PROCESS:

Si Gate CMOS

10
20

30

40

50

60

70

80

90

100
110

OFF ISOLATION (dB)

9

FN6099.0

ISL84780

Thin Shrink Small Outline Plastic Packages (TSSOP)

N

INDEX
AREA

123

-A-

0.05(0.002)

D

SEATING PLANE

e

b

0.10(0.004) C AM BS

M

E1

-B-

A

-C-

0.25(0.010) BM M

E

α

A1

0.10(0.004)

GAUGE

PLANE

0.25

0.010

A2

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact. (Angles in degrees)

M16.173

16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.043 - 1.10 -

A1 0.002 0.006 0.05 0.15 -

L

A2 0.033 0.037 0.85 0.95 -

b 0.0075 0.012 0.19 0.30 9
c 0.0035 0.008 0.09 0.20 -

D 0.193 0.201 4.90 5.10 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

c

E 0.246 0.256 6.25 6.50 ­L 0.020 0.028 0.50 0.70 6

N16 167

o

α

0

o

8

o

0

o

8

NOTESMIN MAX MIN MAX

-

Rev. 1 2/02

10

FN6099.0

ISL84780

Thin Quad Flat No-Lead Plastic Package (TQFN)
Thin Micro Lead Frame Plastic Package (TMLFP)

)

A

6

INDEX

AREA

AREA

2X

2X

SEATING PLANE

(DATUM B)

(DATUM A)

INDEX
AREA

FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE

0.15

6

4X

CC

C

C

4X P

4X P

NX L

e

1
2
3

B

AC0.15

0

8

C

L

D

9

D1

N

TOP VIEW

SIDE VIEW

NX b

D2

D2

N

e

(Nd-1)Xe

REF.

BOTTOM VIEW

NX b

5

L1

TERMINAL TIP

2X

D/2

D1/2

A3

5

0.10 BAMC

7

NX k

2

N

1

2
3

E2/2

SECTION "C-C"

L

10

0.15

C

A

E1/2

E1

A2

A

A1

8

E2

7

8

9
CORNER
OPTION 4X

A1

E/2

9

B

/ /

0.10 C

0.08

9

(Ne-1)Xe

REF.

C

L

E

e

0.152XB

C

L1

C

L

10

L16.3x3A

16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

A 0.70 0.75 0.80 -

A1 - - 0.05 -

A2 - - 0.80 9

A3 0.20 REF 9

b 0.18 0.23 0.30 5, 8

D 3.00 BSC -

D1 2.75 BSC 9

D2 1.35 1.50 1.65 7, 8, 10

E 3.00 BSC -

E1 2.75 BSC 9

E2 1.35 1.50 1.65 7, 8, 10

e 0.50 BSC -

k0.20 - - -

L 0.30 0.40 0.50 8

N162

Nd 4 3

Ne 4 3

P- -0.609

θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.

10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2
and D2 MAX dimension.

NOTESMIN NOMINAL MAX

Rev. 0 6/04

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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11

FN6099.0