intersil ISL84521, ISL84522, ISL84523 DATA SHEET

®

ISL84521, ISL84522, ISL84523

Data Sheet July 2003

Low-Voltage, Single and Dual Supply,
Quad SPST, Analog Switches

The Intersil ISL84521, ISL84523, ISL84523 devices are
CMOS, precision, quad analog switches designed to operate
from a single +2V to +12V supply or from a
Targeted applications include battery powered equipment that
benefit from the devices’ low power consumption (<1µW), low
leakage currents (1nA max), and fast switching speeds
(t

ON

= 45ns, t

= 15ns). A12Ω maximum RON flatness

OFF

ensures signal fidelity, while channel-to-channel mismatch is
guaranteed to be less than 4Ω.

The ISL84521, ISL84522, ISL84523 are quad
single-pole/ single-throw (SPST) devices. The ISL84521 has
four normally closed (NC) switches; the ISL84522 has four
normally open (NO) switches; the ISL84523 has two NO and
two NC switches and can be used as a dual SPDT, or a dual
2:1 multiplexer.

Table summarizes the performance of this family. For higher
performance, pin compatible versions and 3mm x 3mm Quad
No-Lead Flatpack (QFN) package see the ISL43140,
ISL43142 data sheet.

TABLE 1. FEATURES AT A GLANCE

ISL84521 ISL84522 ISL84523

Number of Switches 4 4 4

Configuration All NC All NO 2 NC/2 NO

±5V R

ON

±5V t

ON/tOFF

5V R

ON

5V t

ON/tOFF

3V R

ON

3V tON/t

OFF

Packages 16 Ld SOIC (N), 16 Ld TSSOP

65Ω 65Ω 65Ω

45ns/15ns 45ns/15ns 45ns/15ns

125Ω 125Ω 125Ω

60ns/20ns 60ns/20ns 60ns/20ns

260Ω 260Ω 260Ω

120ns/40ns 120ns/40ns 120ns/40ns

±2V to ±6V supply.

FN6031.2

Features

• Drop-in Replacements for MAX4521 - MAX4523

• Four Separately Controlled SPST Switches

• Pin Compatible with DG411, DG412, DG413

• ON Resistance (R

•R

Matching Between Channels. . . . . . . . . . . . . . . . . . <1Ω

ON

• Low Power Consumption (P

• Low Leakage Current (Max at 85

Max.) . . . . . . . . . . . . . . . . . . . 100Ω

ON

). . . . . . . . . . . . . . . . . . . .<1µW

D

o

C) . . . . . . . . . . . . 10nA

• Fast Switching Action

-t

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45ns

ON

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns

-t

OFF

• Break before Make Timing

• Minimum 2000V ESD Protection per Method 3015.7

• TTL, CMOS Compatible

Applications

• Battery Powered, Handheld, and Portable Equipment

- Cellular/Mobile Phones

- Pagers

- Laptops, Notebooks, Palmtops

• Communications Systems

- Military Radios

- RF “Tee” Switches

• Test Equipment

- Ultrasound

- Electrocardiograph

• Heads-Up Displays

• Audio and Video Switching

• General Purpose Circuits

- +3V/+5V DACs and ADCs

- Digital Filters

- Operational Amplifier Gain Switching Networks

- High Frequency Analog Switching

- High Speed Multiplexing

Related Literature

• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”

• Application Note AN557 “Recommended Test Procedures
for Analog Switches”

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2003. All Rights Reserved

Pinouts (Note 1)

IN1

COM1

NC1

GND

NC4

COM4

IN4

ISL84521 (SOIC, TSSOP)

TOP VIEW

1
2
3

V-

4
5
6
7
8

16
15
14
13
12
11
10

9

ISL84521, ISL84522, ISL84523

IN2
COM2
NC2
V+
N.C.
NC3
COM3
IN3

ISL84523 (SOIC, TSSOP)

TOP VIEW

IN2

IN1

COM1

NO1

GND

NO4

COM4

IN4

1
2
3

V-

4
5
6
7
8

16

COM2

15

NC2

14

V+

13

N.C.

12

NC3

11

COM3

10

IN3

9

ISL84522 (SOIC, TSSOP)

TOP VIEW

1

IN1

2

COM1

NO1

3

V-

4

GND

5

NO4

6

COM4

7

IN4

8

IN2

16

COM2

15

NO2

14

V+

13

N.C.

12

NO3

11

COM3

10

IN3

9

NOTE:

1. Switches Shown for Logic “0” Input.

Truth Table

ISL84521 ISL84522 ISL84523

LOGIC

SW 1, 2, 3, 4 SW 1, 2, 3, 4 SW 1, 4 SW 2, 3

0On OffOffOn
1 Off On On Off

NOTE: Logic “0” ≤ 0.8V. Logic “1” ≥ 2.4V.

Pin Descriptions

PIN FUNCTION

V+ Positive Power Supply Input

V- Negative Power Supply Input. Connect to GND for

Single Supply Configurations.

GND Ground Connection

IN Digital Control Input

COM Analog Switch Common Pin

NO Analog Switch Normally Open Pin

NC Analog Switch Normally Closed Pin

N.C. No Internal Connection

Ordering Information

PART NO.

(NOTE 2)
ISL84521IB -40 to 85 16 Ld SOIC (N) M16.15
ISL84521IV -40 to 85 16 Ld TSSOP M16.173
ISL84522IB -40 to 85 16 Ld SOIC (N) M16.15
ISL84522IV -40 to 85 16 Ld TSSOP M16.173
ISL84523IB -40 to 85 16 Ld SOIC (N) M16.15
ISL84523IV -40 to 85 16 Ld TSSOP M16.173

NOTE:

2. Most surface mount devices are available on tape and reel; add
“-T” to suffix.

TEMP.

RANGE (

o

C) PACKAGE PKG. DWG. #

2

ISL84521, ISL84522, ISL84523

Absolute Maximum Ratings Thermal Information

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V

V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V

All Other Pins (Note 3). . . . . . . . . . . . . ((V-) - 0.3V) to ((V+) + 0.3V)

Continuous Current (Any Terminal). . . . . . . . . . . . . . . . . . . . . 10mA

Peak Current, IN, NO, NC, or COM

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 20mA

ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . > 2kV

Thermal Resistance (Typical, Note 4) θ

16 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . 115

16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Junction Temperature (Plastic Package) . . . . . . . 150

Moisture Sensitivity (See Technical Brief TB363)

All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1

Maximum Storage Temperature Range. . . . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300

(Lead Tips Only)

Operating Conditions

Temperature Range

ISL8452XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. Signals on NC, NO, COM, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings.
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

4. θ

JA

o

C to 85oC

(oC/W)

JA

o

C to 150oC

o

o

C

C

Electrical Specifications +5V Supply Test Conditions: V

Unless Otherwise Specified

PARAMETER TEST CONDITIONS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V
ON Resistance, R

R

Matching Between Channels,

ON

∆R

ON

R

Flatness, R

ON

NO or NC OFF Leakage Current,
I

NO(OFF)

or I

NC(OFF)

COM OFF Leakage Current,
I

COM(OFF)

COM ON Leakage Current,
I

COM(ON)

DIGITAL INPUT CHARACTERISTICS

Input Voltage High, V
Input Voltage Low, V
Input Current, I

INH

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

Turn-OFF Time, t

Break-Before-Make Time Delay
(ISL84523), t

D

Charge Injection, Q C
NO or NC OFF Capacitance, C
COM OFF Capacitance,

C

COM(OFF)

COM ON Capacitance, C

ON

FLAT(ON)

INH

INL

, I

INL

ON

OFF

ANALOG

COM(ON)

VS = ±5V, I

VS = ±5V, I

VS = ±5V, I

VS = ±5.5V, V
(Note 7)

VS = ±5.5V, V
(Note 7)

VS = ±5.5V, V

= 1.0mA, VNO or VNC = ±3V (Figure 5) 25 - 65 100 Ω

COM

= 1.0mA, VNO or VNC = ±3V 25 - 1 4 Ω

COM

= 1.0mA, VNO or VNC = ±3V (Note 8) 25 - 7 12 Ω

COM

= ±4.5V, VNO or VNC = +4.5V

COM

= ±4.5V, VNO or VNC = +4.5V

COM

= VNO or VNC = ±4.5V (Note 7) 25 -2 0.01 2 nA

COM

VS = ±5.5V, VIN = 0V or V+ Full -1 0.03 1 µA

VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,
V

= 0 to 3V (Figure 1)

IN

VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,
V

= 0 to 3V (Figure 1)

IN

VS = ±5.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,
V

= 0 to 3V (Figure 3)

IN

= 1.0nF, VG = 0V, RG = 0Ω (Figure 2) 25 - 1 5 pC

L

f = 1MHz, VNO or VNC = V

OFF

f = 1MHz, VNO or VNC = V

f = 1MHz, VNO or VNC = V

= 0V (Figure 7) 25 - 2 - pF

COM

= 0V (Figure 7) 25 - 2 - pF

COM

= 0V (Figure 7) 25 - 5 - pF

COM

= ±4.5V to ±5.5V, GND = 0V, V

SUPPLY

TEMP

o

C)

(

INH

(NOTE 6)

MIN TYP

= 2.4V, V

= 0.8V (Note 5),

INL

(NOTE 6)

MAX UNITS

Full V- - V+ V

Full - - 125 Ω

Full - - 6 Ω

Full - - 15 Ω

25 -1 0.01 1 nA

Full -10 - 10 nA

25 -1 0.01 1 nA

Full -10 - 10 nA

Full -20 - 20 nA

Full - 1.6 2.4 V
Full 0.8 1.6 - V

25 - 45 80 ns

Full - - 100 ns

25 - 15 30 ns

Full - - 40 ns

25 5 20 - ns

3

ISL84521, ISL84522, ISL84523

Electrical Specifications +5V Supply Test Conditions: V

= ±4.5V to ±5.5V, GND = 0V, V

SUPPLY

= 2.4V, V

INH

= 0.8V (Note 5),

INL

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS

TEMP

OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz,

V

or VNC = 1V

Crosstalk, (Note 9) 25 - <-90 - dB

NO

, (See Figures 4 and 6)

RMS

(NOTE 6)

o

C)

(

MIN TYP

25 - >90 - dB

(NOTE 6)

MAX UNITS

POWER SUPPLY CHARACTERISTICS

Power Supply Range Full ±2-±6V
Positive Supply Current, I+ V

= ±5.5V, VIN = 0V or V+, Switch On or Off 25 -1 0.05 1 µA

S

Full -1 - 1 µA

Negative Supply Current, I- 25 -1 0.05 1 µA

Full -1 - 1 µA

NOTES:

5. V

= Input voltage to perform proper function.

IN

6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

o

7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25

8. Flatness is defined as the delta between the maximum and minimum R

values over the specified voltage range.

ON

C.

9. Between any two switches.

Electrical Specifications 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, V

Unless Otherwise Specified

TEMP

PARAMETER TEST CONDITIONS

o

(

C)

(NOTE 6) TYP

MIN

= 2.4V, V

INH

= 0.8V (Note 5),

INL

MAX

(NOTE 6)UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V
ON Resistance, R

R

Matching Between Channels,

ON

∆R

ON

ANALOG

ON

NO or NC OFF Leakage Current,
I

NO(OFF)

or I

NC(OFF)

COM OFF Leakage Current,
I

COM(OFF)

COM ON Leakage Current,
I

COM(ON)

V+ = 4.5V, I
(Figure 5)

V+ = 5V, I

COM

V+ = 5.5V, V
(Note 7)

V+ = 5.5V, V
(Note 7)

V+ = 5.5V, V

= 1.0mA, VNO or VNC = 3.5V

COM

= 1.0mA, VNO or VNC = 3.5V 25 - 2 8 Ω

= 1V, 4.5V, VNO or VNC = 4.5V, 1V

COM

= 1V, 4.5V, VNO or VNC = 4.5V, 1V

COM

= 1V, 4.5V (Note 7) 25 -2 - 2 nA

COM

Full 0 - V+ V

25 - 125 200 Ω

Full - - 250 Ω

Full - - 10 Ω

25 -1 0.01 1 nA

Full -10 - 10 nA

25 -1 0.01 1 nA

Full -10 - 10 nA

Full -20 - 20 nA

DIGITAL INPUT CHARACTERISTICS

Input Voltage High, V
Input Voltage Low, V
Input Current, I

INH

, I

INH

INL

INL

V+ = 5.5V, VIN = 0V or V+ Full -1 0.03 1 µA

Full - 1.6 2.4 V
Full 0.8 1.6 - V

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

Turn-OFF Time, t

ON

OFF

Break-Before-Make Time Delay
(ISL84523), t

D

Charge Injection, Q C

V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
V

= 0 to 3V (Figure 1)

IN

V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
V

= 0 to 3V (Figure 1)

IN

V+ = 5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
V

= 0 to 3V (Figure 3)

IN

= 1.0nF, VG = 0V, RG = 0Ω (Figure 2) 25 - 1 5 pC

L

25 - 60 100 ns

Full - - 150 ns

25 - 20 50 ns

Full - - 75 ns

25 10 30 - ns

4

ISL84521, ISL84522, ISL84523

Electrical Specifications 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, V

= 2.4V, V

INH

= 0.8V (Note 5),

INL

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS

TEMP

o

C)

(

MIN

(NOTE 6) TYP

MAX

(NOTE 6)UNITS

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V+ = 5.5V, V

= 0V or V+, Switch On or Off 25 -1 0.05 1 µA

IN

Full -1 - 1 µA

Negative Supply Current, I- 25 -1 0.05 1 µA

Full -1 - 1 µA

Electrical Specifications 3V Supply Test Conditions: V+ = +2.7V to +3.6V, V- = GND = 0V, V

= 2.4V, V

INH

= 0.8V (Note 5),

INL

Unless Otherwise Specified

PARAMETER TEST CONDITIONS

TEMP

o

(

C)

MIN

(NOTE 6) TYP

MAX

(NOTE 6)UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V
ON Resistance, R

ON

ANALOG

V+ = 2.7V, I

= 0.1mA, VNO or VNC = 1V 25 - 260 500 Ω

COM

Full 0 - V+ V

Full - - 600 Ω

DIGITAL INPUT CHARACTERISTICS

Input Voltage High, V
Input Voltage Low, V
Input Current, I

INH

, I

INH

INL

INL

V+ = 3.6V, VIN = 0V or V+ Full -1 0.03 1 µA

Full - 1.6 2.4 V
Full 0.8 1.6 - V

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

Turn-OFF Time, t

ON

OFF

Break-Before-Make Time Delay
(ISL84523), t

D

Charge Injection, Q C

V+ = 2.7V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF,
V

= 0 to V+ (Figure 1)

IN

V+ = 2.7V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF,
V

= 0 to V+ (Figure 1)

IN

V+ = 3.6V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF,
V

= 0 to 3V (Figure 3)

IN

= 1.0nF, VG = 0V, RG = 0Ω (Figure 2) 25 - 0.5 5 pC

L

25 - 120 250 ns

Full - - 300 ns

25 - 40 80 ns

Full - - 100 ns

25 15 50 - ns

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V+ = 3.6V, V

= 0V or V+, Switch On or Off 25 -1 0.05 1 µA

IN

Full -1 - 1 µA

Negative Supply Current, I- 25 -1 0.05 1 µA

Full -1 - 1 µA

Test Circuits and Waveforms

3V

LOGIC

INPUT

SWITCH

INPUT

SWITCH

OUTPUT

0V

V

NX

0V

t

ON

50%

90%

t

OFF

V

OUT

Logic input waveform is inverted for switches that have the opposite
logic sense.

FIGURE 1A. MEASUREMENT POINTS

5

tr < 20ns
t

< 20ns

f

90%

FIGURE 1. SWITCHING TIMES

SWITCH

INPUT

C

LOGIC

INPUT

NO OR NC

IN

GND

V

NX

Repeat test for all switches. C
capacitance.

V

OUT

V

(NO or NC)

FIGURE 1B. TEST CIRCUIT

V+

C

COM

RL

300Ω

C

V-

includes fixture and stray

L

R

L

------------------------------=

RLR

+

ON()

V

OUT

C

L

35pF

ISL84521, ISL84522, ISL84523

Test Circuits and Waveforms (Continued)

V+

C

SWITCH

OUTPUT

V

OUT

LOGIC

INPUT

ON

Q = ∆V

OUT

∆V

x C

OUT

L

OFF

ON

3V

0V

Logic input waveform is inverted for switches that have the opposite
logic sense.

FIGURE 2A. MEASUREMENT POINTS

FIGURE 2. CHARGE INJECTION

OUT1

OUT2

3V

0V

0V

0V

90%

t

90%

90%

D

90%

t

D

LOGIC

INPUT

SWITCH

OUTPUT

V

SWITCH

OUTPUT

V

FIGURE 3A. MEASUREMENT POINTS

FIGURE 3. BREAK-BEFORE-MAKE TIME (ISL84523 ONLY)

R

G

NO OR NC

V

G

C

GND

V-

Repeat test for all switches. C
capacitance.

COM

IN

LOGIC
INPUT

includes fixture and stray

L

FIGURE 2B. TEST CIRCUIT

V+

C

C

V

NX

LOGIC

INPUT

includes fixture and stray capacitance.

C

L

NO1

NC2

IN1

IN2

GND

COM1

COM2

V-

C

R

L2

300Ω

Reconfigure accordingly to test SW3 and SW4.

FIGURE 3B. TEST CIRCUIT

V

OUT2

R

L1

300Ω

C

L2

35pF

C

L

V

V

OUT

OUT1

C

L1

35pF

SIGNAL
GENERATOR

ANALYZER

R

L

Repeat test for all switches.

FIGURE 4. OFF ISOLATION TEST CIRCUIT

NO OR NC

COM

6

GND

V+

V-

IN

C

0V OR 2.4V

C

RON = V1/1mA

V

NX

1mA

V

Repeat test for all switches.

FIGURE 5. R

1

NO OR NC

COM

GND

TEST CIRCUIT

ON

V+

C

0.8V OR 2.4V

IN

C

V-

ISL84521, ISL84522, ISL84523

Test Circuits and Waveforms (Continued)

V+

C

V+

SIGNAL
GENERATOR

ANALYZER

NO1 OR NC1

IN2

0V or 2.4V

COM2

R

L

FIGURE 6. CROSSTALK TEST CIRCUIT

COM1

IN2

NO2 OR NC2

GND

V-

50Ω

0V OR 2.4V

NO

CONNECTION

C

Detailed Description

The ISL84521, ISL84522, ISL84523 quad analog switches
offer precise switching capability from a bipolar
or a single 2V to 12V supply with low on-resistance (65Ω)
and high speed switching (t

ON

= 45ns, t

OFF

devices are especially well suited to portable battery
powered equipment thanks to the low operating supply
voltage (2V), low power consumption (1µW) and low leakage
currents (1nA max). High frequency applications also benefit
from the wide bandwidth, and the very high OFF isolation and
crosstalk rejection.

±2V to ±6V

= 15ns). The

NO OR NC

0V OR 2.4V

IMPEDANCE

ANALYZER

COM

FIGURE 7. CAPACITANCE TEST CIRCUIT

GND

IN

V-

unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.

OPTIONAL PROTECTION
DIODE

OPTIONAL
PROTECTION
RESISTOR

IN

X

V

NO OR NC

V+

V

COM

Supply Sequencing And Overvoltage Protection

As with any CMOS device, proper power supply sequencing
is required to protect the device from excessive input
currents which might permanently damage the IC. All I/O
pins contain ESD protection diodes from the pin to V+ and to
V- (Figure 8). To prevent forward biasing these diodes, V+
and V- must be applied before any input signals, and input
signal voltages must remain between V+ and V-. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.

Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (Figure 8). The resistor limits
the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.

Adding a series resistor to the switch input defeats the
purpose of using a low R
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above V-. The low leakage current performance is

switch, so two small signal

ON

V-

OPTIONAL PROTECTION
DIODE

FIGURE 8. OVERVOLTAGE PROTECTION

Power-Supply Considerations

The ISL8452X construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and
GND. V+ and V- drive the internal CMOS switches and set
their analog voltage limits, so there are no connections
between the analog signal path and GND. Unlike switches
with a 13V maximum supply voltage, the ISL8452X 15V
maximum supply voltage provides plenty of room for the
10% tolerance of 12V supplies (
as well as room for overshoot and noise spikes.

This family of switches performs equally well when operated
with bipolar or single voltage supplies, and bipolar supplies
need not be symmetrical. The minimum recommended
supply voltage is 2V or

±2V. It is important to note that the

input signal range, switching times, and ON-resistance
degrade at lower supply voltages. Refer to the electrical
specification tables and Typical Performance Curves for
details.

±6V or 12V single supply),

7

ISL84521, ISL84522, ISL84523

V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals, so switch parameters ­especially R

- are strong functions of both supplies.

ON

Logic-Level Thresholds

V+ and GND power the internal logic stages, so V- has no
affect on logic thresholds. This switch family is TTL
compatible (0.8V and 2.4V) over a V+ supply range of 2.5V
to 10V. At 12V the V
use a logic family the provides a V

level is about 2.7V, so for best results

IH

greater than 3V.

OH

The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.

High-Frequency Performance

In 50Ω systems, signal response is reasonably flat even past
300MHz (Figure 15), with a small signal -3dB bandwidth in
excess of 400MHz, and a large signal bandwidth exceeding
300MHz.

An off switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. OFF Isolation
is the resistance to this feedthrough, while Crosstalk
indicates the amount of feedthrough from one switch to

another. Figure 16 details the high OFF Isolation and
Crosstalk rejection provided by this family. At 10MHz, OFF
isolation is about 50dB in 50Ω systems, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease OFF Isolation and
Crosstalk rejection due to the voltage divider action of the
switch OFF impedance and the load impedance.

Leakage Considerations

Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One
of these diodes conducts if any analog signal exceeds V+
or V-.

Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or V- and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and V- pins constitutes the analog-signal­path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and GND.

Typical Performance Curves T

90
80
70
60
50

40

250

(Ω)

ON

200

R

150

100

85oC

-40oC

50

0

4 6 8 10 12

357911

V- = -5V

V- = 0V

25oC

V+ (V)

= 25oC, Unless Otherwise Specified

A

V

COM

I

COM

85oC

25oC

-40oC

FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE

= (V+) - 1V

= 1mA

300
250
200
150
100

50

225

(Ω)

175

ON

R

125

75

140

85oC

110

25oC

80
50

024

135

V

V+ = 5V

(V)

COM

85oC
25oC

-40oC

V- = 0V

85oC
25oC

-40oC

I

COM

V+ = 2.7V

V- = 0V

V+ = 3.3V

-40oC

= 1mA

V- = 0V

FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE

8

ISL84521, ISL84522, ISL84523

Typical Performance Curves T

180

I

= 1mA

COM

140

100

60

120
100

(Ω)

80

ON

R

60
40

90

85oC

70

25oC

50
30

-5 -3 -1 1 3 5

85oC

85oC

-4-2024
V

COM

(V)

= 25oC, Unless Otherwise Specified (Continued)

A

25oC

-40oC

VS = ±5V

FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE

VS = ±2V

VS = ±3V

25oC

-40oC

-40oC

5

2.5

V+ = 3.3V

0

V+ = 5V

2.5

Q (pC)

VS = ±5V

-5

-7.5

-5 0 5

-2.5 2.5
V

(V)

COM

FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE

(ns)

ON

t

250
200
150
100

300
250
200
150
100

25oC

-40oC

25oC

50

-40oC

0

85oC

25oC

50

-40oC

0

24681012

357911

V- = -5V

85oC

V- = 0V

V+ (V)

V

COM

= (V+) - 1V

FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE

(ns)
t

125
100

75
50
25

50

OFF

40

30

20

10

25oC

-40oC

25oC

-40oC

0

85oC

25oC

-40oC

24681012

357911

V- = -5V

85oC

V- = 0V

V+ (V)

V

COM

= (V+) - 1V

FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE

9

ISL84521, ISL84522, ISL84523

Typical Performance Curves T

VS = ±5V

3

GAIN

0

-3

NORMALIZED GAIN (dB)

PHASE

VIN = 0.2V

RL = 50Ω

1 10 100 600

FREQUENCY (MHz)

= 25oC, Unless Otherwise Specified (Continued)

A

VIN = 0.2V

VIN = 5V

P-P

VIN = 5V

FIGURE 15. FREQUENCY RESPONSE

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

V-

P-P

P-P

P-P

0

45

90

135

180

PHASE (DEGREES)

-10
V+ = 3V to 12V or

VS = ±2V to ±5V

-20

RL = 50Ω

-30

-40

-50

-60

-70

CROSSTALK (dB)

-80

-90

-100

-110
1k 100k 1M 100M 500M10k 10M

ISOLATION

CROSSTALK

FREQUENCY (Hz)

FIGURE 16. CROSSTALK AND OFF ISOLATION

10

20

30

40

50

60

70

80

90

100
110

OFF ISOLATION (dB)

TRANSISTOR COUNT:

ISL84521: 188
ISL84522: 188
ISL84523: 188

PROCESS:

Si Gate CMOS

10

ISL84521, ISL84522, ISL84523

Small Outline Plastic Packages (SOIC)

N

INDEX
AREA

123

-A­D

e

B

0.25(0.010) C AMB

E

-B-

SEATING PLANE

A

-C-

S

M

0.25(0.010) B

H

α

µ

A1

0.10(0.004)

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In­terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact.

M

L

h x 45

M

o

M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.053 0.069 1.35 1.75 -

A1 0.004 0.010 0.10 0.25 -

B 0.014 0.019 0.35 0.49 9
C 0.007 0.010 0.19 0.25 ­D 0.386 0.394 9.80 10.00 3
E 0.150 0.157 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.228 0.244 5.80 6.20 ­h 0.010 0.020 0.25 0.50 5

C

L 0.016 0.050 0.40 1.27 6

N16 167

o

α

0

o

8

o

0

o

8

Rev. 1 02/02

NOTESMIN MAX MIN MAX

-

11

ISL84521, ISL84522, ISL84523

Thin Shrink Small Outline Plastic Packages (TSSOP)

N

INDEX
AREA

123

-A-

0.05(0.002)

D

SEATING PLANE

e

b

0.10(0.004) C AM BS

M

E1

-B-

A

-C-

0.25(0.010) BM M

E

α

A1

0.10(0.004)

GAUGE

PLANE

0.25

0.010

A2

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact. (Angles in degrees)

M16.173

16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.043 - 1.10 -

A1 0.002 0.006 0.05 0.15 -

L

A2 0.033 0.037 0.85 0.95 -

b 0.0075 0.012 0.19 0.30 9

c 0.0035 0.008 0.09 0.20 -

D 0.193 0.201 4.90 5.10 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

c

E 0.246 0.256 6.25 6.50 ­L 0.020 0.028 0.50 0.70 6
N16 167

o

α

0

o

8

o

0

o

8

NOTESMIN MAX MIN MAX

-

Rev. 1 2/02

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data she ets are current before placin g orders. Information furn ished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or othe rwise under any patent or patent rights of Intersil or its subsidiaries.

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12