intersil ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E DATA SHEET

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ISL83080E, ISL83082E, ISL83083E,

ISL83085E, ISL83086E, ISL83088E

Data Sheet

±15kV ESD Protected, 5V, Full Fail-Safe, Fractional (1/8) Unit Load, RS-485/RS-422 Transceivers

The ISL8308XE are BiCMOS, ESD protected, 5V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Each driv er output, and receiver input, is protected against without latch-up, and unlike competitive products, this Intersil family is specified for 10% tole r ance suppli es (4.5V to 5. 5V).

These devices have very low bus currents (+125µA/-75µA), so they present a true “1/8 unit load” to the RS-485 bus. This allows up to 256 transceivers on the network without violating the RS-485 specification’s 32 unit load maximum, and without using repeaters. For example, in a remote utility meter reading system, individual meter readings are routed to a concentrator via an RS-485 network, so the high allowed node count minimizes the number of repeaters required. Data for all meters is then read out from the concentrator via a single access port, or a wireless link.

Receiver (Rx) inputs f eature a “Ful l Fail-Safe” design, which ensures a logic high Rx output if Rx inputs are floating, shorted, or terminated but undriven.

The ISL83080E, ISL83082E, ISL83083E, ISL83085E utilize slew rate limited drivers which reduce EMI, and minimize reflections from improperly terminated transmission lines, or unterminated stubs in multidrop and multipoint applications. Slew rate limited versions also include receiver input filtering to enhance noise immunity in the presence of slow input signals.

Hot Plug circuitry ensures that the Tx and Rx outputs remain in a high impedance state until the power supply has stabilized, and the Tx outputs are fully short circuit protected.

The ISL83080E, ISL83083E, ISL83086E are configured for full duplex (separate Rx input and Tx output pins) applications. The half duplex versions multiplex the Rx inputs and Tx outputs to allow transceivers with output disable functions in 8 lead packages.

±15kV ESD strikes

September 12, 2005

FN6085.6

Features

• Pb-Free Plus Anneal Available (RoHS Compliant) (See Ordering Info)

• RS-485 I/O Pin ESD Protection . . . . . . . . . .

±15kV HBM

Class 3 ESD Protection (HBM) on all Pins. . . . . . . . >7kV

• Full Fail-safe (Open, Short, Terminated and Floating) Receivers

• Hot Plug Circuitry (ISL83080E, ISL83082E, ISL83083E, ISL83085E)

- Tx and Rx Outputs Remain Three-state During Power-

up/Power-down

• True 1/8 Unit Load Allows up to 256 Devices on the Bus

• Specified for Single 5V, 10% Tolerance, Supplies

• High Data Rates. . . . . . . . . . . . . . . . . . . . . up to 10Mbps

• Low Quiescent Supply Current . . . . . . . . . . . . . . . 530

µA

Ultra Low Shutdown Supply Current . . . . . . . . . . . . 70nA

• -7V to +12V Common Mode Input Voltage Range

• Half and Full Duplex Pinouts

• Three-State Rx and Tx Outputs

• Current Limiting and Thermal Shutdown for driver Overload Protection

Applications

• Automated Utility Meter Reading Systems

• High Node Count Systems

• Factory Automation

• Field Bus Networks

• Security Camera Networks

• Building Environmental Control Systems

• Industrial/Process Control Networks

TABLE 1. SUMMARY OF FEATURES

PART

NUMBER

ISL83080E Full 0.115 Yes Yes 256 Yes 530 Yes 14 ISL83082E Half 0.115 Yes Yes 256 Yes 530 Yes 8 ISL83083E Full 0.5 Yes Yes 256 Yes 530 Yes 14 ISL83085E Half 0.5 Yes Yes 256 Yes 530 Yes 8 ISL83086E Full 10 No No 256 Yes 530 Yes 14 ISL83088E Half 10 No No 256 Yes 530 Yes 8

HALF/FULL

DUPLEX

DATA RATE

(Mbps)

SLEW-RATE

LIMITED? HOT PLUG

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

# DEVICES

ON BUS

Rx/Tx

ENABLE?

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

QUIESCENT

(µA)

LOW POWER SHUTDOWN?

COUNT

Pinouts

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

ISL83082E, ISL83085E, ISL83088E

(MSOP, SOIC)

TOP VIEW

RO RE DE

2 3

B/Z

A/Y

GND

ISL83080E, ISL83083E, ISL83086E

(SOIC)

TOP VIEW

NC RO RE DE

GND GND

1 2

3 4

5 6 7

Y NC

Ordering Information (Note 1)

TEMP.

PART NO. (BRAND)

ISL83080EIB

RANGE (°C) PACKAGE

-40 to 85 14 Ld SOIC M14.15

(83080EIB) ISL83080EIBZ

(83080EIBZ, Note 2) ISL83082EIB

-40 to 85 14 Ld SOIC (Pb-Free)

-40 to 85 8 Ld SOIC M8.15

(83082EIB) ISL83082EIBZ

(83082EIBZ, Note 2)

-40 to 85 8 Ld SOIC (Pb-Free)

ISL83082EIU (3082E) -40 to 85 8 Ld MSOP M8.118 ISL83082EIUZ

(3082Z, Note 2) ISL83083EIB

-40 to 85 8 Ld MSOP (Pb-free)

-40 to 85 14 Ld SOIC M14.15

(83083EIB) ISL83083EIBZ

(83083EIBZ, Note 2) ISL83085EIB

-40 to 85 14 Ld SOIC (Pb-Free)

-40 to 85 8 Ld SOIC M8.15

(83085EIB) ISL83085EIBZ

(83085EIBZ, Note 2)

-40 to 85 8 Ld SOIC (Pb-Free)

ISL83085EIU (3085E) -40 to 85 8 Ld MSOP M8.118 ISL83085EIUZ

(3085Z, Note 2) ISL83086EIB

-40 to 85 8 Ld MSOP (Pb-free)

-40 to 85 14 Ld SOIC M14.15

(83086EIB) ISL83086EIBZ

(83086EIBZ, Note 2) ISL83088EIB

-40 to 85 14 Ld SOIC (Pb-Free)

-40 to 85 8 Ld SOIC M8.15

(83088EIB) ISL83088EIBZ

(83088EIBZ, Note 2)

-40 to 85 8 Ld SOIC (Pb-Free)

ISL83088EIU (3088E) -40 to 85 8 Ld MSOP M8.118

PKG.

DWG. #

M14.15

M8.15

M8.118

M14.15

M8.15

M8.118

M14.15

M8.15

Ordering Information (Note 1) (Continued)

PART NO. (BRAND)

ISL83088EIUZ (3088Z, Note 2)

NOTES:

1. Units also available in Tape and Reel; Add “-T” to suffix.

2. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pbfree soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

RANGE (°C) PACKAGE

-40 to 85 8 Ld MSOP (Pb-free)

TEMP.

PKG.

DWG. #

M8.118

FN6085.6

September 12, 2005

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Truth Tables

TRANSMITTING

INPUTS OUTPUTS

X1101 X1010 0 0 X High-Z High-Z 1 0 X High-Z * High-Z *

NOTE: *Shutdown Mode (See Note 9).

DE DI Z Y

00 X≥ -0.05V 1 00 X≤ -0.2V 0 0 0 X Inputs

1 0 0 X High-Z * 1 1 1 X High-Z

NOTE: *Shutdown Mode (See Note 9).

Half DuplexDEFull Duplex

RECEIVING

INPUTS OUTPUT

A-B RO

Open/Shorted

Pin Descriptions

PIN FUNCTION

RO Receiver output: If A-B ≥ -50mV, RO is high; I f A -B ≤ -200mV, RO is low; RO = High if A and B are unconnected (floating) or shorted.

RE DE Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low.

DI Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low.

Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high.

GND Ground connection.

A/Y ±15kV HBM ESD Protected RS-485/422 level, noninverting receiver input and noninverting driver output. Pin is an input if DE = 0;

B/Z ±15kV HBM ESD Protected RS-485/422 level, Inverting receiver input and inverting driver output. Pin is an input if DE = 0; pin is an

NC No Connection.

pin is an output if DE = 1.

output if DE = 1. A ±15kV HBM ESD Protected RS-485/422 level, noninverting receiver input. B ±15kV HBM ESD Protected RS-485/422 level, inverting receiver input. Y ±15kV HBM ESD Protected RS-485/422 level, noninverting driver output. Z ±15kV HBM ESD Protected RS-485/422 level, inverting driver output.

System power supply input (4.5V to 5.5V).

FN6085.6

September 12, 2005

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Typical Operating Circuit

+5V

1 2

B/Z A/Y

GND

+5V

GND

6, 7

ISL83082E, ISL83085E, ISL83088E

+5V

0.1µF

7 6

0.1µF

B/Z

A/Y

GND

ISL83080E, ISL83083E, ISL83086E

+5V

0.1µF

10 9

0.1µF

GND

6, 7

FN6085.6

September 12, 2005

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Absolute Maximum Ratings Thermal Information

VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V

Input Voltages

DI, DE, RE

. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V)

Input/Output Voltages

A, B, Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9V to +13V

A, B, Y, Z (Transient Pulse Through 100Ω) . . . . . . . . . . . . . ±25V

RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (V

Short Circuit Duration

+0.3V)

Y, Z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3. θ

Thermal Resistance (Typical, Note 3)

(°C/W)

8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 105

8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 140

14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 128

Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C

(Lead Tips Only)

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C

Electrical Specifications Test Conditions: V

(Note 4)

PARAMETER SYMBOL TEST CONDITIONS

DC CHARACTERISTICS

Driver Differential V Driver Differential V

Change in Magnitude of Driver Differential V Complementary Output States

OUT

Driver Common-Mode V Change in Magnitude of Driver

Common-Mode V Complementary Output States

Logic Input High Voltage V Logic Input Low Voltage V DI Input Hysteresis Voltage V Logic Input Current I Input Current (A, B) I

Output Leakage Current (Y, Z) (Full Duplex Versions Only)

Output Leakage Current (Y, Z) in Shutdown Mode (Full Duplex)

Driver Short-Circuit Current, V

= High or Low

Receiver Differential Threshold Voltage

Receiver Input Hysteresis ∆V

(no load) V

OUT

(with load) V

OUT

for

OUT

for

OUT

OD1 OD2

∆V

HYS IN1 IN2

IN3

OSD1

RL = 100Ω (RS-422) (Figure 1A) Full 2 2.9 - V RL = 54Ω (RS-485) (Figure 1A) Full 1.5 2.4 V R RL = 54Ω or 100Ω (Figure 1A) Full - 0.01 0.2 V

RL = 54Ω or 100Ω (Figure 1A) Full - 2.85 3 V RL = 54Ω or 100Ω (Figure 1A) Full - 0.01 0.1 V

DE, DI, RE Full 2 - - V

DE, DI, RE Full - - 0.8 V

DE, DI, RE Full -2 - 2 µA DE = 0V, VCC = 0V or 5.5V VIN = 12V Full - 70 125 µA

RE = 0V, DE = 0V, VCC = 0V or 5.5V

RE = VCC, DE = 0V, VCC = 0V or 5.5V

DE = VCC, -7V ≤ VY or VZ ≤ 12V (Note 6) Full - - ±250 mA

-7V ≤ VCM ≤ 12V Full -200 -90 -50 mV

VCM = 0V 25 - 20 - mV

= 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = 25°C

TEMP

(°C) MIN TYP MAX UNITS

Full - - V

= 60Ω, -7V ≤ VCM ≤ 12V (Figure 1B) Full 1.5 2.6 - V

25 - 100 - mV

= -7V Full -75 55 - µA

VIN = 12V Full - 7 125 µA V

= -7V Full -75 11 - µA

VIN = 12V Full - 0 20 µA

= -7V Full -20 9 - µA

FN6085.6

September 12, 2005

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Electrical Specifications Test Conditions: V

= 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = 25°C

(Note 4) (Continued)

TEMP

PARAMETER SYMBOL TEST CONDITIONS

Receiver Output High Voltage V Receiver Output Low Voltage V Three-State (high impedance)

OZR

IO = -4mA, VID = -50mV Full VCC - 1 4.6 - V

IO = -4mA, VID = -200mV Full - 0.2 0.4 V

0.4V ≤ VO ≤ 2.4V Full -1 0.03 1 µA

(°C) MIN TYP MAX UNITS

Receiver Output Current Receiver Input Resistance R Receiver Short-Circuit Current I

OSR

-7V ≤ VCM ≤ 12V Full 96 160 - kΩ

0V ≤ VO ≤ V

Full ±7-±85 mA

SUPPLY CURRENT

No-Load Supply Current (Note 5) I

Shutdown Supply Current I

SHDN

Half Duplex Versions, DE = VCC, RE = X, DI = 0V or V

All Versions, DE = 0V, RE Versions, DE = V

DE = 0V, RE = VCC, DI = 0V or V

, RE = X. DI = 0V or V

= 0V, or Full Duplex

Full - 560 700 µA

Full - 530 650 µA

Full - 0.07 2 µA

ESD PERFORMANCE

RS-485 Pins (A, Y, B, Z) Human Body Model (HBM), Pin to GND 25 - ±15 - kV All Other Pins HBM, per MIL-STD-883 Method 3015 25 - ±7-kV

DRIVER SWITCHING CHARACTERISTICS (115kbps Versions; ISL83080E, ISL83082E)

Driver Differential Output Delay t

PLH, tPHLRDIFF

Driver Differential Output Skew t Driver Differential Rise or Fall Time t Maximum Data Rate f Driver Enable to Output High t

Driver Enable to Output Low t

Driver Disable from Output Low t Driver Disable from Output High t Time to Shutdown t Driver Enable from Shutdown to

ZH(SHDN)RL

Output High Driver Enable from Shutdown to

Output Low

ZL(SHDN)RL

SKEW

, t

R MAX

LZ HZ

SHDN

= 54Ω, CL = 100pF (Figure 2) Full 500 780 1300 ns

= 54Ω, CL = 100pF (Figure 2) Full - 40 100 ns

DIFF

= 54Ω, CL = 100pF (Figure 2) Full 667 1000 1500 ns

DIFF

CD = 820pF (Figure 4, Note 12) Full 115 666 - kbps RL = 500Ω, CL = 100pF, SW = GND (Figure 3),

Full - 278 1500 ns

(Note 7) RL = 500Ω, CL = 100pF, SW = VCC (Figure 3),

Full - 35 1500 ns

(Note 7) RL = 500Ω, CL = 15pF, SW = VCC (Figure 3) Full - 67 100 ns RL = 500Ω, CL = 15pF, SW = GND (Figure 3) Full - 38 100 ns (Notes 9, 12) Full 60 160 600 ns

= 500Ω, CL = 100pF, SW = GND (Figure 3),

Full - 400 2000 ns

(Notes 9, 10)

= 500Ω, CL = 100pF, SW = VCC (Figure 3),

Full - 155 2000 ns

(Notes 9, 10)

DRIVER SWITCHING CHARACTERISTICS (500kbps Versions; ISL83083E, ISL83085E)

Driver Differential Output Delay t

PLH, tPHLRDIFF

Driver Differential Output Skew t Driver Differential Rise or Fall Time t Maximum Data Rate f Driver Enable to Output High t

SKEW

, t

R MAX

= 54Ω, CL = 100pF (Figure 2) Full 250 360 1000 ns

= 54Ω, CL = 100pF (Figure 2) Full - 20 100 ns

DIFF

= 54Ω, CL = 100pF (Figure 2) Full 200 475 750 ns

DIFF

CD = 820pF (Figure 4, Note 12) Full 500 1000 - kbps RL = 500Ω, CL = 100pF, SW = GND (Figure 3),

Full - 137 1000 ns

(Note 7)

Driver Enable to Output Low t

Driver Disable from Output Low t

RL = 500Ω, CL = 100pF, SW = VCC (Figure 3),

Full - 35 1000 ns

(Note 7) RL = 500Ω, CL = 15pF, SW = VCC (Figure 3) Full - 65 100 ns

FN6085.6

September 12, 2005

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Electrical Specifications Test Conditions: V

= 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = 25°C

(Note 4) (Continued)

TEMP

PARAMETER SYMBOL TEST CONDITIONS

Driver Disable from Output High t Time to Shutdown t Driver Enable from Shutdown to

ZH(SHDN)RL

Output High Driver Enable from Shutdown to

Output Low

ZL(SHDN)RL

SHDN

RL = 500Ω, CL = 15pF, SW = GND (Figure 3) Full - 38 100 ns (Notes 9, 12) Full 60 160 600 ns

= 500Ω, CL = 100pF, SW = GND (Figure 3),

(Notes 9, 10)

= 500Ω, CL = 100pF, SW = VCC (Figure 3),

(Notes 9, 10)

(°C) MIN TYP MAX UNITS

Full - 260 1500 ns

Full - 155 1500 ns

DRIVER SWITCHING CHARACTERISTICS (10Mbps Versions; ISL83086E, ISL83088E)

Driver Differential Output Delay t

PLH, tPHLRDIFF

Driver Differential Output Skew t Driver Differential Rise or Fall Time t Maximum Data Rate f Driver Enable to Output High t

SKEW

, t

R MAX

= 54Ω, CL = 100pF (Figure 2) Full - 20 60 ns

= 54Ω, CL = 100pF (Figure 2) Full - 1 10 ns

DIFF

= 54Ω, CL = 100pF (Figure 2) Full - 13 25 ns

DIFF

CD = 470pF (Figure 4, Note 12) Full 10 15 - Mbps RL = 500Ω, CL = 100pF, SW = GND (Figure 3),

Full - 35 150 ns

(Note 7)

Driver Enable to Output Low t

Driver Disable from Output Low t Driver Disable from Output High t Time to Shutdown t Driver Enable from Shutdown to

ZH(SHDN)RL

Output High Driver Enable from Shutdown to

Output Low

ZL(SHDN)RL

LZ HZ

SHDN

RL = 500Ω, CL = 100pF, SW = VCC (Figure 3),

Full - 30 150 ns

(Note 7) RL = 500Ω, CL = 15pF, SW = VCC (Figure 3) Full - 66 100 ns RL = 500Ω, CL = 15pF, SW = GND (Figure 3) Full - 38 100 ns (Notes 9, 12) Full 60 160 600 ns

= 500Ω, CL = 100pF, SW = GND (Figure 3),

Full - 115 250 ns

(Notes 9, 10)

= 500Ω, CL = 100pF, SW = VCC (Figure 3),

Full - 84 250 ns

(Notes 9, 10)

RECEIVER SWITCHING CHARACTERISTICS (115kbps and 500kbps Versions; ISL83080E-ISL83085E)

Maximum Data Rate f Receiver Input to Output Delay t Receiver Skew | t

PLH

- t

PHL

PLH

Receiver Enable to Output Low t

Receiver Enable to Output High t

Receiver Disable from Output Low t Receiver Disable from Output High t Time to Shutdown t Receiver Enable from Shutdown to

ZH(SHDN)RL

Output High Receiver Enable from Shutdown to

Output Low

ZL(SHDN)RL

MAX

SKD

LZ HZ

SHDN

(Figure 5, Note 12) Full 0.5 10 - Mbps

, t

(Figure 5) Full - 100 150 ns

PHL

(Figure 5) Full - 7 10 ns RL = 1kΩ, CL = 15pF, SW = VCC (Figure 6),

Full - 10 50 ns

(Note 8) RL = 1kΩ, CL = 15pF, SW = GND (Figure 6),

Full - 10 50 ns

(Note 8) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 6) Full - 10 50 ns RL = 1kΩ, CL = 15pF, SW = GND (Figure 6) Full - 10 50 ns (Notes 9, 12) Full 60 160 600 ns

= 1kΩ, CL = 15pF, SW = GND (Figure 6),

Full - 150 2000 ns

(Notes 9, 11)

= 1kΩ, CL = 15pF, SW = VCC (Figure 6),

Full - 150 2000 ns

(Notes 9, 11)

RECEIVER SWITCHING CHARACTERISTICS (10Mbps Versions; ISL83086E, ISL83088E)

Maximum Data Rate f Receiver Input to Output Delay t Receiver Skew | t

PLH

- t

PHL

PLH

Receiver Enable to Output Low t

MAX

SKD

(Figure 5, Note 12) Full 10 15 - Mbps

, t

(Figure 5) Full - 70 125 ns

PHL

(Figure 5) Full - 0 10 ns RL = 1kΩ, CL = 15pF, SW = VCC (Figure 6),

Full - 10 30 ns

(Note 8)

FN6085.6

September 12, 2005

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Electrical Specifications Test Conditions: V

= 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = 25°C

(Note 4) (Continued)

TEMP

PARAMETER SYMBOL TEST CONDITIONS

Receiver Enable to Output High t

Receiver Disable from Output Low t Receiver Disable from Output High t Time to Shutdown t Receiver Enable from Shutdown to

ZH(SHDN)RL

Output High Receiver Enable from Shutdown to

Output Low

ZL(SHDN)RL

LZ HZ

SHDN

RL = 1kΩ, CL = 15pF, SW = GND (Figure 6), (Note 8)

RL = 1kΩ, CL = 15pF, SW = VCC (Figure 6) Full - 10 30 ns RL = 1kΩ, CL = 15pF, SW = GND (Figure 6) Full - 10 30 ns (Notes 9, 12) Full 60 160 600 ns

= 1kΩ, CL = 15pF, SW = GND (Figure 6),

(Notes 9, 11)

= 1kΩ, CL = 15pF, SW = VCC (Figure 6),

(Notes 9, 11)

(°C) MIN TYP MAX UNITS

Full - 10 30 ns

Full - 150 2000 ns

NOTES:

4. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified.

5. Supply current specification is valid for loaded drivers when DE = 0V.

6. Applies to peak current. See “Typical Performance Curves” for more information.

7. Keep RE

8. The RE

Transceivers are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 60ns, the parts are guaranteed

= 0 to prevent the device from entering SHDN.

signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN.

not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See “Low-Power Shutdown Mode” section.

10. Keep RE

11. Set the RE

= VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN.

signal high time >600ns to ensure that the device enters SHDN.

12. Guaranteed by characterization but not tested.

Test Circuits and Wavef orms

FIGURE 1A. VOD AND V

RL/2

FIGURE 1. DC DRIVER TEST CIRCUITS

RL = 60Ω

FIGURE 1B. VOD WITH COMMON MODE LOAD

375Ω

VCM

-7V to +12V

375Ω

FN6085.6

September 12, 2005

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Test Circuits and Wavef orms (Continued)

1.5V1.5V 0V

CL = 100pF

= 100pF

SIGNAL GENERATOR

DIFF

FIGURE 2A. TEST CIRCUIT FIGURE 2B. MEASUREMENT POINTS

FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES

SIGNAL GENERATOR

500Ω

GND

PARAMETER OUTPUT RE DI SW CL (pF)

ZH(SHDN)

ZL(SHDN)

Y/Z X 1/0 GND 15 Y/Z X 0/1 V

15 Y/Z 0 (Note 7) 1/0 GND 100 Y/Z 0 (Note 7) 0/1 V

100 Y/Z 1 (Note 10) 1/0 GND 100 Y/Z 1 (Note 10) 0/1 V

100

OUT (Z)

OUT (Y)

DIFF OUT (Y - Z)

NOTE 9

tZH, t

ZH(SHDN)

NOTE 9

OUT (Y, Z)

, t

ZL(SHDN)

NOTE 9

OUT (Y, Z)

PLH

- t

PHL

1.5V1.5V

VOH - 0.5V

VOL + 0.5V

PLH

90% 90%

10% 10%

SKEW = |t

OUTPUT HIGH

2.3V

OUTPUT LOW

-V

SIGNAL GENERATOR

FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS

FIGURE 3. DRIVER ENABLE AND DISABLE TIMES

60Ω

FIGURE 4A. TEST CIRCUIT

DIFF OUT (Y - Z)

FIGURE 4B. MEASUREMENT POINTS

-V

FIGURE 4. DRIVER DATA RATE

FN6085.6

September 12, 2005

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Test Circuits and Wavef orms (Continued)

SIGNAL GENERATOR

FIGURE 5A. TEST CIRCUIT FIGURE 5B. MEASUREMENT POINTS

FIGURE 5. RECEIVER PROPAGATION DELAY AND DATA RATE

B A

15pF

SIGNAL GENERATOR

GND

PARAMETER DE A SW

0 +1.5V GND 0 -1.5V V

tZH (Note 8) 0 +1.5V GND

(Note 8) 0 -1.5V V

ZH(SHDN)

ZL(SHDN)

(Note 11) 0 +1.5V GND

(Note 11) 0 -1.5V V

FIGURE 6A. TEST CIRCUIT FIGURE 6B. MEASUREMENT POINTS

FIGURE 6. RECEIVER ENABLE AND DISABLE TIMES

15pF

1kΩ

GND

tZH, t

ZH(SHDN)

NOTE 9

, t

ZL(SHDN)

NOTE 9

PLH

1.5V 1.5V

OUTPUT HIGH

1.5V

OUTPUT LOW

PHL

1.5V1.5V

0V0V

+1.5V

-1.5V

VOH - 0.5V

VOL + 0.5V

Application Information

RS-485 and RS-422 are differential (balanced) data transmission standards for use in long haul or noisy environments. RS-422 is a subset of RS-485, so RS-485 transceivers are also RS-422 compliant. RS-422 is a pointto-multipoint (multidrop) standard, which allows only one driver and up to 10 (assuming one unit load devices) receivers on each bus. RS-485 is a true multipoint standard, which allows up to 32 one unit load devices (any combination of drivers and receivers) on each bus. To allow for multipoint operation, the RS-485 spec requires that drivers must handle bus contention without sustaining any damage.

Another important advantage of RS-485 is the extended common mode range (CMR), which specifies that the driver outputs and receiver inputs withstand signals that range from +12V to -7V. RS-422 and RS-485 are intended for runs as long as 4000’, so the wide CMR is necessary to handle ground potential differences, as well as voltages induced in the cable by external fields.

Receiver Features

These devices utilize a diff erential input receiv er f or maxim um noise immunity and common mode rejection. Input sensitivity is ±200mV, as required by the RS-422 and RS-485 specifications.

Receiver input resistance of 96kΩ surpasses the RS-422 spec of 4kΩ, and is eight times the RS-485 “Unit Load (UL)” requirement of 12kΩ minimum. Thus, these products are known as “one-eighth UL” transceivers, and there can be up to 256 of these devices on a network while still complying with the RS-485 loading spec.

Receiver inputs function with common mode voltages as great as ±7V outside the power supplies (i.e., +12V and

-7V), making them ideal for long networks where induced voltages are a realistic concern.

All the receivers include a “full fail-safe” function that guarantees a high level receiver output if the receiver inputs are unconnected (floating) or shorted.

FN6085.6

September 12, 2005

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Receivers easily meet the data rates supported by the corresponding driver, and all receiver outputs are threestatable via the active low RE

input.

Driver Features

The RS-485/422 driver is a differential output device that delivers at least 1.5V across a 54Ω load (RS-485), and at least 2V across a 100Ω load (RS-422). The drivers feature low propagation delay skew to maximize bit width, and to minimize EMI.

All drivers are three-statable via the active high DE input. The 115kbps and 500kbps driver outputs are slew rate

limited to minimize EMI, and to minimize reflections in unterminated or improperly terminated networks. Outputs of the ISL83086E, ISL83088E drivers are not limited, so faster output transition times allow data rates of at least 10Mbps.

Hot Plug Function

When a piece of equipment powers up, there is a period of time where the processor or ASIC driving the RS-485 control lines (DE, RE

) is unable to ensure that the RS-485 Tx and Rx outputs are kept disabled. If the equipment is connected to the bus, a driver activating prematurely during power up may crash the bus. To avoid this scenario, the ISL83080, ISL83082, ISL83083, ISL83085 versions incorporate a “Hot Plug” function. Circuitry monitoring V

ensures that, during

power up and power down, the Tx and Rx outputs remain disabled, regardless of the state of DE and RE

, if VCC is less than ~3.4V . This giv es the processor/ASIC a chance to stabilize and drive the RS-485 control lines to the proper states.

DI = V

A/Y

2.5

DRIVER Y OUTPUT (V)

FIGURE 7. HOT PLUG PERFORMANCE (ISL83080E) vs

3.4V

ISL83080E

TIME (40µs/DIV)

DEVICE WITHOUT HOT PLUG CIRCUITRY (ISL83086E)

3.2V

RL = 1kΩ

2.5 0

ESD Protection

All pins on these devices include class 3 Human Body Model (HBM) ESD protection structures, but the RS-485 pins (driver outputs and receiver inputs) incorporate advanced structures allowing them to survive ESD events in excess of ±15kV HBM. The RS-485 pins are particularly vulnerable to ESD damage because they typically connect

to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, protect without allowing any latchup mechanism to activate, and without degrading the RS-485 common mode range of -7V to +12V. This built-in ESD protection eliminates the need for board level protection structures (e.g., transient suppression diodes), and the associated, undesirable capacitive load they present.

Data Rate, Cables, and Terminations

RS-485/422 are intended for network lengths up to 4000’, but the maximum system data rate decreases as the transmission length increases. Devices operating at 10Mbps are limited to lengths less than 100’, while the 115kbps versions can oper ate at full data rates wit h lengths of se v er al thousand feet.

Twisted pair is the cable of choice for RS-485/422 networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common mode signals, which are effectively rejected by the differential receivers in these ICs.

Proper termination is imperative, when using the 10Mbps devices, to minimize reflections. Short networks using the 115kbps versions need not be terminated, but, terminations are recommended unless power dissipation is an overriding concern.

In point-to-point, or point-to-multipoint (single driver on bus) networks, the main cable should be terminated in its characteristic impedance (typically 120Ω) at the end farthest from the driver. In multi-receiver applications, stubs

(V)

connecting receivers to the main cable should be kept as short as possible. Multipoint (multi-driver) systems require that the main cable be terminated in its characteristic impedance at both ends. Stubs connecting a transceiver to the main cable should be kept as short as possible.

Built-In Driver Overload Protection

As stated previously, the RS-485 spec requires that drivers survive worst case bus contentions undamaged. These devices meet this requirement via driver output short circuit current limits, and on-chip thermal shutdown circuitry.

The driver output stages incorporate short circuit current

RECEIVER OUTPUT (V)

limiting circuitry which ensures that the output current never exceeds the RS-485 spec, even at the common mode voltage range extremes. Additionally, these devices utilize a foldback circuit which reduces the short circuit current, and thus the power dissipation, whenever the contending voltage exceeds either supply.

In the event of a major short circuit condition, devices also include a thermal shutdown feature that disables the drivers whenever the die temper ature becomes excessive. This eliminates the power dissipation, allowing the die to cool. Th e drivers automatically re-enable after the die temperature drops about 15 degrees. If the contention persists, the thermal shutdown/re-enable cycle repeats until the fault is cleared. Receivers stay oper ationa l during thermal shutdown.

FN6085.6

September 12, 2005

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Low Power Shutdown Mode

These CMOS transceivers all use a fraction of the power required by their bipolar counterparts, but they also include a shutdown feature that reduces the already low quiescent I to a 70nA trickle. These devices enter shutdown whenever the receiver and driver are simultaneously disabled

=VCC and DE = GND) for a period of at least 600ns.

(RE

Typical Performance Curves V

DRIVER OUTPUT CURRENT (mA)

012345

DIFFERENTIAL OUTPUT VOLTAGE (V)

FIGURE 8. DRIVER OUTPUT CURRENT vs DIFFERENTIAL

OUTPUT VOLTAGE

= 5V, TA = 25°C; Unless Otherwise Specified

Disabling both the driver and the receiver for less than 60ns guarantees that the transceiver will not enter shutdown.

Note that receiver and driver enable times increase when the transceiver enables from shutdown. Refer to Notes 7-11, at the end of the Electrical Specification table, for more information.

3.4

3.2

2.8

2.6

2.4

2.2

DIFFERENTIAL OUTPUT VOLTAGE (V)

-40 0 50 85

-25 25 75

FIGURE 9. DRIVER DIFFERENTIAL OUTPUT VOL T AGE vs

TEMPERATURE

= 100Ω

DIFF

TEMPERATURE (°C)

DIFF

= 54Ω

200

150

Y OR Z = LOW

100

-50

OUTPUT CURRENT (mA)

-100

-150

-7 -6 -4 -2 0 2 4 6 8 10 12

ISL8308XE

OUTPUT VOLTAGE (V)

ISL83080E thru ISL83085E

Y OR Z = HIGH

ISL83086E/88E

FIGURE 10. DRIVER OUTPUT CURRENT vs SHORT CIRCUIT

VOLTAGE

560

550

540

530

(µA)

520

510

500

-40 0 50 85

HALF DUPLEX, DE = VCC, RE = X

HALF DUPLEX, DE = GND, RE = GND FULL DUPLEX, DE = X, RE

-25 25 75 TEMPERATURE (°C)

= GND

FIGURE 11. SUPPLY CURRENT vs TEMPERATURE

FN6085.6

September 12, 2005

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Typical Performance Curves V

880

860

840

820

800

780

PROPAGATION DELAY (ns)

760

740

-40 0 50 85

-25 25 75 TEMPERATURE (°C)

= 5V, TA = 25°C; Unless Otherwise Specified (Continued)

PHL

PLH

FIGURE 12. DRIVER DIFFERENTIAL PROPA GA TION DELAY

vs TEMPERATURE (ISL83080E, ISL83082E)

400

390

380

370

360

PROPAGATION DELAY (ns)

350

340

-40 0 50 85

-25 25 75 TEMPERATURE (°C)

PHL

PLH

FIGURE 14. DRIVER DIFFERENTIAL PROPA GA TION DELAY

vs TEMPERATURE (ISL83083E, ISL83085E)

SKEW (ns)

|CROSS PT. OF Y↑ & Z↓ - CROSS PT. OF Y↓ & Z↑|

-40 0 50 85

-25 25 75 TEMPERATURE (°C)

FIGURE 13. DRIVER DIFFERENTIAL SKEW vs

TEMPERATURE (ISL83080E, ISL83082E)

27 26 25 24 23 22

SKEW (ns)

21 20 19 18

|CROSS PT. OF Y↑ & Z↓ - CROSS PT. OF Y↓ & Z↑|

-40 0 50 85

-25 25 75 TEMPERATURE (°C)

FIGURE 15. DRIVER DIFFERENTIAL SKEW vs

TEMPERATURE (ISL83083E, ISL83085E)

PROPAGATION DELAY (ns)

-40 0 50 85

-25 25 75 TEMPERATURE (°C)

PHL

PLH

FIGURE 16. DRIVER DIFFERENTIAL PROPA GA TION DELAY

vs TEMPERATURE (ISL83086E, ISL83088E)

0.7

0.65

0.6

SKEW (ns)

0.55

0.5

|CROSS PT. OF Y↑ & Z↓ - CROSS PT. OF Y↓ & Z↑|

-40 0 50 85

-25 25 75 TEMPERATURE (°C)

FIGURE 17. DRIVER DIFFERENTIAL SKEW vs

TEMPERATURE (ISL83086E, ISL83088E)

September 12, 2005

FN6085.6

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Typical Performance Curves V

DIFF

5 0

RECEIVER OUTPUT (V)

4 3

B/Z

A/Y

1 0

DRIVER OUTPUT (V)

TIME (400ns/DIV)

= 54Ω, CL = 100pF

FIGURE 18. DRIVER AND RECEIVER WAVEFOR MS,

LOW TO HIGH (ISL83080E, ISL83082E)

= 54Ω, CL = 100pF

DIFF

5 0

RECEIVER OUTPUT (V)

= 5V, TA = 25°C; Unless Otherwise Specified (Continued)

5 0

DRIVER INPUT (V)

5 0

RECEIVER OUTPUT (V)

4 3

2 1 0

DRIVER OUTPUT (V)

A/Y

B/Z

TIME (400ns/DIV)

FIGURE 19. DRIVER AND RECEIVER WAVEFORMS,

HIGH TO LOW (ISL83080E, ISL83082E)

5 0

DRIVER INPUT (V)

5 0

RECEIVER OUTPUT (V)

= 54Ω, CL = 100pF

DIFF

= 54Ω, CL = 100pF

DIFF

5 0

DRIVER INPUT (V)

5 0

DRIVER INPUT (V)

4 3

B/Z

A/Y

1 0

DRIVER OUTPUT (V)

TIME (200ns/DIV)

FIGURE 20. DRIVER AND RECEIVER WAVEFOR MS,

LOW TO HIGH (ISL83083E, ISL83085E)

= 54Ω, CL = 100pF

DIFF

5 0

RECEIVER OUTPUT (V)

B/Z

A/Y

DRIVER OUTPUT (V)

TIME (20ns/DIV)

FIGURE 22. DRIVER AND RECEIVER WAVEFOR MS,

LOW TO HIGH (ISL83086E, ISL83088E)

5 0

DRIVER INPUT (V)

A/Y

B/Z

1 0

DRIVER OUTPUT (V)

TIME (200ns/DIV)

FIGURE 21. DRIVER AND RECEIVER WAVEFORMS,

HIGH TO LOW (ISL83083E, ISL83085E)

= 54Ω, CL = 100pF

DIFF

5 0

RECEIVER OUTPUT (V)

A/Y

B/Z

1 0

DRIVER OUTPUT (V)

TIME (20ns/DIV)

FIGURE 23. DRIVER AND RECEIVER WAVEFORMS,

HIGH TO LOW (ISL83086E, ISL83088E)

5 0

DRIVER INPUT (V)

FN6085.6

September 12, 2005

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Typical Performance Curves V

40 35 30

20 15

RECEIVER OUTPUT CURRENT (mA)

012345

VOL, 25°C

VOH, 25°C

VOH, 85°C

RECEIVER OUTPUT VOLTAGE (V)

= 5V, TA = 25°C; Unless Otherwise Specified (Continued)

VOL, 85°C

FIGURE 24. RECEIVER OUTPUT CURRENT vs RECEIVER

OUTPUT VOLTAGE

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND

TRANSISTOR COUNT:

525

PROCESS:

Si Gate BiCMOS

FN6085.6

September 12, 2005

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Mini Small Outline Plastic Packages (MSOP)

EE1

INDEX

AREA

AA1A2

-H-

SIDE VIEW

TOP VIEW

NOTES:

1. These package dimensions are within allowable dimensions of JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.

-B-

0.20 (0.008) A

GAUGE PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING PLANE

0.20 (0.008) C

- H -

4X θ

END VIEW

-B-

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 A1 0.002 0.006 0.05 0.15 A2 0.030 0.037 0.75 0.95 -

b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4

e 0.026 BSC 0.65 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N8 87

R 0.003 - 0.07 - R1 0.003 - 0.07 - -

o o

Rev. 2 01/03

NOTESMIN MAX MIN MAX

FN6085.6

September 12, 2005

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Small Outline Plastic Packages (SOIC)

INDEX AREA

123

SEA TING PLANE

-AD

0.25(0.010) C AM BS

-B-

-C-

0.25(0.010) BM M

0.10(0.004)

h x 45

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

M14.15 (JEDEC MS-012-AB ISSUE C)

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 D 0.3367 0.3444 8.55 8.75 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC H 0.2284 0.2440 5.80 6.20 h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N14 147

Rev. 0 12/93

NOTESMIN MAX MIN MAX

FN6085.6

September 12, 2005

ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E, ISL83088E

Small Outline Plastic Packages (SOIC)

INDEX AREA

123

SEA TING PLANE

-AD

0.25(0.010) C AM BS

-B-

-C-

0.25(0.010) BM M

0.10(0.004)

h x 45

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6

N8 87

Rev. 0 12/93

NOTESMIN MAX MIN MAX

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6085.6

September 12, 2005

intersil ISL83080E, ISL83082E, ISL83083E, ISL83085E, ISL83086E DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual