intersil ISL8105, ISL8105A DATA SHEET

®

ISL8105, ISL8105A

Data Sheet April 20, 2007 FN6306.4

+5V or +12V Single-Phase Synchronous
Buck Converter PWM Controller with
Integrated MOSFET Gate Drivers

The ISL8105 is a simple single-phase PWM controller for a
synchronous buck converter. It operates from +5V or +12V bias
supply voltage. With integrated linear regulator, boot diode, and
N-Channel MOSFET gate drivers, the ISL8105 reduces
external component count and board space requirements.
These make the IC suitable for a wide range of applications.

Utilizing voltage-mode control, the output voltage can be
precisely regulated to as low as 0.6V. The 0.6V internal
reference features a maximum tolerance of ±1.0% over the
commercial temperature range, and ±1.5% over the
industrial temperature range. Two fixed oscillator frequency
versions are available; 300kHz (ISL8105 for high efficiency
applications) and 600kHz (ISL8105A for fast transient
applications).

The ISL8105 features the capability of safe start-up with
pre-biased load. It also provides overcurrent protection by
monitoring the ON-resistance of the bottom-side MOSFET to
inhibit PWM operation appropriately. During start-up interval,
the resistor connected to BGATE/BSOC pin is employed to
program overcurrent protection condition. This approach
simplifies the implementation and does not deteriorate
converter efficiency.

Pinouts

ISL8105

(10 LD 3X3 DFN)

TOP VIEW

BOOT

TGATE

N/C

GND

BGATE/BSOC

1
2
3
4
5

GND

ISL8105

(8 LD SOIC)

TOP VIEW

10

9
8
7
6

LX
COMP/EN

FB
N/C
VBIAS

Features

• Operates from +5V or +12V Bias Supply Voltage

- 1.0V to 12V Input Voltage Range (up to 20V possible
with restrictions; see Input Voltage Considerations)

- 0.6V to VIN Output Voltage Range

• 0.6V Internal Reference Voltage

- ±1.0% Tolerance Over the Commercial Temperature
Range (0°C to +70°C)

- ±1.5% Tolerance Over the Industrial T e mperature
Range (-40°C to +85°C).

• Integrated MOSFET Gate Drivers that Operate from
(+5V to +12V)

V

BIAS

- Bootstrapped High-side Gate Driver with Integrated
Boot Diode

- Drives N-Channel MOSFETs

• Simple Voltage-Mode PWM Control

- Traditional Dual Edge Modulation

• Fast Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Cycle

• Fixed Operating Frequency

- 300kHz for ISL8105

- 600kHz for ISL8105A

• Fixed Internal Soft-Start with Pre-biased Load Capability

• Lossless, Programmable Overcurrent Protection

- Uses Bottom-side MOSFET’s r

DS(ON)

• Enable/Disable Function Using COMP/EN Pin

• Output Current Sourcing and Sinking Currents

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• 5V or 12V DC/DC Regulators

• Industrial Power Systems

• Telecom and Datacom Applications

• Test and Measurement Instruments

• Distributed DC/DC Power Architecture

• Point of Load Modules

BOOT

TGATE

GND

BGATE/BSOC

LX

1

2

3

4

1

8

COMP/EN

7

FB

6

5

VBIAS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved

ISL8105, ISL8105A

Ordering Information

PART NUMBER

(Note)

ISL8105CRZ* 5CRZ 300 0 to +70 10 Ld DFN L10.3X3C
ISL8105IBZ* 8105 IBZ 300 -40 to +85 8 Ld SOIC M8.15
ISL8105IRZ* 5IRZ 300 -40 to +85 10 Ld DFN L10.3X3C
ISL8105ACRZ* 05AZ 600 0 to +70 10 Ld DFN L10.3X3C
ISL8105AIBZ* 8105 AIBZ 600 -40 to +85 8 Ld SOIC M8.15
ISL8105AIRZ* 5AIZ 600 -40 to +85 10 Ld DFN L10.3X3C
ISL8105AEVAL1Z Evaluation Board
*Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products em ploy special Pb -free mat erial set s; mol ding compou nds/die at tach m aterials a nd 100% matte tin plate
termination finish, which are RoHS compliant and compatible with bot h SnPb and Pb-free soldering operat ions. Intersil Pb-free products are MSL cl assified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

SWITCHING

FREQUENCY (kHz)

TEMPERATURE

RANGE (°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

Typical Application Diagram

V

IN

BOOT

TGATE

LX

C

HF

C

BOOT

R

BSOC

C

BULK

Q1

Q2

L

OUT

C

OUT

V

OUT

V

BIAS

+5V OR +12V

+1V TO +12V

C

DCPL

VBIAS

COMP/EN

C

1

C

2

R

2

C

3

FB

R

3

ISL8105

BGATE/BSOC

GND

R

R

0

2

1

FN6306.4

April 20, 2007

Block Diagram

3

SAMPLE

AND

HOLD

+

­OC

COMPARATOR

POR AND

SOFT-START

5V INT.

INTERNAL

REGULATOR

VBIAS

D

BOOT

BOOT

TGATE

21.5μA

20kΩ

PWM

TO

BGATE/BSOC

FB

5V INT.

20μA

COMP/EN

April 20, 2007

FN6306.4

0.4V

0.6V

+

-

ERROR

AMP

DIS

+

-

FIXED 300kHZ OR 600kHz

COMPARATOR

+

-

OSCILLATOR

INHIBIT

PWM

DIS

GATE

CONTROL

LOGIC

GND

V

BIAS

LX

BGATE/BSOC

ISL8105, ISL8105A

ISL8105, ISL8105A

Absolute Maximum Ratings Thermal Information

Bias Voltage, V
Boot Voltage, V
TGATE Voltage, V
BGATE/BSOC Voltage, V
LX Voltage, V
Upper Driver Supply Voltage, V
Clamp Voltage, V

FB, COMP/EN Voltage . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6V

. . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +15.0V

BIAS

. . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +36.0V

BOOT

. . . . . . . . . . . . . . . . . . . .GND - 0.3V to V

LX

. . . . . . . . . . . . . VLX - 0.3V to V

TGATE

BOOT

BGATE/BSOC

- V

BIAS

. . . .GND - 0.3 to V

- VLX . . . . . . . . . . . . . . . . . .15V

BOOT

. . . . . . . . . . . . . . . . . . . . . . . . . . . .24V

BOOT

BIAS

BOOT

+ 0.3V

+ 0.3V
+ 0.3V

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150V

Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0kV

Recommended Operating Conditions

Bias Voltage, V
Ambient Temperature Range

ISL8105C, ISL8105AC . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

ISL8105I, ISL8105AI. . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Junction Temperature Range. . . . . . . . . . . . . . . . . . . .-40°C to +125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.

1. θ

JA

2. For θ

JC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

INPUT SUPPLY CURRENTS

Shutdown V

DISABLE

Disable Threshold (COMP/EN pin) V

OSCILLATOR

Nominal Frequency Range f

Ramp Amplitude (Note 3) ΔV

POWER-ON RESET

Rising V
V

BIAS

POR Threshold Hysteresis V

BIAS

REFERENCE

Nominal Reference Voltage V
Reference Voltage Tolerance ISL8105C (0°C to +70°C) -1.0 +1.0 %

ERROR AMPLIFIER

DC Gain (Note 3) GAIN
Unity Gain-Bandwidth (Note 3) UGBW 20 MHz
Slew Rate (Note 3) SR 9 V/μs

GATE DRIVERS

TGATE Source Resistance R

. . . . . . . +5V ±10%, +12V ±20%, or 6.5V to 14.4V

BIAS

, the “case temp” location is the center of the exposed metal pad on the package underside.

Supply Current I

BIAS

VBIAS_S

DISABLE

OSC

V

= 12V; Disabled 4 5.2 7 mA

BIAS

ISL8105C 270 300 330 kHz
ISL8105I 240 300 330 kHz

f

OSC

ISL8105AC 540 600 660 kHz
ISL8105AI 510 600 660 kHz

OSC

Threshold V

POR_R
POR_H

REF

ISL8105I (-40°C to +85°C) -1.5 +1.5 %

DC

V

TG-SRCh

= 14.5V, 50mA Source Current 3.0 Ω

BIAS

Thermal Resistance (Note 1) θ

(°C/W) θJC (°C/W)

JA

SOIC Package . . . . . . . . . . . . . . . . . . . 95 N/A

DFN Package (Note 2). . . . . . . . . . . . . 44 5.5

Maximum Junction Temperature

(Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C

(SOIC - Lead Tips Only)

0.375 0.4 0.425 V

1.5 V

P-P

3.9 4.1 4.3 V

0.30 0.35 0.40 mV

0.6 V

96 dB

4

FN6306.4

April 20, 2007

ISL8105, ISL8105A

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

TGATE Source Resistance R
TGATE Sink Resistance R
TGATE Sink Resistance R
BGATE Source Resistance R
BGATE Source Resistance R
BGATE Sink Resistance R
BGATE Sink Resistance R

OVERCURRENT PROTECTION (OCP)

BSOC Current Source I

NOTE:

3. Test conditions are guaranteed by design simulation.

TG-SRCl

TG-SNKh

TG-SNKl

BG-SRCh

BG-SRCl

BG-SNKh

BG-SNKl

BSOC

V

= 4.25V, 50mA Source Current 3.5 Ω

BIAS

V

= 14.5V, 50mA Source Current 2.7 Ω

BIAS

V

= 4.25V, 50mA Source Current 2.7 Ω

BIAS

V

= 14.5V, 50mA Source Current 2.4 Ω

BIAS

V

= 4.25V, 50mA Source Current 2.75 Ω

BIAS

V

= 14.5V, 50mA Source Current 2.0 Ω

BIAS

V

= 4.25V, 50mA Source Current 2.1 Ω

BIAS

ISL8105C; BGATE/BSOC Disabled 19.5 21.5 23.5 µA
ISL8105I; BGATE/BSOC Disabled 18.0 21.5 23.5 µA

Functional Pin Description (SOIC, DFN)

BOOT (SOIC Pin 1, DFN Pin 1)

This pin provides ground referenced bias voltage to the
top-side MOSFET driver. A bootstrap circuit is used to create
a voltage suitable to drive an N-Channel MOSFET (equal to
V

minus the on-chip BOOT diode voltage drop), with

BIAS

respect to LX.

TGATE (SOIC Pin 2, DFN Pin 2)

Connect this pin to the gate of top-side MOSFET; it provides
the PWM-controlled gate drive. It is also monitored by the
adaptive shoot-through protection circuitry to determine
when the top-side MOSFET has turned off.

GND (SOIC Pin 3, DFN Pin 4)

This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.

BGATE/BSOC (SOIC Pin 4, DFN Pin 5)

Connect this pin to the gate of the bottom-side MOSFET; it
provides the PWM-controlled gate drive (from V
pin is also monitored by the adaptive shoot-through
protection circuitry to determine when the lower MOSFET
has turned off.

During a short period of time following Power-On Reset
(POR) or shut-down release, this pin is also used to
determine the current limit threshold of the converter.
Connect a resistor (R

) from this pin to GND. See

BSOC

“Overcurrent Protection (OCP)” on page 7 for equations. An
overcurrent trip cycles the soft-sta rt fu nct i on , after two
dummy soft-start time-outs. Some of the text describing the
BGATE function may leave off the BSOC part of the name,
when it is not relevant to the discussion.

BIAS

). This

VBIAS (SOIC Pin 5, DFN Pin 6)

This pin provides the bias supply for the ISL8105, as well as
the bottom-side MOSFET's gate and the BOOT voltage for
the top-side MOSFET's gate. An internal 5V regulator will
supply bias if V
and BOOT will still be sourced by V

rises above 6.5V (but the BGATE/BSOC

BIAS

). Connect a well

BIAS

decoupled +5V or +12V supply to this pin.

FB (SOIC Pin 6, DFN Pin 8)

This pin is the inverting input of the internal error amplifier.
Use FB, in combination with the COMP/EN pin, to
compensate the voltage-control feedback loop of the
converter. A resistor divider from the output to GND is used
to set the regulation voltage.

COMP/EN (SOIC Pin 7, DFN Pin 9)

This is a multiplexed pin. During soft-start and normal converter
operation, this pin represents the output of the error amplifier.
Use COMP/EN, in combination with the FB pin, to compensate
the voltage-control feedback loop of the converter.

Pulling COMP/EN low (V

DISABLE

= 0.4V nominal) will
disable (shut-down) the controller, which causes the
oscillator to stop, the BGATE and TGATE outputs to be held
low, and the soft-start circuitry to re-arm. The external
pull-down device will initially need to overcome maximum of
5mA of COMP/EN output current. However, once the IC is
disabled, the COMP output will also be disabled, so only a
20µA current source will continue to draw current.

When the pull-down device is released, the COMP/EN pin
will start to rise at a rate determined by the 20µA charging up
the capacitance on the COMP/EN pin. When the COMP/EN
pin rises above the V

DISABLE

trip point, the ISL8105 will

begin a new initialization and soft-start cycle.

LX (SOIC Pin 8, DFN Pin 10)

Connect this pin to the source of the top-side MOSFET and
the drain of the bottom-side MOSFET. It is used as the sink

5

FN6306.4

April 20, 2007

ISL8105, ISL8105A

for the TGATE driver and to monitor the voltage drop across
the bottom-side MOSFET for overcurrent protection. This pin
is also monitored by the adaptive shoot-through protection
circuitry to determine when the top-side MOSFET has turned
off.

N/C (DFN Only; Pin3, Pin 7)

These two pins in the DFN package are No Connect.

Functional Description

Initialization (POR and OCP Sampling)

Figure 1 shows a start-up waveform of ISL8105. The
Power-ON-Reset (POR) function continually monitors the
bias voltage at the VBIAS pin. Once the rising POR
threshold is exceeded 4V (V
initiates the Overcurrent Protection (OCP) sample and hold
operation (while COMP/EN is ~1V). When the sampling is
complete, V

~4V POR

begins the soft-start ramp.

OUT

nominal), the POR function

POR

V

V

BIAS

OUT

trip point. At t2, there is a variable time period for the OCP
sample and hold operation (0ms to 3.4ms nominal; the
longer time occurs with the higher overcurrent setting). The
sample and hold uses a digital counter and DAC to save the
voltage, so the stored value does not degrade, for as long as
the V

BIAS

is above V

. See “Overcurrent Protection

POR

(OCP)” on page 7 for more details on the equations and
variables. Upon the completion of sample and hold at t

, the

3

soft-start operation is initiated, and the output voltage ramps
up between t

t0

t1

and t5.

4

COMP/EN

BGATE/BSOC

3.4ms

3.4ms
t2 t3

BGATE
STARTS
SWITCHING

0ms to 3.4ms

t4

V

OUT

t5

V

COMP/EN

FIGURE 1. POR AND SOFT-START OPERATION

If the COMP/EN pin is held low during power-up, the
initialization will be delayed until the COMP/EN is released
and its voltage rises above the V

DISABLE

trip point.

Figure 2 shows a typical power-up sequence in more detail.
The initialization starts at t
V

, or the COMP/EN pin is released (after POR). The

POR

, when either V

0

rises above

BIAS

COMP/EN will be pulled up by an internal 20µA current
source, but the timing will not begin until the COMP/EN
exceeds the V

DISABLE

trip point (at t1). The external
capacitance of the disabling device, as well as the
compensation capacitors, will determine how quickly the
20µA current source will charge the COMP/EN pin. With
typical values, it should add a small delay compared to the
soft-start times. The COMP/EN will continue to ramp to ~1V.

From t

, there is a nominal 6.8ms delay, which allows the

1

VBIAS pin to exceed 6.5V (if rising up towards 12V), so that
the internal bias regulator can turn on cleanly. At the same
time, the BGATE/BSOC pin is initialized by disabling the
BGATE driver and drawing BSOC (nominal 21.5µA) through
R

. This sets up a voltage that will represent the BSOC

BSOC

FIGURE 2. BGATE/BSOC AND SOFT-START OPERATION

Soft-Start and Pre-Biased Outputs

Functionally, the soft-start internally ramps the reference on
the non-inverting terminal of the error amp from 0V to 0.6V in
a nominal 6.8ms. The output voltage will thus follow the
ramp, from zero to final value, in the same 6.8ms (the actual
ramp seen on the V
due to some initialization timing, between t

The ramp is created digitally, so there will be 64 small
discrete steps. There is no simple way to change this ramp
rate externally, and it is the same for either frequency
version of the IC (300kHz or 600kHz).

After an initialization period (t
(COMP/EN pin) is enabled, and begins to regulate the
converter's output voltage during soft-start. The oscillator's
triangular waveform is compared to the ramping error
amplifier voltage. This generates LX pulses of increasing
width that charge the output capacitors. When the internally
generated soft-start voltage exceeds the reference voltage
(0.6V), the soft-start is complete and the output should be in
regulation at the expected voltage. This method provides a
rapid and controlled output voltage rise; there is no large
inrush current charging the output capacitors. The entire
start-up sequence from POR typically takes up to 17ms; up
to 10.2ms for the delay and OCP sample and 6.8ms for the
soft-start ramp.

will be less than the nominal time),

OUT

to t4), the error amplifier

3

and t4).

3

6

FN6306.4

April 20, 2007

ISL8105, ISL8105A

Figure 3 shows the normal curve in blue; initialization begins
at t

, and the output ramps between t1 and t2. If the output is

0

pre-biased to a voltage less than the expected value, as
shown by the red curve, the ISL8105 will detect that
condition. Neither MOSFET will turn on until the soft-start
ramp voltage exceeds the output; V

starts seamlessly

OUT

ramping from there. If the output is pre-biased to a voltage
above the expected value, as in the gray curve, neither
MOSFET will turn on until the end of the soft-start, at which
time it will pull the output voltage down to the final value. Any
resistive load connected to the output will help pull down the
voltage (at the RC rate of the R of the load and the C of the
output capacitance).

V

OVER-CHARGED

OUT

PRE-BIASED

V

V

PRE-BIASED

OUT

OUT

V

NORMAL

V

NORMAL

OUT

OUT

If the V

t0 t1

IN

t1

FIGURE 3. SOFT-START WITH PRE-BIAS

for the synchronous buck converter is from a

different supply that comes up after V

BIAS

t2

t2

, the soft-start
would go through its cycle, but with no output voltage ramp.
When V
V

IN

100% duty cycle, with COMP/EN pin >4V). If V

turns on, the output would follow the ramp of the

IN

from zero up to the final expected voltage (at close to

is too fast,

IN

there may be excessive inrush current charging the output
capacitors (only the beginning of the ramp, from zero to
V

matters here). If this is not acceptable, then consider

OUT

changing the sequencing of the power supplies, or sharing
the same supply, or adding sequencing logic to the
COMP/EN pin to delay the soft-start until the V

supply is

IN

ready (see “Input Voltage Considerations” on page 9).
If the IC is disabled after soft-start (by pulling COMP/EN pin

low), and then enabled (by releasing the COMP/EN pin),
then the full initialization (including OCP sample) will take
place. However, there is no new OCP sampling during
overcurrent retries. If the output is shorted to GND during
soft-start, the OCP will handle it, as described in the next
section.

Overcurrent Protection (OCP)

The overcurrent function protects the converter from a
shorted output by using the bottom-side MOSFET's
on-resistance, r
(R

) programs the overcurrent trip level (see “Typical

BSOC

Application Diagram” on page 2). This method enhances the
converter's efficiency and reduces cost by eliminating a
current sensing resistor. If overcurrent is detected, the output
immediately shuts off, it cycles the soft-start function in a
hiccup mode (2 dummy soft-start time-outs, then up to one
real one) to provide fault protection. If the shorted condition
is not removed, this cycle will continue indefinitely.

Following POR (and 6.8ms delay), the ISL8105 initiates the
Overcurrent Protection sample and hold operation. The
BGATE driver is disabled to allow an internal 21.5 current
source to develop a voltage across R
samples this voltage (which is referenced to the GND pin) at
the BGATE/BSOC pin, and holds it in a counter and DAC
combination. This sampled voltage is held internally as the
Overcurrent Set Point, for as long as power is applied, or
until a new sample is taken after coming out of a shut-down.

The actual monitoring of the bottom-side MOSFET's
on-resistance starts 200ns (nominal) after the edge of the
internal PWM logic signal (that creates the rising external
BGATE signal). This is done to allow the gate transition
noise and ringing on the LX pin to settle out before
monitoring. The monitoring ends when the internal PWM
edge (and thus BGATE) goes low . The OCP can be detected
anywhere within the above window.

If the regulator is running at high TGATE duty cycles (around
75% for 600kHz or 87% for 300kHz operation), then the
BGATE pulse width may not be wide enough for the OCP to
properly sample the r
is too narrow (or not there at all) for 3 consecutive pulses,
then the third pulse will be stretched and/or inserted to the
425ns minimum width. This allows for OCP monitoring every
third pulse under this condition. This can introduce a small
pulse-width error on the output voltage, which will be
corrected on the next pulse; and the output ripple voltage will
have an unusual 3-clock pattern, which may look like jitter. If
the OCP is disabled (by choosing a too-high value of
R

, or no resistor at all), then the pulse stretching

BSOC

feature is also disabled. Figure 4 illustrates the BGATE pulse
width stretching, as the width gets smaller.

, to monitor the current. A resistor

DS(ON)

BSOC

. For those cases, if the BGA TE

DS(ON)

μA

. The ISL8105

If the output is shorted to GND during soft-start, the OCP will
handle it, as described in the next section.

7

FN6306.4

April 20, 2007

BGATE > 425ns

s

BGATE = 425ns

BGATE < 425ns

BGATE << 425ns

ISL8105, ISL8105A

MOSFETs is typically in the 20mV to 120mV ballpark
(500Ω to 3000Ω). If the voltage drop across R
too low, that can cause almost continuous OCP tripping and
retry. It would also be very sensitive to system noise and
inrush current spikes, so it should be avoided. The maximum
usable setting is around 0.2V across R
the MOSFET); values above that might disable the
protection. Any voltage drop across R
than 0.3V (0.6V MOSFET trip point) will disable the OCP.
The preferred method to disable OCP is simply to remove
the resistor, which will be detected as no OCP.

Note that conditions during power-up or during a retry may
look different than normal operation. During power-up in a
12V system, the IC starts operation just above 4V; if the
supply ramp is slow, the soft-start ramp might be over well
before 12V is reached. So with bottom-side gate drive
voltages, the r
power-up, effectively lowering the OCP trip. In addition, the
ripple current will likely be different at lower input voltage.

Another factor is the digital nature of the soft-start ramp. On
each discrete voltage step, there is in effect a small load
transient, and a current spike to charge the ou tput
capacitors. The height of the current spike is not controlled; it
is affected by the step size of the output, the value of the
output capacitors, as well as the IC error amp compensation.
So it is possible to trip the overcurrent with inrush current, in
addition to the normal load and ripple considerations.

BSOC

BSOC

of the MOSFETs will be higher during

DS(ON)

is set

BSOC

(0.4V across

that is greater

FIGURE 4. BGATE PULSE STRETCHING

The overcurrent function will trip at a peak inductor current
(I

) determined by:

PEAK

2I

I

PEAK

where I

× R

------------------------------------------------------

=

BSOC

BSOC

r

DS ON()

×

BSOC

(EQ. 1)

is the internal BSOC current source (21.5µA
typical). The scale factor of 2 doubles the trip point of the
MOSFET voltage drop, compared to the setting on the
R

resistor. The OC trip point varies in a system mainly

BSOC

due to the MOSFET's r

variations (over process,

DS(ON)

current and temperature). To avoid overcurrent tripping in
the normal operating load range, find the R

BSOC

resistor

from Equation 1 with:

1. The maximum r

at the highest junction

DS(ON)

temperature

2. The minimum I

3. Determine I
is the output inductor ripple current.

ΔI

PEAK

from the specification table

BSOC

for I

PEAK

> I

OUT(MAX)

ΔI()

----------

+ , where

2

For an equation for the ripple current, see “Output Inductor
Selection” on page 13.

The range of allowable voltages detected (2*I

BSOC*RBSOC

is 0mV to 475mV; but the practical range for typical

INTERNAL SOFT-START RAMP

V

OUT

6.8ms

6.8ms

t0

FIGURE 5. OVERCURRENT RETRY OPERATION

t1

t1

6.8ms

0ms TO 6.8m

t2

t2

Figure 5 shows the output response during a retry of an
output shorted to GND. At time t

, the output has been

0

turned off, due to sensing an overcurrent condition. There
are two internal soft-start delay cycles (t

and t2) to allow the

1

MOSFETs to cool down, to keep the average power
dissipation in retry at an acceptable level. At time t

, the

2

output starts a normal soft-start cycle, and the output tries to
ramp. If the short is still applied, and the current reaches the

)

BSOC trip point any time during soft-start ramp period, the
output will shut off and return to time t

for another delay

0

8

FN6306.4

April 20, 2007

ISL8105, ISL8105A

cycle. The retry period is thus two dummy soft-start cycles
plus one variable one (which depends on how long it takes to
trip the sensor each time). Figure 5 shows an example
where the output gets about half-way up before shutting
down; therefore, the retry (or hiccup) time will be around
17ms. The minimum should be nominally 13.6ms and the
maximum 20.4ms. If the short condition is finally removed,
the output should ramp up normally on the next t

cycle.

2

Starting up into a shorted load looks the same as a retry into
that same shorted load. In both cases, OCP is always
enabled during soft-start; once it trips, it will go into retry
(hiccup) mode. The retry cycle will always have two dummy
time-outs, plus whatever fraction of the real soft-start time
passes before the detection and shutoff; at that point, the
logic immediately starts a new two dummy cycle time-out.

Output Voltage Selection

The output voltage can be programmed to any level between
the 0.6V internal reference, up to the V

supply. The

BIAS

ISL8105 can run at near 100% duty cycle at zero load, but
the r

of the top-side MOSFET will effectively limit it to

DS(ON)

something less as the load current increases. In addition, the
OCP (if enabled) will also limit the maximum effective duty
cycle.

An external resistor divider is used to scale the output
voltage relative to the internal reference voltage, and feed it
back to the inverting input of the error amp. See “Typical
Application Diagram” on page 2 for more detail; R
upper resistor; R

OFFSET

lower one. The recommended value for R
(±1% for accuracy) and then R
to the equation below. Since R

(shortened to R0 below) is the

is 1kΩ to 5kΩ

1
OFFSET
1

is chosen according

is part of the compensation

is the

1

circuit (see “Feedback Compensation” on page 11), it is
often easier to change R

OFFSET

to change the output
voltage; that way the compensation calculations do not need
to be repeated. If V

= 0.6V, then R

OUT

OFFSET

can be left

open. Output voltages less than 0.6V are not available.

+()

V

R

OUT

=

0

0.6V

•=

R10.6V•

----------------------------------

V

0.6V–

OUT

R

1R0

------------------------- -

R

0

(EQ. 2)

(EQ. 3)

Input Voltage Considerations

The “Typical Application Diagram” on page 2 shows a
standard configuration where V
12V (±20%); in each case, the gate drivers use the V
voltage for BGATE and BOOT/TGATE. In addition, V
allowed to work anywhere from 6.5V up to the 14.4V
maximum. The V

NOT

allowed for long-term reliability reasons, but

range between 5.5V and 6.5V is

BIAS

transitions through it to voltages above 6.5V are acceptable.
There is an internal 5V regulator for bias; it turns on between

5.5 and 6.5V . Some of the delay after POR is there to allow a

is either 5V (±10%) or

BIAS

BIAS

BIAS

is

typical power supply to ramp up past 6.5V before the
soft-start ramps begins. This prevents a disturbance on the
output, due to the internal regulator turning on or off. If the
transition is slow (not a step change), the disturbance should
be minimal. So while the recommendation is to not have the
output enabled during the transition through this region, it
may be acceptable. The user should monitor the output for
their application to see if there is any problem.

The V
as V
sources, such as outputs of other regulators. If V
powers up first, and the V

to the top-side MOSFET can share the same supply

IN

but can also run off a separate supply or other

BIAS

is not present by the time the

IN

BIAS

initialization is done, then the soft-start will not be able to
ramp the output, and the output will later follow part of the
V

ramp when it is applied. If this is not desired, then

IN

change the sequencing of the supplies, or use the
COMP/EN pin to disable V

until both supplies are ready.

OUT

Figure 6 shows a simple sequencer for this situation. If
V

powers up first, Q1 will be off, and R3 pulling to V

BIAS

will turn Q
V

turns on, the resistor divider R1 and R2 determines

IN

when Q
shut-down. If V
off; so the ISL8105 will start-up as soon as V
The V

on, keeping the ISL8105 in shut-down. When

2

turns on, which will turn off Q2 and release the

1

DISABLE

powers up first, Q1 will be on, turning Q2

IN

BIAS

trip point is 0.4V nominal, so a wide variety of

BIAS

comes up.

NFET's or NPN's or even some logic IC's can be used as Q1
or Q

; but Q2 must be low leakage when off (open-drain or

2

open-collector) so as not to interfere with the COMP output.
Q

should also be placed near the COMP/EN pin.

2

V

V

IN

BIAS

R

R

1

R

2

FIGURE 6. SEQUENCER CIRCUIT

The V

range can be as low as ~1V (for V

IN

0.6V reference). It can be as high as 20V (for V
below V

). There are some restrictions for running high VIN

IN

3

Q

1

TO COMP/EN

Q

2

as low as the

OUT

OUT

just

voltage.
The first consideration for high V

voltage of 36V. The V

(as seen on LX) + V

IN

is the maximum BOOT

IN

BIAS

(boot
voltage - the diode drop) + any ringing (or other transients)
on the BOOT pin must be less than 36V. If V
limits V

The second consideration for high V
(BOOT - V
BOOT = V

+ ringing to 16V.

BIAS

) voltage; this must be less than 24V. Since

BIAS

+ V

IN

BIAS

is the maximum

IN

+ ringing, that reduces to (VIN + ringing)

is 20V, that

IN

must be <24V. So based on typical circuits, a 20V maximum
V

is a good starting assumption; the user should verify the

IN

ringing in their particular application.

9

FN6306.4

April 20, 2007

ISL8105, ISL8105A

Another consideration for high VIN is duty cycle. Very low
duty cycles (such as 20V in to 1.0V out, for 5% duty cycle)
require component selection compatible with that choice
(such as low r

bottom-side MOSFET, and a good LC

DS(ON)

output filter). At the other extreme (for example, 20V in to
12V out), the top-side MOSFET needs to be low r

DS(ON)

. In
addition, if the duty cycle gets too high, it can affect the
overcurrent sample time. In all cases, the input and output
capacitors and both MOSFETs must be rated for the
voltages present.

Switching Frequency

The switching frequency is either a fixed 300kHz or 600kHz,
depending on the part number chosen (ISL8105 is 300kHz;
ISL8105A is 600kHz; the generic name “ISL8105” may apply
to either in the rest of this document, except when choosing
the frequency). However, all of the other timing mentioned
(POR delay, OCP sample, soft-start, etc.) is independent of
the clock frequency (unless otherwise noted).

BOOT Refresh

In the event that the TGATE is on for an extended period of
time, the charge on the boot capacitor can start to sag,
raising the r

of the top-side MOSFET. The ISL8105

DS(ON)

has a circuit that detects a long TGATE on-time (nominal
100µs), and forces the BGATE to go higher for one clock
cycle, which will allow the boot capacitor some time to
recharge. Separately, the OCP circuit has a BGATE pulse
stretcher (to be sure the sample time is long enough), which
can also help refresh the boot. But if OCP is disabled (no
current sense resistor), the regular boot refresh circuit will
still be active.

Current Sinking

The ISL8105 incorporates a MOSFET shoot-through
protection method which allows a converter to sink current
as well as source current. Care should be exercised when
designing a converter with the ISL8105 when it is known that
the converter may sink current.

When the converter is sinking current, it is behaving as a
boost converter that is regulating its input voltage. This
means that the converter is boosting current into the V
If there is nowhere for this current to go, such as to other
distributed loads on the V

rail, through a voltage limiting

IN

protection device, or other methods, the capacitance on the
V

bus will absorb the current. This situation will allow

IN

voltage level of the V

rail (also LX) to increase. If the

IN

voltage level of the LX is increased to a level that exceeds
the maximum voltage rating of the ISL8105, then the IC will
experience an irreversible failure and the converter will no
longer be operational. Ensuring that there is a path for the
current to follow other than the capacitance on the rail will
prevent this failure mode.

IN

rail.

Application Guidelines

Layout Considerations

As in any high-frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.

V

IN

ISL8105

TGATE

LX

BGATE

PGND

FIGURE 7. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

Figure 7 shows the critical power components of the
converter. To minimize the voltage overshoot/undershoot,
the interconnecting wires indicated by heavy lines should be
part of ground or power plane in a printed circuit board. The
components shown in Figure 8 should be located as close
together as possible. Please note that the capacitors C
and C

each represent numerous physical capacitors.

O

Locate the ISL8105 within three inches of the MOSFETs, Q
and Q

. The circuit traces for the MOSFETs’ gate and

2

source connections from the ISL8105 must be sized to
handle up to 1A peak current.

Proper grounding of the IC is important for correct operation
in noisy environments. The GND pin should be connected to
a large copper fill under the IC which is subsequently
connected to board ground at a quiet location on the board,
typically found at an input or output bulk (electrolytic)
capacitor.

Q1

Q2

RETURN

L

O

V

OUT

C

IN

C

O

IN

LOAD

1

10

FN6306.4

April 20, 2007

BSOC

R

ISL8105

BGATE/BSOC

GND

GND

BOOT

C

BOOT

LX

+V

V

BIAS

BIAS

C

VBIAS

Q1

+V

Q2

ISL8105, ISL8105A

C

E/A

2

C

R

C

2

1

-

+

VREF

R

FB

3

3

R

1

IN

L

O

C

V

OUT

COMP

O

LOAD

FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

Figure 8 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Locate the resistor,
R

, close to the BGATE/BSOC pin as the internal BSOC

BSOC

current source is only 21.5µA. Minimize the loop from any
pulldown transistor connected to COMP/EN pin to reduce
antenna effect. Provide local decoupling between VBIAS
and GND pins as described earlier. Locate the capacitor,
C

, as close as practical to the BOOT and LX pins. All

BOOT

components used for feedback compensation (not shown)
should be located as close to the IC as practical.

Feedback Compensation

This section highlights the design considerations for a
voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
network is recommended (see Figure 9).

Figure 9 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable to the
ISL8105 circuit. The output voltage (V
the reference voltage, V

, level. The error amplifier output

REF

(COMP pin voltage) is compared with the oscillator (OSC)
triangle wave to provide a pulse-width modulated wave with
an amplitude of V

at the LX node. The PWM wave is

IN

smoothed by the output filter (L a nd C). The ou tput filter
capacitor bank’s equivalent series resistance is represented
by the series resistor ESR.

) is regulated to

OUT

V

OUT

L

DCR

C

ESR

PWM

CIRCUIT

OSCILLATOR

V

OSC

HALF-BRIDGE

DRIVE

TGATE

LX

BGATE

EXTERNAL CIRCUITISL8105

V

IN

FIGURE 9. VOLT AGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

The modulator transfer function is the small-signal transfer
function of V
gain, given by d

OUT/VCOMP

MAXVIN/VOSC

with a double pole break frequency at F

. This function is dominated by a DC

, and shaped by the output filter,

and a zero at FCE.

LC

For the purpose of this analysis, C and ESR represent the total
output capacitance and its equivalent series resistance.

FLC

---------------------------

=

2π LC⋅⋅

1

FCE

---------------------------------

=

2π C ESR⋅⋅

1

(EQ. 4)

The compensation network consists of the error amplifier
(internal to the ISL8105) and the external R

to R3, C1 to C3

1

components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F

; typically 0.1 to 0.3 of fSW) and adequate phase

0

margin (better than +45°). Phase margin is the difference
between the closed loop phase at F

and +180°. The

0dB

equations that follow relate the compensation network’s poles,
zeros and gain to the components (R
C

) in Figure 9. Use the following guidelines for locating the

3

, R2, R3, C1, C2, and

1

poles and zeros of the compensation network:

11

1. Select a value for R
value for R

for desired converter bandwidth (F0). If

2

(1kΩ to 10kΩ, typically). Calculate

1

setting the output voltage to be equal to the reference set
voltage as shown in Figure 9, the design procedure can
be followed as presented.

V

⋅⋅

OSCR1F0

---------------------------------------------

R

=

2

d

⋅⋅

MAXVINFLC

April 20, 2007

(EQ. 5)

FN6306.4

)

ISL8105, ISL8105A

2. Calculate C1 such that FZ1 is placed at a fraction of the FLC,
at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F

, the lower the FZ1

CE/FLC

frequency (to maximize phase boost at FLC).

1

2π R

3. Calculate C

--------------------------------------------------------

=

C

2

2π R2C1FCE1–⋅⋅⋅

4. Calculate R

0.5 F

⋅⋅ ⋅

2

LC

such that FP1 is placed at FCE.

2

C

1

such that FZ2 is placed at FLC. Calculate C3

3

(EQ. 6)

(EQ. 7)

1

-----------------------------------------------

C

=

such that FP2 is placed below fSW (typically, 0.5 to 1.0
times f

). fSW represents the regulator’s switching

SW

frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of FP2 lower in
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant
duty cycle jitter.

R

1

--------------------

R

=

3

f

SW

---------- -

F

LC

-----------------------------------------------

=

C

3

2π R

1–

1

0.7 f

⋅⋅ ⋅

3

SW

(EQ. 8)

It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
compensation (G

d

----------------------------- -

f()

G

MOD

1sf() R

G

FB

G

CL

----------------------------------------------------

f()

sf() R

-------------------------------------------------------------------------------------------------------------------------

f() G

MOD

) and closed-loop response (GCL):

FB

⋅

MAXVIN

V

OSC

-----------------------------------------------------------------------------------------------------------

⋅=

1sf() ESR DCR+()C⋅⋅s

⋅⋅+

2C1

+()⋅⋅

1C1C2

1sf() R

1sf() R

⋅⋅+()1sf() R

3C3

f() GFBf()⋅=

1sf() ESR C⋅⋅+

⋅=

+()C

⋅⋅+

1R3

⎛⎞

⋅

⎜⎟
⎝⎠

where s f(), 2π fj⋅⋅=

), feedback

MOD

3

C1C2⋅

⎛⎞

---------------------

⋅⋅+

⎜⎟

2

C

⎝⎠

1C2

2

f() LC⋅⋅++

+

(EQ. 9

COMPENSATION BREAK FREQUENCY EQUATIONS

------------------------------ -

F

=

Z1

2π R

-------------------------------------------------

=

F

Z2

2π R

1

⋅⋅

2C1

1

+()C

⋅⋅

1R3

F

F

3

P1

P2

=

=

1

---------------------------------------------

2π R

------------------------------ -

2π R

C1C2⋅

---------------------

⋅⋅

2

C

1

⋅⋅

3C3

+

1C2

(EQ. 10)

Figure 10 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain, G

against the capabilities of the error

P2

, is constructed on the

CL

log-log graph of Figure 10 by adding the modulator gain,
G

(in dB), to the feedback compensation gain, GFB (in

MOD

dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.

F

Z1

GAIN

R2

⎛⎞

------- -

log

20

⎝⎠

R1

0

LOG

LOG

F

Z2

f

LCfCE

F

P1

20

f

0

FIGURE 10. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

MODULATOR GAIN

COMPENSATION GAIN

CLOSED LOOP GAIN

OPEN LOOP E/A GAIN

F

P2

d

⋅

V

MAX

V

OSC

G

MOD

IN

G

G

CL

FREQUENCY

---------------------------------log

FB

A stable control loop has a gain crossing with close to a

-20dB/decade slope and a phase margin greater than +45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the switching frequency, f

SW

.

12

FN6306.4

April 20, 2007

ISL8105, ISL8105A

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.

Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.

High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the ma nu facturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1.0mF
ceramic capacitors in the 1206 surface-mount package.
Follow on specifications have only increased the number
and quality of required ceramic decoupling capacitors.

Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transi ent. An
aluminum electrolytic capacitor's ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the equiva lent series i nduct ance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by Equation 11:

Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.

One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL8105 will provide either 0% or 100% duty cycle in response
to a load transient. The response time is the time required to
slew the inductor current from an initial current value to the
transient current level. During this interval the difference
between the inductor current and the transient current level
must be supplied by the output capacitor. Minimizing the
response time can minimize the output capacitance required.

The response time to a transient is different for the
application of load and the removal of load. Equation 12
gives the approximate response time interval for application
and removal of a transient load:

LOI

×

-------------------------------

=t

V

OUT

TRAN

(EQ. 12)

RISE

LOI

×

------------------------------- -

=

–

V

INVOUT

TRAN

t

FALL

where:
I

is the transient load current step

TRAN

t

is the response time to the application of load

RISE

t

is the response time to the removal of load

FALL

With a lower input source such as 1.8V or 3.3V, the worst
case response time can be either at the application or
removal of load and dependent upon the output voltage
setting. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the volt age
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacito rs
to supply the current needed each time Q
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q

and the source of Q2.

1

The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement

turns on. Place the

1

ΔI =

- V

V

IN

OUT

--------------------------------

FS x L

•

V

OUT

--------------- -

V

IN

13

ΔV

= ΔI x ESR

OUT

(EQ. 11)

FN6306.4

April 20, 2007

ISL8105, ISL8105A

0.60

0.50

0.40

0.30

ICM

K

0.20

0.10

0.00
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

DUTY CYCLE (D)

FIGURE 11. INPUT-CAPACITOR CURRENT MULTIPLIER FOR

SINGLE-PHASE BUCK CONVERTER

0.25Io

for the input capacitor of a buck regulator is approximately
as shown in Equation 13.

2

--------

12

IΔ

D+=

D

=

I

IN RMS,

IN RMS,

OR

2

I

DD2–()

O

K

•=

ICMIO

For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo
MV-GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series, available from
AVX, and the 593D, available series from Sprague, are both
surge current tested.

MOSFET Selection/Considerations

The ISL8105 requires 2 N-Channel power MOSFETs. These
should be selected based upon r
requirements, and thermal management requirements.

In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components: conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the top and the bottom-side MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor. The switching losses seen when
sourcing current will be different from the switching losses
seen when sinking current. When sourcing current, the
top-side MOSFET realizes most of the switching losses. The
bottom-side switch realizes most of the switching losses
when the converter is sinking current (see Equation 14).
These equations assume linear voltage current transitions

DS(ON)

, gate supply

ΔI = 0Io

V

O

----------

VIN

0.5Io

(EQ. 13)

and do not adequately model power loss due to the reverse
recovery of the upper and lower MOSFET’s body diode. The
gate-charge losses are dissipated by the ISL8105 and do not
heat the MOSFETs. However, large gate charge increases
the switching interval, t

, which increases the MOSFET

SW

switching losses. Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature
by calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.

Losses while Sourcing Current

1

1

-- -

P

P

TOP

TOP

P

BOTTOM

Io2r

× D×

Io2r

× D×

= Io2 x r

DS ON()

DS ON()

DS(ON)

-- -

2

2

x (1 - D)

× t

× tSW×+=

Io⋅ V

Io⋅ V

IN

IN

××+=

SWfS

Losses while Sinking Current

= Io2 x r

P

TOP

P

BOTTOM

DS(ON)

Io2r

× 1D–()×

x D

DS ON()

1

-- -

2

× t

Io⋅ V

IN

××+=

SWfS

(EQ. 14)

Where:
D is the duty cycle = V
t

is the combined switch ON and OFF time, and

SW

f

is the switching frequency.

S

OUT/VIN

When operating with a 12V power supply for V

,

(or down

BIAS

to a minimum supply voltage of 6.5V), a wide variety of
NMOSFETs can be used. Check the absolute maximum
V

rating for both MOSFETs; it needs to be above the

GS

highest V
means a 20V V
30V V

DS

voltage allowed in the system; that usually

BIAS

rating (which typically correlates with a

GS

maximum rating). Low threshold transistors
(around 1V or below) are not recommended for the reasons
explained in the next paragraph.

For 5V-only operation, given the reduced available gate bias
voltage (5V), logic-level transistors should be used for both
N-MOSFETs. Look for r

ratings at 4.5V. Caution

DS(ON)

should be exercised with devices exhibiting very low
V

characteristics. The shoot-through protection

GS(ON)

present aboard the ISL8105 may be circumvented by these
MOSFETs if they have large parasitic impedances and/or
capacitances that would inhibit the gate of the MOSFET from
being discharged below its threshold level before the
complementary MOSFET is turned on. Also avoid MOSFET s
with excessive switching times; the circuitry is expecting
transitions to occur in under 50ns or so.

Bootstrap Considerations

Figure 12 shows the top-side gate drive (BOOT pin) supplied
by a bootstrap circuit from V
C

, develops a floating supply voltage referenced to the

BOOT

LX pin. The supply is refreshed to a voltage of V
the boot diode drop (V

) each time the lower MOSFET, Q2,

D

. The boot capacitor,

BIAS

BIAS

less

14

FN6306.4

April 20, 2007

ISL8105, ISL8105A

turns on. Check that the voltage rating of the capacitor is
above the maximum V

voltage in the system. A 16V

BIAS

rating should be sufficient for a 12V system. A value of 0.1µF
is typical for many systems driving single MOSFETs.

+V

BIAS

+

V

D

-

BOOT

ISL8105

TGATE

LX

+V

BIAS

-

+

GND

FIGURE 12. UPPER GATE DRIVE - BOOTSTRAP OPTION

BGATE

+1V TO +12V

C

BOOT

Q1

Q2

V

G-S

NOTE:
V

G-S

≈ V

≈ V

BIAS

BIAS

- V

If V

is 12V, but VIN is lower (such as 5V), then another

BIAS

option is to connect the BOOT pin to 12V and remove the
BOOT cap (although, you may want to add a local cap from
BOOT to GND). This will make the TGATE V

voltage

GS

equal to (12V - 5V = 7V). That should be high enough to
drive most MOSFETs, and low enough to improve the
efficiency slightly . Do NOT
to get the same effect by driving BOOT through V

leave the BOOT pin open, and try

and

BIAS

the internal diode; this path is not designed for the high
current pulses that will result.

D

For low V

voltage applications where efficiency is very

BIAS

important, an external BOOT diode (in parallel with the
internal one) may be considered. The external diode drop
has to be lower than the internal one. The resulting higher
V

of the top-side FET will lower its r

G-S

DS(ON)

. The modest
gain in efficiency should be balanced against the extra cost
and area of the external diode.

For information on the Application circuit, including a
complete Bill-of-Materials and circuit board description, can
be found in Application Note AN1258.

15

FN6306.4

April 20, 2007

ISL8105, ISL8105A

Dual Flat No-Lead Plastic Package (DFN)

(DAT UM B )

6

INDEX
AREA

(DATUM A)

NX (b)

5

SECTION "C-C"

6

INDEX

AREA

SEATING

PLANE

NX L

8

A

C

D

TOP

VIEW

SIDE VIEW

D2

D2/2

12

N

N-1

e
(Nd-1)Xe

REF .

BOTTOM VIEW

(A1)

2X

A3

E2/2

NX b

5

C

L

e

CC

FOR ODD TERMINAL/SIDE

87

0.10

ABC0.10

2X

0.10

E

//

A

NX k

E2

M

9

TERMINAL TIP

0.10

0.08

L

CB

C

BAC

L10.3x3C

10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

A 0.85 0.90 0.95 ­A1 - - 0.05 ­A3 0.20 REF -

b 0.20 0.25 0.30 5, 8

D 3.00 BSC ­D2 2.33 2.38 2.43 7, 8

E 3.00 BSC ­E2 1.59 1.64 1.69 7, 8

C

e 0.50 BSC ­k0.20- - ­L 0.35 0.40 0.45 8

N102
Nd 5 3

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identi fier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

9. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.

NOTESMIN NOMINAL MAX

Rev. 1 4/06

16

FN6306.4

April 20, 2007

ISL8105, ISL8105A

Small Outline Plastic Packages (SOIC)

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

A1

C

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

17

FN6306.4

April 20, 2007