intersil ISL8105, ISL8105A DATA SHEET

ISL8105, ISL8105A

Data Sheet April 20, 2007 FN6306.4

+5V or +12V Single-Phase Synchronous Buck Converter PWM Controller with Integrated MOSFET Gate Drivers

The ISL8105 is a simple single-phase PWM controller for a synchronous buck converter. It operates from +5V or +12V bias supply voltage. With integrated linear regulator, boot diode, and N-Channel MOSFET gate drivers, the ISL8105 reduces external component count and board space requirements. These make the IC suitable for a wide range of applications.

Utilizing voltage-mode control, the output voltage can be precisely regulated to as low as 0.6V. The 0.6V internal reference features a maximum tolerance of ±1.0% over the commercial temperature range, and ±1.5% over the industrial temperature range. Two fixed oscillator frequency versions are available; 300kHz (ISL8105 for high efficiency applications) and 600kHz (ISL8105A for fast transient applications).

The ISL8105 features the capability of safe start-up with pre-biased load. It also provides overcurrent protection by monitoring the ON-resistance of the bottom-side MOSFET to inhibit PWM operation appropriately. During start-up interval, the resistor connected to BGATE/BSOC pin is employed to program overcurrent protection condition. This approach simplifies the implementation and does not deteriorate converter efficiency.

Pinouts

ISL8105

(10 LD 3X3 DFN)

TOP VIEW

BOOT

TGATE

N/C

GND

BGATE/BSOC

1 2 3 4 5

GND

ISL8105

(8 LD SOIC)

TOP VIEW

9 8 7 6

LX COMP/EN

FB N/C VBIAS

Features

• Operates from +5V or +12V Bias Supply Voltage

- 1.0V to 12V Input Voltage Range (up to 20V possible with restrictions; see Input Voltage Considerations)

- 0.6V to VIN Output Voltage Range

• 0.6V Internal Reference Voltage

- ±1.0% Tolerance Over the Commercial Temperature Range (0°C to +70°C)

- ±1.5% Tolerance Over the Industrial T e mperature Range (-40°C to +85°C).

• Integrated MOSFET Gate Drivers that Operate from (+5V to +12V)

BIAS

- Bootstrapped High-side Gate Driver with Integrated Boot Diode

- Drives N-Channel MOSFETs

• Simple Voltage-Mode PWM Control

- Traditional Dual Edge Modulation

• Fast Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Cycle

• Fixed Operating Frequency

- 300kHz for ISL8105

- 600kHz for ISL8105A

• Fixed Internal Soft-Start with Pre-biased Load Capability

• Lossless, Programmable Overcurrent Protection

- Uses Bottom-side MOSFET’s r

DS(ON)

• Enable/Disable Function Using COMP/EN Pin

• Output Current Sourcing and Sinking Currents

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• 5V or 12V DC/DC Regulators

• Industrial Power Systems

• Telecom and Datacom Applications

• Test and Measurement Instruments

• Distributed DC/DC Power Architecture

• Point of Load Modules

BOOT

TGATE

GND

BGATE/BSOC

COMP/EN

VBIAS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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ISL8105, ISL8105A

Ordering Information

PART NUMBER

(Note)

ISL8105CRZ* 5CRZ 300 0 to +70 10 Ld DFN L10.3X3C ISL8105IBZ* 8105 IBZ 300 -40 to +85 8 Ld SOIC M8.15 ISL8105IRZ* 5IRZ 300 -40 to +85 10 Ld DFN L10.3X3C ISL8105ACRZ* 05AZ 600 0 to +70 10 Ld DFN L10.3X3C ISL8105AIBZ* 8105 AIBZ 600 -40 to +85 8 Ld SOIC M8.15 ISL8105AIRZ* 5AIZ 600 -40 to +85 10 Ld DFN L10.3X3C ISL8105AEVAL1Z Evaluation Board *Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products em ploy special Pb -free mat erial set s; mol ding compou nds/die at tach m aterials a nd 100% matte tin plate termination finish, which are RoHS compliant and compatible with bot h SnPb and Pb-free soldering operat ions. Intersil Pb-free products are MSL cl assified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

SWITCHING

FREQUENCY (kHz)

TEMPERATURE

RANGE (°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

Typical Application Diagram

BOOT

TGATE

BOOT

BSOC

BULK

OUT

BIAS

+5V OR +12V

+1V TO +12V

DCPL

VBIAS

COMP/EN

ISL8105

BGATE/BSOC

GND

FN6306.4

April 20, 2007

Block Diagram

SAMPLE

AND

HOLD

COMPARATOR

POR AND

SOFT-START

5V INT.

INTERNAL

REGULATOR

VBIAS

BOOT

TGATE

21.5μA

20kΩ

PWM

BGATE/BSOC

5V INT.

20μA

COMP/EN

April 20, 2007

FN6306.4

0.4V

0.6V

ERROR

AMP

DIS

FIXED 300kHZ OR 600kHz

COMPARATOR

OSCILLATOR

INHIBIT

PWM

DIS

GATE

CONTROL

LOGIC

GND

BIAS

BGATE/BSOC

ISL8105, ISL8105A

Absolute Maximum Ratings Thermal Information

Bias Voltage, V Boot Voltage, V TGATE Voltage, V BGATE/BSOC Voltage, V LX Voltage, V Upper Driver Supply Voltage, V Clamp Voltage, V

FB, COMP/EN Voltage . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6V

. . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +15.0V

BIAS

. . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +36.0V

BOOT

. . . . . . . . . . . . . . . . . . . .GND - 0.3V to V

. . . . . . . . . . . . . VLX - 0.3V to V

TGATE

BOOT

BGATE/BSOC

- V

BIAS

. . . .GND - 0.3 to V

- VLX . . . . . . . . . . . . . . . . . .15V

BOOT

. . . . . . . . . . . . . . . . . . . . . . . . . . . .24V

BOOT

BIAS

BOOT

+ 0.3V

+ 0.3V + 0.3V

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150V

Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0kV

Recommended Operating Conditions

Bias Voltage, V Ambient Temperature Range

ISL8105C, ISL8105AC . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

ISL8105I, ISL8105AI. . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Junction Temperature Range. . . . . . . . . . . . . . . . . . . .-40°C to +125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.

1. θ

2. For θ

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

INPUT SUPPLY CURRENTS

Shutdown V

DISABLE

Disable Threshold (COMP/EN pin) V

OSCILLATOR

Nominal Frequency Range f

Ramp Amplitude (Note 3) ΔV

POWER-ON RESET

Rising V V

BIAS

POR Threshold Hysteresis V

BIAS

REFERENCE

Nominal Reference Voltage V Reference Voltage Tolerance ISL8105C (0°C to +70°C) -1.0 +1.0 %

ERROR AMPLIFIER

DC Gain (Note 3) GAIN Unity Gain-Bandwidth (Note 3) UGBW 20 MHz Slew Rate (Note 3) SR 9 V/μs

GATE DRIVERS

TGATE Source Resistance R

. . . . . . . +5V ±10%, +12V ±20%, or 6.5V to 14.4V

BIAS

, the “case temp” location is the center of the exposed metal pad on the package underside.

Supply Current I

BIAS

VBIAS_S

DISABLE

OSC

= 12V; Disabled 4 5.2 7 mA

BIAS

ISL8105C 270 300 330 kHz ISL8105I 240 300 330 kHz

OSC

ISL8105AC 540 600 660 kHz ISL8105AI 510 600 660 kHz

OSC

Threshold V

POR_R POR_H

REF

ISL8105I (-40°C to +85°C) -1.5 +1.5 %

TG-SRCh

= 14.5V, 50mA Source Current 3.0 Ω

BIAS

Thermal Resistance (Note 1) θ

(°C/W) θJC (°C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . 95 N/A

DFN Package (Note 2). . . . . . . . . . . . . 44 5.5

Maximum Junction Temperature

(Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C

(SOIC - Lead Tips Only)

0.375 0.4 0.425 V

1.5 V

P-P

3.9 4.1 4.3 V

0.30 0.35 0.40 mV

0.6 V

96 dB

FN6306.4

April 20, 2007

ISL8105, ISL8105A

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

TGATE Source Resistance R TGATE Sink Resistance R TGATE Sink Resistance R BGATE Source Resistance R BGATE Source Resistance R BGATE Sink Resistance R BGATE Sink Resistance R

OVERCURRENT PROTECTION (OCP)

BSOC Current Source I

NOTE:

3. Test conditions are guaranteed by design simulation.

TG-SRCl

TG-SNKh

TG-SNKl

BG-SRCh

BG-SRCl

BG-SNKh

BG-SNKl

BSOC

= 4.25V, 50mA Source Current 3.5 Ω

BIAS

= 14.5V, 50mA Source Current 2.7 Ω

BIAS

= 4.25V, 50mA Source Current 2.7 Ω

BIAS

= 14.5V, 50mA Source Current 2.4 Ω

BIAS

= 4.25V, 50mA Source Current 2.75 Ω

BIAS

= 14.5V, 50mA Source Current 2.0 Ω

BIAS

= 4.25V, 50mA Source Current 2.1 Ω

BIAS

ISL8105C; BGATE/BSOC Disabled 19.5 21.5 23.5 µA ISL8105I; BGATE/BSOC Disabled 18.0 21.5 23.5 µA

Functional Pin Description (SOIC, DFN)

BOOT (SOIC Pin 1, DFN Pin 1)

This pin provides ground referenced bias voltage to the top-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive an N-Channel MOSFET (equal to V

minus the on-chip BOOT diode voltage drop), with

BIAS

respect to LX.

TGATE (SOIC Pin 2, DFN Pin 2)

Connect this pin to the gate of top-side MOSFET; it provides the PWM-controlled gate drive. It is also monitored by the adaptive shoot-through protection circuitry to determine when the top-side MOSFET has turned off.

GND (SOIC Pin 3, DFN Pin 4)

This pin represents the signal and power ground for the IC. Tie this pin to the ground island/plane through the lowest impedance connection available.

BGATE/BSOC (SOIC Pin 4, DFN Pin 5)

Connect this pin to the gate of the bottom-side MOSFET; it provides the PWM-controlled gate drive (from V pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off.

During a short period of time following Power-On Reset (POR) or shut-down release, this pin is also used to determine the current limit threshold of the converter. Connect a resistor (R

) from this pin to GND. See

BSOC

“Overcurrent Protection (OCP)” on page 7 for equations. An overcurrent trip cycles the soft-sta rt fu nct i on , after two dummy soft-start time-outs. Some of the text describing the BGATE function may leave off the BSOC part of the name, when it is not relevant to the discussion.

BIAS

). This

VBIAS (SOIC Pin 5, DFN Pin 6)

This pin provides the bias supply for the ISL8105, as well as the bottom-side MOSFET's gate and the BOOT voltage for the top-side MOSFET's gate. An internal 5V regulator will supply bias if V and BOOT will still be sourced by V

rises above 6.5V (but the BGATE/BSOC

BIAS

). Connect a well

BIAS

decoupled +5V or +12V supply to this pin.

FB (SOIC Pin 6, DFN Pin 8)

This pin is the inverting input of the internal error amplifier. Use FB, in combination with the COMP/EN pin, to compensate the voltage-control feedback loop of the converter. A resistor divider from the output to GND is used to set the regulation voltage.

COMP/EN (SOIC Pin 7, DFN Pin 9)

This is a multiplexed pin. During soft-start and normal converter operation, this pin represents the output of the error amplifier. Use COMP/EN, in combination with the FB pin, to compensate the voltage-control feedback loop of the converter.

Pulling COMP/EN low (V

DISABLE

= 0.4V nominal) will disable (shut-down) the controller, which causes the oscillator to stop, the BGATE and TGATE outputs to be held low, and the soft-start circuitry to re-arm. The external pull-down device will initially need to overcome maximum of 5mA of COMP/EN output current. However, once the IC is disabled, the COMP output will also be disabled, so only a 20µA current source will continue to draw current.

When the pull-down device is released, the COMP/EN pin will start to rise at a rate determined by the 20µA charging up the capacitance on the COMP/EN pin. When the COMP/EN pin rises above the V

DISABLE

trip point, the ISL8105 will

begin a new initialization and soft-start cycle.

LX (SOIC Pin 8, DFN Pin 10)

Connect this pin to the source of the top-side MOSFET and the drain of the bottom-side MOSFET. It is used as the sink

FN6306.4

April 20, 2007

ISL8105, ISL8105A

for the TGATE driver and to monitor the voltage drop across the bottom-side MOSFET for overcurrent protection. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the top-side MOSFET has turned off.

N/C (DFN Only; Pin3, Pin 7)

These two pins in the DFN package are No Connect.

Functional Description

Initialization (POR and OCP Sampling)

Figure 1 shows a start-up waveform of ISL8105. The Power-ON-Reset (POR) function continually monitors the bias voltage at the VBIAS pin. Once the rising POR threshold is exceeded 4V (V initiates the Overcurrent Protection (OCP) sample and hold operation (while COMP/EN is ~1V). When the sampling is complete, V

~4V POR

begins the soft-start ramp.

OUT

nominal), the POR function

POR

BIAS

OUT

trip point. At t2, there is a variable time period for the OCP sample and hold operation (0ms to 3.4ms nominal; the longer time occurs with the higher overcurrent setting). The sample and hold uses a digital counter and DAC to save the voltage, so the stored value does not degrade, for as long as the V

BIAS

is above V

. See “Overcurrent Protection

POR

(OCP)” on page 7 for more details on the equations and variables. Upon the completion of sample and hold at t

, the

soft-start operation is initiated, and the output voltage ramps up between t

and t5.

COMP/EN

BGATE/BSOC

3.4ms

3.4ms t2 t3

BGATE STARTS SWITCHING

0ms to 3.4ms

OUT

COMP/EN

FIGURE 1. POR AND SOFT-START OPERATION

If the COMP/EN pin is held low during power-up, the initialization will be delayed until the COMP/EN is released and its voltage rises above the V

DISABLE

trip point.

Figure 2 shows a typical power-up sequence in more detail. The initialization starts at t V

, or the COMP/EN pin is released (after POR). The

POR

, when either V

rises above

BIAS

COMP/EN will be pulled up by an internal 20µA current source, but the timing will not begin until the COMP/EN exceeds the V

DISABLE

trip point (at t1). The external capacitance of the disabling device, as well as the compensation capacitors, will determine how quickly the 20µA current source will charge the COMP/EN pin. With typical values, it should add a small delay compared to the soft-start times. The COMP/EN will continue to ramp to ~1V.

From t

, there is a nominal 6.8ms delay, which allows the

VBIAS pin to exceed 6.5V (if rising up towards 12V), so that the internal bias regulator can turn on cleanly. At the same time, the BGATE/BSOC pin is initialized by disabling the BGATE driver and drawing BSOC (nominal 21.5µA) through R

. This sets up a voltage that will represent the BSOC

BSOC

FIGURE 2. BGATE/BSOC AND SOFT-START OPERATION

Soft-Start and Pre-Biased Outputs

Functionally, the soft-start internally ramps the reference on the non-inverting terminal of the error amp from 0V to 0.6V in a nominal 6.8ms. The output voltage will thus follow the ramp, from zero to final value, in the same 6.8ms (the actual ramp seen on the V due to some initialization timing, between t

The ramp is created digitally, so there will be 64 small discrete steps. There is no simple way to change this ramp rate externally, and it is the same for either frequency version of the IC (300kHz or 600kHz).

After an initialization period (t (COMP/EN pin) is enabled, and begins to regulate the converter's output voltage during soft-start. The oscillator's triangular waveform is compared to the ramping error amplifier voltage. This generates LX pulses of increasing width that charge the output capacitors. When the internally generated soft-start voltage exceeds the reference voltage (0.6V), the soft-start is complete and the output should be in regulation at the expected voltage. This method provides a rapid and controlled output voltage rise; there is no large inrush current charging the output capacitors. The entire start-up sequence from POR typically takes up to 17ms; up to 10.2ms for the delay and OCP sample and 6.8ms for the soft-start ramp.

will be less than the nominal time),

OUT

to t4), the error amplifier

and t4).

FN6306.4

April 20, 2007

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