High Performance 1A LDO
ISL80101
ISL80101
The ISL80101 ia a low-voltage, high-current, single
output LDO specified for 1A output current. This part
operates from input voltages of 2.2V to 6V and is capable
of providing output voltages of 0.8V to 5V on the
adjustable V
versions. Fixed output voltage options
OUT
available in 0.8V, 1.2V, 1.5V, 1.8V, 2.5V , 3.3V and 5V.
Other custom voltage options available upon request.
For applications that demand in-rush current less than
current limit or a longer delay for a valid V
OUT
, an
external capacitor on the soft-start pin provides
adjustment. A supply independent ENABLE signal allows
the part to be placed into a low quiescent current
shutdown mode. Sub-micron CMOS process is utilized for
this product family to deliver best in class analog
performance and overall value.
This CMOS LDO will consume significantly lower
quiescent current as a function of load over bipolar LDOs,
which translates into higher efficiency and the ability to
consider packages with smaller footprints. Quiescent
current is modestly compromised to enable leading class
fast load transient response and hence total AC
regulation band for an LDO in this category.
Applications*(see page 14)
• DSP, FPGA and µP Core Power Supplies
• Noise-Sensitive Instrumentation Systems
• Post Regulation of Switched Mode Power Supplies
• Industrial Systems
•Medical Equipment
• Telecommunications and Networking Equipment
•Servers
• Hard Disk Drives (HD/HDD)
Features
• 0.2% initial V
• Designed for 2.2V to 6V Input Supply
• Dropout Typically 130mV at 1A
• Fast Load Transient Response
• Rated Output Current Options of 1A
• Adjustable In-Rush Current Limiting
• Fixed and Adjustable V
• 58dB Typical PSRR
• Output Noise of 100µV
300kHz
•PG Feature
•1V Enable Input Threshold
• Short-Circuit Current Protection
• 1A Peak Reverse Current
• Over-Temperature Shutdown
• Any Cap Stable with Minimum 10µF Ceramic
• ±1.8% Guaranteed V
Temperature Range from -40°C to +125°C
• Available in a 10 Ld DFN Package and soon to follow
TO220-5, TO263-5 and SOT223-5
• Pb-Free (RoHS Compliant)
Accuracy
OUT
Options Available
OUT
between 300Hz to
RMS
Accuracy for Junction
OUT
Pin Configuration
December 21, 2009
FN6931.0
1
ISL80101
(10 LD 3X3 DFN)
TOP VIEW
VOUT
VOUT
SENSE/ADJ
1-888-INTERSIL or 1-888-468-3774
1
2
3
PG
4
GND
5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
All other trademarks mentioned are the property of their respective owners.
VIN
10
VIN
9
NC
8
ENABLE
7
SS
6
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009. All Rights Reserved.
ISL80101
Pin Descriptions
PIN
NUMBER PIN NAME DESCRIPTION
1, 2 VOUT Output voltage pin.
3SENSE/ADJRemote voltage sense for internally fixed V
4PGV
5GNDGND pin.
6 SS External cap controls the rate of the V
7ENABLE V
8 DNC Do not connect this pin to ground or supply. Leave floating.
9, 10 VIN Input supply pin.
in regulation signal. Logic low defines when V
OUT
if not used.
OUT
independent chip enable. TTL and CMOS compatible.
IN
options. ADJ pin for externally set V
OUT
is not in regulation. Pin should be grounded
OUT
ramp.
OUT
.
Ordering Information
VOUT
PART NUMBER
(Notes 4, 5) PART MARKING
ISL80101IRAJZ
(Note 1)
ISL80101IR08Z DZBB 0.8V -40 to +125 10 Ld 3x3 DFN L10.3x3
ISL80101IR08Z-T
(Note 2)
ISL80101IR12Z DZCB 1.2V -40 to +125 10 Ld 3x3 DFN L10.3x3
ISL80101IR12Z-T
(Note 2)
ISL80101IR15Z DZDB 1.5V -40 to +125 10 Ld 3x3 DFN L10.3x3
ISL80101IR15Z-T
(Note 2)
ISL80101IR18Z
(Note 1)
ISL80101IR25Z
(Note 1)
ISL80101IR33Z DZGB 3.3V -40 to +125 10 Ld 3x3 DFN L10.3x3
ISL80101IR33Z-T
(Note 2)
ISL80101IR50Z DZHB 5.0V -40 to +125 10 Ld 3x3 DFN L10.3x3
ISL80101IR50Z-T
(Note 2)
NOTES:
1. Add “-T” or “TK” for Tape and Reel. Please refer to TB347
2. Please refer to TB347
3. For other output voltages, contact Intersil Marketing.
4. These Intersil Pb-free plastic pac kaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 .
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL80101
see techbrief TB363
DZAB ADJ -40 to +125 10 Ld 3x3 DFN L10.3x3
DZBB 0.8V -40 to +125 10 Ld 3x3 DFN L10.3x3
DZCB 1.2V -40 to +125 10 Ld 3x3 DFN L10.3x3
DZDB 1.5V -40 to +125 10 Ld 3x3 DFN L10.3x3
DZEB 1.8V -40 to +125 10 Ld 3x3 DFN L10.3x3
DZFB 2.5V -40 to +125 10 Ld 3x3 DFN L10.3x3
DZGB 3.3V -40 to +125 10 Ld 3x3 DFN L10.3x3
DZHB 5.0V -40 to +125 10 Ld 3x3 DFN L10.3x3
for details on reel specifications.
.
VOLTAGE
(Note 3) TEMP RANGE (°C)
for details on reel specifications.
PACKAGE
(Pb-Free) PKG DWG. #
. For more information on MSL please
2
December 21, 2009
FN6931.0
ISL80101
Absolute Maximum Ratings Thermal Information
VIN relative to GND (Note 6). . . . . . . . . . . . -0.3V to +6.5V
VOUT relative to GND (Note 6) . . . . . . . . . . -0.3V to +6.5V
PG, ENABLE, SENSE/ADJ, SS
Relative to GND (Note 6) . . . . . . . . . . . . . -0.3V to +6.5V
Recommended Operating Conditions
(Notes 9, 10)
Junction Temperature Range (TJ) (Note 9) . -40°C to +125°C
VIN relative to GND . . . . . . . . . . . . . . . . . . . . . 2.2V to 6V
VOUT range. . . . . . . . . . . . . . . . . . . . . . . . . .800mV to 5V
PG, ENABLE, SENSE/ADJ, SS relative to GND . . . .0V to +6V
PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . .<10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
6. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
is measured in free air with the component mounted on a high effective th ermal conductivity test board with “direct attach”
7. θ
JA
features. See Tech Brief TB379.
8. For θ
9. Extended operation at these conditions may compromise reliability. Exceeding these limi ts will res ult in damage.
10. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current =
, the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Recommended operating conditions define limits where specifications are guaranteed.
lifetime average current.
Thermal Resistance . . . . . . . . . . . . . . . . . . .θJA (°C/W)θJC (°C/W)
10 Ld DFN Package (Notes 7, 8) . . 45 4
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Electrical Specifications Unless otherwise noted, V
Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to Applications section of the datasheet and Tech Brief TB379.
Boldface limits apply over the operating temperature range,
-40°C to +125°C.
PARAMETER SYMBOL TEST CONDITIONS
DC CHARACTERISTICS
DC Ouput Voltage Accuracy V
Feedback Pin
OUTVOUT
V
ADJ
(ADJ Option Only)
DC Input Line Regulation ΔV
DC Output Load Regulation ΔV
ΔI
ΔV
OUT
IN
OUT
OUT
/
/
Feedback Input Current V
Ground Pin Current I
Ground Pin Current in
Q
I
SHDN
Shutdown
Dropout Voltage (Note 12) V
Output Short Circuit Current
(1A Version)
Thermal Shutdown
Temperature
DO
OCP
TSD
Options: 0.8V, 1.2V, 1.5V and 1.8V
2.2V ≤ V
Options: 2.5V, 3.3V and 5.0V
V
OUT
V
OUT
2.2V ≤V
V
+ 0.5V < V
OUT
0A < I
LOAD
= 0.5V 0.01 1 µA
ADJ
I
= 0A, 2.2V < V
LOAD
= 1A, 2.2V < V
I
LOAD
< 3.6V; 0A < I
IN
+ 0.4V ≤ V
≤ 6V, 0A < I
IN
IN
< 1A, All voltage options -1 %
ENABLE Pin = 0.2V, V
I
= 1A, V
LOAD
V
= 0V, 2.2V < V
OUT
2.2V < V
OUT
< 6V 160 °C
IN
= V
IN
≤ 6V; 0A < I
IN
LOAD
OUT
LOAD
+ 0.4V, V
≤ 1A -1.8 0.2 1.8 %
LOAD
OUT
= 1.8V, C
(Note 11) TYP
IN
MIN
= C
= 10µF, TJ = +25°C.
OUT
MAX
(Note 11) UNITS
< 1A -1.8 0.2 1.8 %
< 1A 491 500 509 mV
< 5V 1 %
< 6V 3 5 mA
IN
< 6V 5 7 mA
IN
= 6V 0.2 12 µA
IN
= 2.5V 130 212 mV
< 6V 1.75 A
IN
3
December 21, 2009
FN6931.0
ISL80101
Electrical Specifications Unless otherwise noted, V
Applications must follow thermal guidelines of the package to determine worst case junction
IN
= V
OUT
+ 0.4V, V
OUT
= 1.8V, C
IN
= C
= 10µF, TJ = +25°C.
OUT
temperature. Please refer to Applications section of the datasheet and Tech Brief TB379.
Boldface limits apply over the operating temperature range,
-40°C to +125°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
Thermal Shutdown
TSDn
2.2V < V
< 6V 30 °C
IN
MIN
(Note 11) TYP
MAX
(Note 11) UNITS
Hysteresis (Rising Threshold)
AC CHARACTERISTICS
Input Supply Ripple
Rejection
Output Noise Voltage I
PSRR f = 1kHz, I
f = 120Hz, I
= 10mA, BW = 300Hz < f < 300kHz 100 µV
LOAD
= 1A; VIN = 2.2V 58 dB
LOAD
LOAD
= 1A; V
= 2.2V 72 dB
IN
RMS
ENABLE PIN CHARACTERISTICS
Turn-on Threshold 2.2V < V
Hysteresis
2.2V < V
(Rising Threshold)
Enable Pin Turn-on Delay C
Enable Pin Leakage Current V
OUT
= 6V, EN = 3V 1 µA
IN
< 6V 0.3 0.8 1 V
IN
+ 0.4V < 6V 10 80 200 mV
OUT
= 10µF, I
= 1A 100 µs
LOAD
ADJUSTABLE INRUSH CURRENT LIMIT CHARACTERISTICS
Current limit adjust I
I
CHG
VIN = 3.5V, EN = 0V, SS = 1V 0.5 1 1.3 mA
PD
-3.3 -2 -0.8 µA
PG PIN CHARACTERISTICS
PG Flag Threshold 75 85 92 %V
V
OUT
V
PG Flag Hysteresis 4%
OUT
PG Flag Low Voltage V
PG Flag Leakage Current V
= 2.5V, I
IN
= 6V, PG = 6V 1 µA
IN
= 500µA 100 mV
SINK
OUT
NOTES:
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
12. Dropout is defined by the difference in supply V
value.
and V
IN
when the supply produces a 2% drop in VOUT from its nominal
OUT
4
December 21, 2009
FN6931.0
Typical Application Diagrams
ISL80101
2.5V ± 10% 1.8V ± 1.8%
10µF
10k
(*NOTE 13)
9
10
7
6
V
IN
V
IN
ENABLE
SS
ISL80101
GN D
5
FIXED
V
V
SENSE/ADJ
OUT
OUT
PG
1
2
3
4
10µF
100k
FIGURE 1. FIXED TYPICAL APPLICATION DIAGRAM
2.5V ± 10%
10k
10µF
10
9
V
IN
V
IN
ISL80101
SE
NSE/ADJ
1
V
OUT
2
V
OUT
10µF
2.6k
1.8V ± 1.8%
100k
7
6
(*NOTE 13)
FIGURE 2. ADJUSTABLE TYPICAL APPLICATION DIAGRAM
NOTE:
13. Used when large bulk capacitance required on V
EN A B LE
SS
ADJUSTABLE
for application.
OUT
GND
5
PG
1k
4
5
December 21, 2009
FN6931.0
ISL80101
ISL80101 Schematic Block Diagram
VIN
SS
ENABLE
SS
LEVEL
SHIFT
REFERENCE
BIAS
-
+
Application Section
Input Voltage Requirements
Despite other output voltages offered, this family of LDOs
is optimized for a true 2.5V to 1.8V conversion where the
input supply can have a tolerance of as much as ±10%
for conditions noted in the “Electrical Specifications” table
on page 3. Minimum guaranteed input voltage is 2.2V.
However, due to the nature of an LDO, V
margin higher than the output voltage plus dropout at
the maximum rated current of the application if active
filtering (PSRR) is expected from V
IN
Dropout spec of this family of LDOs has been generously
specified in order to allow applications to design for a
level of efficiency that can accommodate the smaller
outline package for those applications that cannot
accommodate the profile of the TO220/263.
External Capacitor Requirements
GENERAL GUIDELINE
External capacitors are required for proper operation.
Careful attention must be paid to layout guidelines and
selection of capacitor type and value to ensure optimal
performance.
OUTPUT CAPACITOR
The required minimum output capacitor is 10µF X5R/X7R
to ensure stable operation. Additional capacitors of any
value in Ceramic, PO SCAP or Alum/Tantalum Electrolytic
types may be placed in parallel to improve PSRR at
higher frequencies and/or load transient AC output
voltage tolerances. This minimum capacitor must be
connected to V
traces no longer than 0.5cm.
and Ground pins of the LDO with PCB
OUT
must be some
IN
to V
OUT
. The
THERMAL
SHUTDOWN
+
OCL
POWER
PMOS
VOUT
SENSE
ADJ
PGOOD
GND
INPUT CAPACITOR
The minimum input capacitor required for proper
operation is 10µF having a ceramic dielectric. This
minimum capacitor must be connected to V
OUT
and
Ground pins of the LDO with PCB traces no longer than
0.5cm.
Thermal Fault Protection
In the event the die temperature exceeds typically
+160°C, then the output of the LDO will shut down until
the die temperature can cool down to typically +130°C.
The level of power combined with the thermal resistance
of the package (+45°C/W for DFN) will determine if the
junction temperature exceeds the thermal shutdown
temperature specified in the “Electrical Specifications”
table on page 3 (see thermal packaging guidelines).
Current Limit Protection
The ISL80101 LDO incorporates protection against
overcurrent due to any short or overload condition
applied to the output pin. The current limit circuit
performs as a constant current source when the output
current exceeds the current limit threshold noted in the
“Electrical Specifications” table on page 3. If the short or
overload condition is removed from V
output returns to normal voltage mode regulation. In the
event of an overload condition on the DFN package the
LDO will begin to cycle on and off due to the die
temperature exceeding thermal fault condition. The
TO220/263 package will tolerate higher levels of power
dissipation on the die which may never thermal cycle if
the heatsink of this larger package can keep the die
temperature below the specified typical thermal
shutdown temperature.
, then the
OUT
6
December 21, 2009
FN6931.0
ISL80101
Functional Description
Enable Operation
The Enable turn-on threshold is typically 0.8V with a
hysteresis of 80mV. The Enable pin doesn't have an
internal pull-up or pull-down resistor. As a result, this pin
must not be left floating. This pin must be tied to V
is not used. A pull-up resistor (typically 1k
Ω to 10kΩ) will
be required for applications that use open collector or
open drain outputs to control the Enable pin. The Enable
pin may be connected directly to V
for applications that
IN
are always on.
Soft-Start Operation
The soft-start circuit controls the rate at which the output
voltage comes up to reg ulation at power -up or com ing
out of a chip disable. A constant current charges an
external soft-start capacitor. The external capacitor
always gets discharged to 0V at start-up of after coming
out of a chip disable. The discharge rate is the RC time
constant of an internal resistance and C
function effectively limits the amount of in-rush current
below the programmed current limit during start-up or
an enable sequence to avoid an ov ercurrent fault
condition. This can be an issue for applications that
require large, external bulk capacitances on V
high levels of charging current can be seen for a
significant period of time. High in-rush currents can
cause V
V
OUT
C
SS
output voltage, C
output and I
C
SS
to drop below minimum which could cause
IN
to shutdown. Equation 3 can be used to calculate
for a desired in-rush current. Where V
is the total capacitance on the
OUT
INRUSH
V
OUTxCOUT
-----------------------------------------------------------
=
I
INRUSH
is the desired in-rush current.
x2μA )()
x0.5V
The following scope in Figure 3 captures the response for
the soft-start function.The output voltage is set to 1.8V.
. The soft-start
SS
OUT
OUT
IN
where
is the
(EQ. 1)
if it
FIGURE 4. IN-RUSH CURRENT WITH C
FIGURE 5. IN-RUSH CURRENT WITH C
Also
The rise time of the regulator output voltage for a given
C
= 1000µF, IN-RUSH CURRENT = 0.5A
OUT
C
= 1000µF, IN-RUSH CURRENT = 0.2A
OUT
= 15nF,
SS
= 33nF,
SS
CSS value can be calculated using Equation 2.
t
RAMP
CSSx0.5V
----------------------------
=
2μ A
(EQ. 2)
FIGURE 3. IN-RUSH CURRENT WITH NO CSS,
C
= 1000µF, IN-RUSH CURRENT = 1.8A
OUT
7
Power-Good Operation
The PGOOD circuit monitors V
condition when V
is below 85% of the nominal output
OUT
voltage. The PGOOD flag is an open-drain NMOS that can
sink 10mA during a fault condition. The PGOOD pin
requires an external pull up resistor which is typically
connected to the VOUT pin. The PGOOD pin should not
be pulled up to a voltage source greater than V
a fault condition, the PGOOD output is pulled low. The
PGOOD fault can be caused by the current limit fault or
low input voltage. The PGOOD does not function during
thermal shutdown and when the part is disabled.
and signals a fault
OUT
December 21, 2009
. During
IN
FN6931.0
ISL80101
Output Voltage Selection
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage. This
voltage is then fed back to the error amplifier. The output
voltage can be programmed to any level between 0.8V
and 5V. An external resistor divider , R
and R2, is used to
1
set the output voltage as shown in Equation 3. The
recommended value for R
is 500Ω to 1kΩ. R1 is then
2
chosen according to Equation 4:
R
⎛⎞
V
OUT
R
1R2
0.5V
V
OUT
⎛⎞
--------------- -
×=
⎝⎠
0.5V
1+
×=
⎜⎟
R
⎝⎠
2
1–
1
-------
(EQ. 3)
(EQ. 4)
Power Dissipation
The junction temperature must not exceed the range
specified in the Recommended Operating Conditions. The
power dissipation can be calculated by using Equation 5:
VINV
P
D
–()I
OUT
OUTVINIGND
×+×=
The maximum allowed junction temperature, T
and the maximum expected ambient temperature,
T
A(MAX)
will determine the maximum allowed junction
temperature rise (ΔTJ) as shown in Equation 6:
ΔT
JTJMAX()TAMAX()
–=
(EQ. 5)
J(MAX)
(EQ. 6)
To calculate the maximum ambient operating
temperature, use the junction-to-ambient thermal
resistance (θ
P
DMAX()TJMAX()TA
Substitute P
) for the DFN package with Equation 5:
JA
–()θ
⁄=
JA
for P
D
D(MAX)
and the maximum ambient
(EQ. 7)
operating temperature can be found by solving for TA
using Equation 8:
T
ATJMAXPDMAX()θJA
×–=
(EQ. 8)
Heatsinking The DFN Package
The DFN package uses the copper area on the PCB as a
heat-sink. The EPAD of this package must be soldered to
the copper plane (GND plane) for heat sinking. Figure 6
shows a curve for the θ
different copper area sizes.
46
44
42
40
, C/W
JA
38
θ
36
34
24681012141618202224
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
FIGURE 6. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB
WITH THERMAL VIAS θ
COPPER LAND AREA ON PCB
the DFN package for
JA of
JA
2
vs EPAD-MOUNT
8
December 21, 2009
FN6931.0
ISL80101
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, V
1.8
1.2
0.6
(%)
0
OUT
ΔV
-0.6
-1.2
-1.8
-50 -25 0 25 50 75 100 125 150
JUNCTION TEMPERATURE (°C)
FIGURE 7. OUTPUT VOLTAGE vs TEMPERATURE
= 1.8V, CIN = C
OUT
= 10µF, TJ = +25°C, IL = 0A.
OUT
2.0
1.8
1.6
1.4
1.2
+125°C
1.0
0.8
+25°C
0.6
OUTPUT VOLTAGE (V)
0.4
0.2
0
0246
-40°C
135
SUPPLY VOLTAGE (V)
FIGURE 8. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
1.8
1.2
(%)
OUT
DV
0.6
-0.6
-1.2
-1.8
0
0
+25°C
+125°C
0.25
OUTPUT CURRENT (mA)
-40°C
0.50 0.75 1.00
FIGURE 9. OUTPUT VOLTAGE vs OUTPUT CURRENT
3.50
3.25
3.00
2.75
2.50
2.25
2.00
GROUND CURRENT (mA)
1.75
1.50
0 0.25 0.50 0.75 1.00
+125°C
+25°C
OUTPUT CURRENT (A)
-40°C
FIGURE 11. GROUND CURRENT vs OUTPUT CURRENT
5
4
3
2
1
GROUND CURRENT (mA)
0
24
356
INPUT VOLTAGE (V)
FIGURE 10. GROUND CURRENT vs SUPPLY VOLTAGE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
GROUND CURRENT (µA)
0.5
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
VIN = 6V
TEMPERATURE (°C)
FIGURE 12. SHUTDOWN CURRENT vs TEMPERATURE
9
December 21, 2009
FN6931.0
ISL80101
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, V
200
190
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
DROPOUT VOLTAGE (mV)
30
20
10
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FIGURE 13. DROPOUT VOLTAGE vs TEMPERATURE
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
VOLTAGE (V)
0.45
0.40
0.35
0.30
-40 -25 -10 5 20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 15. ENABLE THRESHOLD VOLTAGE vs
TEMPERATURE
= 1.8V, CIN = C
OUT
V
= 2.5
OUT
= 10µF, TJ = +25°C, IL = 0A. (Continued)
OUT
200
190
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
DROPOUT VOLTAGE (mV)
20
10
0
0 0.2 0.4 0.6 0.8 1.0
OUTPUT CURRENT (A)
V
OUT
FIGURE 14. DROPOUT VOLTAGE vs OUTPUT CURRENT
FIGURE 16. POWER-UP (V
= 2.2V)
IN
= 2.5
FIGURE 17. POWER-DOWN (V
10
= 2.2V)
IN
FIGURE 18. ENABLE START-UP
December 21, 2009
FN6931.0
ISL80101
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, V
FIGURE 19. ENABLE SHUTDOWN
= 1.8V, CIN = C
OUT
= 10µF, TJ = +25°C, IL = 0A. (Continued)
OUT
300
250
200
150
100
START-UP TIME (µs)
50
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
INPUT VOLTAGE (V)
FIGURE 20. START-UP TIME vs SUPPLY VOLTAGE
300
250
200
150
100
START-UP (µs)
50
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 21. START-UP TIME vs TEMPERATURE
3.0
2.5
2.0
1.5
3.5
2.5
2.0
1.5
1.0
CURRENT (A)
0.5
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
6V
2.2V
FIGURE 22. CURRENT LIMIT vs TEMPERATURE
1.0
CURRENT LIMIT (A)
0.5
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
INPUT VOLTAGE (V)
FIGURE 23. CURRENT LIMIT vs SUPPLY VOLTAGE
11
FIGURE 24. CURRENT LIMIT RESPONSE
December 21, 2009
FN6931.0
ISL80101
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, V
= 1.8V, CIN = C
OUT
= 10µF, TJ = +25°C, IL = 0A. (Continued)
OUT
FIGURE 25. LOAD TRANSIENT 0A TO 1A,
C
=10µF CERAMIC
OUT
FIGURE 27. LOAD TRANSIENT 10mA TO 1A,
C
=10µF CERAMIC
OUT
FIGURE 29. I
TRANSIENT
LINE
FIGURE 26. LOAD TRANSIENT 0A TO 1A,
C
=100µF CERAMIC
OUT
FIGURE 28. LOAD TRANSIENT 10mA TO 1A,
C
=100µF CERAMIC
OUT
90
80
70
60
50
dB
40
30
20
10
0
10 100 1k 10k 100k 1M
I
OUT
2V
2.5V
= 1A
FREQUENCY (Hz)
FIGURE 30. PSRR vs V
2.2V
IN
12
December 21, 2009
FN6931.0
ISL80101
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, V
= 1.8V, CIN = C
OUT
= 10µF, TJ = +25°C, IL = 0A. (Continued)
OUT
90
80
70
dB
60
50
40
30
20
10
0
100µF
I
= 1A
OUT
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
FIGURE 31. PSRR vs C
OUT
10
1
0.1
47µF
10µF
90
80
70
60
50
dB
40
30
20
10
0
10 100 1k 10k 100k 1M
1A
100mA
FREQUENCY (Hz)
FIGURE 32. PSRR vs LOAD
NOISE µV/⎟Hz
0.01
I
LOAD
0.001
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
FIGURE 33. SPECTRAL NOISE DENSITY vs FREQUENCY
13
December 21, 2009
FN6931.0
ISL80101
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE REVISION CHANGE
12/21/09 FN6931.0 Initial Release to web
Products
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Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL80101
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FIT s are available from our website at http://rel.intersil.com/reports/search.php
for a complete list of Intersil product families.
For additional products, see www.intersil.com/product_tree
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description o nly . In tersil Corporation reserves the right to make changes in circuit design, software and/or specifications
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Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
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14
December 21, 2009
FN6931.0
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 6, 09/09
3.00
6
PIN 1
INDEX AREA
(4X) 0.10
TOP VIEW
ISL80101
A
B
3.00
2.00
8x 0.50
1.60
BOTTOM VIEW
(4X) 0.10
0.415
0.23
0.200
6
PIN #1 INDEX AREA
1
2
10 x 0.23
10x 0.35
4
AB
C
M
4
PACKAGE
OUTLINE
(8x 0.50)
(10 x 0.55)
(10x 0.23)
1.60
TYPICAL RECOMMENDED LAND PATTERN
0.35
1.00
MAX
0.20
2.00
NOTES:
Dimensions are in millimeters.1.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
2.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
Lead width applies to the metallized terminal and is measured
4.
between 0.18mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
C
SIDE VIEW
0.20 REF
0.05
DETAIL "X"
5
SEE DETAIL "X"
0.10
C
BASE PLANE
SEATING PLANE
C
0.08
C
15
The configuration of the pin #1 identifier is optional, but must be
6.
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
December 21, 2009
FN6931.0
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