intersil ISL80101 DATA SHEET

High Performance 1A LDO

ISL80101

ISL80101

The ISL80101 ia a low-voltage, high-current, single
output LDO specified for 1A output current. This part
operates from input voltages of 2.2V to 6V and is capable
of providing output voltages of 0.8V to 5V on the
adjustable V

versions. Fixed output voltage options

OUT

available in 0.8V, 1.2V, 1.5V, 1.8V, 2.5V , 3.3V and 5V.
Other custom voltage options available upon request.

For applications that demand in-rush current less than
current limit or a longer delay for a valid V

OUT

, an
external capacitor on the soft-start pin provides
adjustment. A supply independent ENABLE signal allows
the part to be placed into a low quiescent current
shutdown mode. Sub-micron CMOS process is utilized for
this product family to deliver best in class analog
performance and overall value.

This CMOS LDO will consume significantly lower
quiescent current as a function of load over bipolar LDOs,
which translates into higher efficiency and the ability to
consider packages with smaller footprints. Quiescent
current is modestly compromised to enable leading class
fast load transient response and hence total AC
regulation band for an LDO in this category.

Applications*(see page 14)

• DSP, FPGA and µP Core Power Supplies

• Noise-Sensitive Instrumentation Systems

• Post Regulation of Switched Mode Power Supplies

• Industrial Systems

•Medical Equipment

• Telecommunications and Networking Equipment

•Servers

• Hard Disk Drives (HD/HDD)

Features

• 0.2% initial V

• Designed for 2.2V to 6V Input Supply

• Dropout Typically 130mV at 1A

• Fast Load Transient Response

• Rated Output Current Options of 1A

• Adjustable In-Rush Current Limiting

• Fixed and Adjustable V

• 58dB Typical PSRR

• Output Noise of 100µV
300kHz

•PG Feature

•1V Enable Input Threshold

• Short-Circuit Current Protection

• 1A Peak Reverse Current

• Over-Temperature Shutdown

• Any Cap Stable with Minimum 10µF Ceramic

• ±1.8% Guaranteed V
Temperature Range from -40°C to +125°C

• Available in a 10 Ld DFN Package and soon to follow
TO220-5, TO263-5 and SOT223-5

• Pb-Free (RoHS Compliant)

Accuracy

OUT

Options Available

OUT

between 300Hz to

RMS

Accuracy for Junction

OUT

Pin Configuration

December 21, 2009
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1

ISL80101

(10 LD 3X3 DFN)

TOP VIEW

VOUT
VOUT

SENSE/ADJ

1-888-INTERSIL or 1-888-468-3774

1
2
3

PG

4

GND

5

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

All other trademarks mentioned are the property of their respective owners.

VIN

10

VIN

9

NC

8

ENABLE

7

SS

6

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2009. All Rights Reserved.

ISL80101

Pin Descriptions

PIN

NUMBER PIN NAME DESCRIPTION

1, 2 VOUT Output voltage pin.

3SENSE/ADJRemote voltage sense for internally fixed V
4PGV

5GNDGND pin.
6 SS External cap controls the rate of the V
7ENABLE V
8 DNC Do not connect this pin to ground or supply. Leave floating.

9, 10 VIN Input supply pin.

in regulation signal. Logic low defines when V

OUT

if not used.

OUT

independent chip enable. TTL and CMOS compatible.

IN

options. ADJ pin for externally set V

OUT

is not in regulation. Pin should be grounded

OUT

ramp.

OUT

.

Ordering Information

VOUT

PART NUMBER

(Notes 4, 5) PART MARKING

ISL80101IRAJZ
(Note 1)

ISL80101IR08Z DZBB 0.8V -40 to +125 10 Ld 3x3 DFN L10.3x3
ISL80101IR08Z-T

(Note 2)
ISL80101IR12Z DZCB 1.2V -40 to +125 10 Ld 3x3 DFN L10.3x3
ISL80101IR12Z-T

(Note 2)
ISL80101IR15Z DZDB 1.5V -40 to +125 10 Ld 3x3 DFN L10.3x3
ISL80101IR15Z-T

(Note 2)
ISL80101IR18Z

(Note 1)
ISL80101IR25Z

(Note 1)
ISL80101IR33Z DZGB 3.3V -40 to +125 10 Ld 3x3 DFN L10.3x3
ISL80101IR33Z-T

(Note 2)
ISL80101IR50Z DZHB 5.0V -40 to +125 10 Ld 3x3 DFN L10.3x3
ISL80101IR50Z-T

(Note 2)

NOTES:

1. Add “-T” or “TK” for Tape and Reel. Please refer to TB347

2. Please refer to TB347

3. For other output voltages, contact Intersil Marketing.

4. These Intersil Pb-free plastic pac kaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 .

5. For Moisture Sensitivity Level (MSL), please see device information page for ISL80101
see techbrief TB363

DZAB ADJ -40 to +125 10 Ld 3x3 DFN L10.3x3

DZBB 0.8V -40 to +125 10 Ld 3x3 DFN L10.3x3

DZCB 1.2V -40 to +125 10 Ld 3x3 DFN L10.3x3

DZDB 1.5V -40 to +125 10 Ld 3x3 DFN L10.3x3

DZEB 1.8V -40 to +125 10 Ld 3x3 DFN L10.3x3

DZFB 2.5V -40 to +125 10 Ld 3x3 DFN L10.3x3

DZGB 3.3V -40 to +125 10 Ld 3x3 DFN L10.3x3

DZHB 5.0V -40 to +125 10 Ld 3x3 DFN L10.3x3

for details on reel specifications.

.

VOLTAGE

(Note 3) TEMP RANGE (°C)

for details on reel specifications.

PACKAGE

(Pb-Free) PKG DWG. #

. For more information on MSL please

2

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FN6931.0

ISL80101

Absolute Maximum Ratings Thermal Information

VIN relative to GND (Note 6). . . . . . . . . . . . -0.3V to +6.5V

VOUT relative to GND (Note 6) . . . . . . . . . . -0.3V to +6.5V

PG, ENABLE, SENSE/ADJ, SS

Relative to GND (Note 6) . . . . . . . . . . . . . -0.3V to +6.5V

Recommended Operating Conditions

(Notes 9, 10)

Junction Temperature Range (TJ) (Note 9) . -40°C to +125°C

VIN relative to GND . . . . . . . . . . . . . . . . . . . . . 2.2V to 6V

VOUT range. . . . . . . . . . . . . . . . . . . . . . . . . .800mV to 5V

PG, ENABLE, SENSE/ADJ, SS relative to GND . . . .0V to +6V

PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . .<10mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.

NOTES:

6. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.

is measured in free air with the component mounted on a high effective th ermal conductivity test board with “direct attach”

7. θ

JA

features. See Tech Brief TB379.

8. For θ

9. Extended operation at these conditions may compromise reliability. Exceeding these limi ts will res ult in damage.

10. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current =

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Recommended operating conditions define limits where specifications are guaranteed.

lifetime average current.

Thermal Resistance . . . . . . . . . . . . . . . . . . .θJA (°C/W)θJC (°C/W)

10 Ld DFN Package (Notes 7, 8) . . 45 4

Storage Temperature Range . . . . . . . . . . . -65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Electrical Specifications Unless otherwise noted, V

Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to Applications section of the datasheet and Tech Brief TB379.

Boldface limits apply over the operating temperature range,

-40°C to +125°C.

PARAMETER SYMBOL TEST CONDITIONS

DC CHARACTERISTICS

DC Ouput Voltage Accuracy V

Feedback Pin

OUTVOUT

V

ADJ

(ADJ Option Only)
DC Input Line Regulation ΔV

DC Output Load Regulation ΔV

ΔI

ΔV

OUT

IN

OUT

OUT

/

/

Feedback Input Current V
Ground Pin Current I

Ground Pin Current in

Q

I

SHDN

Shutdown
Dropout Voltage (Note 12) V
Output Short Circuit Current

(1A Version)
Thermal Shutdown

Temperature

DO

OCP

TSD

Options: 0.8V, 1.2V, 1.5V and 1.8V

2.2V ≤ V
Options: 2.5V, 3.3V and 5.0V

V

OUT

V

OUT

2.2V ≤V

V

+ 0.5V < V

OUT

0A < I

LOAD

= 0.5V 0.01 1 µA

ADJ

I

= 0A, 2.2V < V

LOAD

= 1A, 2.2V < V

I

LOAD

< 3.6V; 0A < I

IN

+ 0.4V ≤ V

≤ 6V, 0A < I

IN

IN

< 1A, All voltage options -1 %

ENABLE Pin = 0.2V, V

I

= 1A, V

LOAD

V

= 0V, 2.2V < V

OUT

2.2V < V

OUT

< 6V 160 °C

IN

= V

IN

≤ 6V; 0A < I

IN

LOAD

OUT

LOAD

+ 0.4V, V

≤ 1A -1.8 0.2 1.8 %

LOAD

OUT

= 1.8V, C

(Note 11) TYP

IN

MIN

= C

= 10µF, TJ = +25°C.

OUT

MAX

(Note 11) UNITS

< 1A -1.8 0.2 1.8 %

< 1A 491 500 509 mV

< 5V 1 %

< 6V 3 5 mA

IN

< 6V 5 7 mA

IN

= 6V 0.2 12 µA

IN

= 2.5V 130 212 mV

< 6V 1.75 A

IN

3

December 21, 2009

FN6931.0

ISL80101

Electrical Specifications Unless otherwise noted, V

Applications must follow thermal guidelines of the package to determine worst case junction

IN

= V

OUT

+ 0.4V, V

OUT

= 1.8V, C

IN

= C

= 10µF, TJ = +25°C.

OUT

temperature. Please refer to Applications section of the datasheet and Tech Brief TB379.

Boldface limits apply over the operating temperature range,

-40°C to +125°C. (Continued)

PARAMETER SYMBOL TEST CONDITIONS

Thermal Shutdown

TSDn

2.2V < V

< 6V 30 °C

IN

MIN

(Note 11) TYP

MAX

(Note 11) UNITS

Hysteresis (Rising Threshold)

AC CHARACTERISTICS

Input Supply Ripple
Rejection

Output Noise Voltage I

PSRR f = 1kHz, I

f = 120Hz, I

= 10mA, BW = 300Hz < f < 300kHz 100 µV

LOAD

= 1A; VIN = 2.2V 58 dB

LOAD

LOAD

= 1A; V

= 2.2V 72 dB

IN

RMS

ENABLE PIN CHARACTERISTICS

Turn-on Threshold 2.2V < V
Hysteresis

2.2V < V

(Rising Threshold)
Enable Pin Turn-on Delay C
Enable Pin Leakage Current V

OUT

= 6V, EN = 3V 1 µA

IN

< 6V 0.3 0.8 1 V

IN

+ 0.4V < 6V 10 80 200 mV

OUT

= 10µF, I

= 1A 100 µs

LOAD

ADJUSTABLE INRUSH CURRENT LIMIT CHARACTERISTICS

Current limit adjust I

I

CHG

VIN = 3.5V, EN = 0V, SS = 1V 0.5 1 1.3 mA

PD

-3.3 -2 -0.8 µA

PG PIN CHARACTERISTICS

PG Flag Threshold 75 85 92 %V

V

OUT

V

PG Flag Hysteresis 4%

OUT

PG Flag Low Voltage V
PG Flag Leakage Current V

= 2.5V, I

IN

= 6V, PG = 6V 1 µA

IN

= 500µA 100 mV

SINK

OUT

NOTES:

11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.

12. Dropout is defined by the difference in supply V
value.

and V

IN

when the supply produces a 2% drop in VOUT from its nominal

OUT

4

December 21, 2009

FN6931.0

Typical Application Diagrams

ISL80101

2.5V ± 10% 1.8V ± 1.8%
10µF

10k

(*NOTE 13)

9

10

7

6

V

IN

V

IN

ENABLE

SS

ISL80101

GN D
5

FIXED

V
V

SENSE/ADJ

OUT
OUT

PG

1
2

3

4

10µF

100k

FIGURE 1. FIXED TYPICAL APPLICATION DIAGRAM

2.5V ± 10%

10k

10µF

10

9

V

IN

V

IN

ISL80101

SE

NSE/ADJ

1

V

OUT

2

V

OUT

10µF

2.6k

1.8V ± 1.8%

100k

7

6

(*NOTE 13)

FIGURE 2. ADJUSTABLE TYPICAL APPLICATION DIAGRAM

NOTE:

13. Used when large bulk capacitance required on V

EN A B LE

SS

ADJUSTABLE

for application.

OUT

GND

5

PG

1k

4

5

December 21, 2009

FN6931.0