intersil ISL78010 DATA SHEET

®

ISL78010

Data Sheet May 30, 2007

Automotive Grade TFT-LCD Power Supply

The ISL78010 is a multiple output regulator for use in all TFT-LCD automotive applications. It features a single boost converter with an integrated 2A FET, two positive LDOs for V

and V

ON

V

generation. The boost converter can be programmed

OFF

generation, and a single negative LDO for

LOGIC

to operate in either P-mode for optimal transient response or PI-mode for improved load regulation.

The ISL78010 includes fault protection for all four channels. Once a fault is detected on either the V

BOOST

, VON or V

OFF

channels, the device is latched off until the input supply or EN is cycled. If a fault is detected on the V

LOGIC

channel, the device is latched off until the input supply is cycled. The V

channel is not affected by the EN function.

LOGIC

The ISL78010 also includes an integrated start-up sequence for V V

BOOST

LOGIC

, V

BOOST

, V

, then VON or for V

OFF

LOGIC

, and VON. The latter sequence requires a single

, V

OFF

external transistor. The timing of the start-up sequence is set using an external capacitor.

The ISL78010 comes in a 32 Ld 5x5 TQFP package and is specified for operation over a -40°C to +105°C temperature range.

Ordering Information

FN6501.0

Features

• 2A current FET

• 3V to 5V input

• Up to 20V boost output

• 1% regulation on boost output

•V

LOGIC-VBOOST-VOFF-VON

V

LOGIC-VOFF-VBOOST-VON

• Programmable sequence delay

or sequence control

• Fully fault protected

• Thermal shutdown

• Internal soft-start

• 32 Ld 5x5 TQFP packages

,

• Pb-free plus anneal available (RoHS compliant)

Applications

• All Automotive LCD Displays

Pinout

ISL78010

(32 LD 5X5 TQFP)

TOP VIEW

PART NUMBER

(Note)

ISL78010ANZ* 78010ANZ 32 Ld 5x5 TQFP Q32.5x5 *Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for

details on reel specifications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

PACKAGE

(Pb-free)

PKG.

DWG. #

NC

DELB

NC

LX

NC

DRVP

NC

SGND

EN

VDD

PG

CDLY

NC

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

NC

FBP

NC

DRVL

FBL

SGND

CINT

FBB

161514131211109

NC

DRVN

24

23

22

21

20

19

18

17

VREF

NC

PGND

NC

FBN

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL78010

Absolute Maximum Ratings (T

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V

DELB

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V

DRVP

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V

DRVN

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V

DD

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V

LX

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V

DRVL

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T

Electrical Specifications V

= +25°C) Thermal Information

A

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Ambient Operating Temperature . . . . . . . . . . . . . . .-40°C to +105°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

Maximum Continuous Junction Temperature . . . . . . . . . . . +125°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

= TC = T

J

= 5V, V

DD

+105°C temperature range, unless otherwise specified.

BOOST

= 11V, I

A

LOAD

= 200mA, V

ON

= 15V, V

OFF

= -5V, V

= 2.5V, limits over -40°C to

LOGIC

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

SUPPLY

V

S

I

Quiescent Current Enabled, LX not switching 1.7 2.5 mA

S

Supply Voltage 3 5.5 V

Disabled 750 900 µA

CLOCK

f

OSC

Oscillator Frequency 900 1000 1100 kHz

BOOST

V V

Boost Output Range 5.5 20 V

BOOST FBB

Boost Feedback Voltage TA= +25°C 1.192 1.205 1.218 V

1.188 1.205 1.222 V

V

F_FBB

V

REF

FBB Fault Trip Point 0.9 V Reference Voltage TA= +25°C 1.19 1.215 1.235 V

1.187 1.215 1.238 V

D

MAX

I

LXMAX

I

LEAK

r

DS(ON)

Maximum Duty Cycle 85 % Current Switch 2.0 A Switch Leakage Current VLX = 16V 10 µA

Switch ON-Resistance 320 mΩ Eff Boost Efficiency See curves 85 92 % I(V

) Feedback Input Bias Current Pl mode, V

FBB

ΔV

BOOST

ΔV

BOOST

ΔV

BOOST

V

CINT_T

V

ON

V

FBP

V

F_FBP

I

FBP

LDO

/ΔV /ΔI

/ΔI

BOOST

Line Regulation C

IN

Load Regulation - “P” Mode C

Load Regulation - “PI” Mode C

CINT Pl Mode Select Threshold 4.7 4.8 V

FBP Regulation Voltage I

FBP Fault Trip Point V

FBP Input Bias Current V GMP FBP Effective Transconductance V

= 4.7nF , I

INT

pin strapped to VDD,

INT

50mA < I

= 4.7nF, 50mA < IO < 250mA 0.1 %

INT

= 0.2mA, TA = +25°C 1.176 1.2 1.224 V

DRVP

I

DRVP

falling 0.82 0.87 0.92 V

FBP

= 1.35V -250 250 nA

FBP DRVP

= 1.35V 50 500 nA

FBB

= 100mA, VIN = 3V to 5.5V 0.05 %/V

OUT

3%

< 250mA

LOAD

= 0.2mA 1.172 1.2 1.228 V

= 25V, I

= 0.2mA to 2mA 50 ms

DRVP

2

FN6501.0

May 30, 2007

ISL78010

Electrical Specifications V

= 5V, V

DD

+105°C temperature range, unless otherwise specified. (Continued)

BOOST

= 11V, I

LOAD

= 200mA, V

ON

= 15V, V

OFF

= -5V, V

= 2.5V, limits over -40°C to

LOGIC

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

ΔVON/ΔI(VON)VON Load Regulation I(VON) = 0mA to 20mA -0.5 % I

DRVP

I

L_DRVP

V

OFF

V

FBN

V

F_FBN

I

FBN

LDO

DRVP Sink Current Max V

DRVP Leakage Current V

FBN Regulation Voltage I

FNN Fault Trip Point V

FBN Input Bias Current V GMN FBN Effective Transconductance V ΔV

OFF

ΔI(V

OFF

I

DRVN

I

L_DRVN

V

LOGIC

V

FBL

V

F_FBL

I

FBL

G

ML

ΔV

LOGIC

ΔI(V

LOGIC

I

DRVL

I

L_DRL

/

)

LDO

/

)

Load Regulation I(V

V

OFF

DRVN Source Current Max V

DRVN Leakage Current V

FBL Regulation Voltage I

FBL Fault Trip Point V

FBL Input Bias Current V

FBL Effective Transconductance V

Load Regulation I(V

V

LOGIC

DRVL Sink Current Max V

I

L_DRVL

= 1.1V, V

FBP

= 1.5V, V

FBP

= 0.2mA, TA = +25°C 0.173 0.203 0.233 V

DRVN

I

= 0.2mA 0.171 0.203 0.235 V

DRVN

falling 0.38 0.43 0.48 V

FBN

= 0.2V -250 250 nA

FBN

= -6V, I

DRVN

) = 0mA to 20mA -0.5 %

OFF

= 0.3V, V

FBN

= 0V, V

FBN

= 1mA, TA = +25°C 1.176 1.2 1.224 V

DRVL

I

= 1mA 1.174 1.2 1.226 V

DRVL

falling 0.82 0.87 0.92 V

FBL

= 1.35V -500 500 nA

FBL

= 2.5V, I

DRVL

) = 100mA to 500mA 0.5 %

LOGIC

= 1.1V, V

FBL

V

= 1.5V, V

FBL

= 25V 2 4 mA

DRVP

= 35V 0.1 5 µA

DRVP

= 0.2mA to 2mA 50 mS

DRVN

= -6V 2 4 mA

DRVN

= -20V 0.1 5 µA

DRVN

= 1mA to 8mA 200 mS

DRVL

= 2.5V 8 16 mA

DRVL

= 5.5V 0.1 5 µA

DRVL

SEQUENCING

t

ON

t

SS

t

DEL1

t

DEL2

I

DELB

Turn On Delay C

Soft-start Time C

Delay Between A

Delay Between VON and V

VDD

and V

OFFCDLY

DELB Pull-down Current V

= 0.22µF 30 ms

DLY

= 0.22µF 2 ms

DLY

= 0.22µF 10 ms = 0.22µF 17 ms

>0.6V 50 µA

DELB

<0.6V 1.4 mA

V

DELB

FAULT DETECTION

t

FAULT

Fault Time Out C

= 0.22µF 50 ms

DLY

OT Over-temperature Threshold 140 °C I

PG

PG Pull-down Current VPG > 0.6V 15 µA

VPG < 0.6V 1.7 mA

LOGIC ENABLE

V

HI

V

LO

I

LOW

I

HIGH

Logic High Threshold 2.3 V

Logic Low Threshold 0.8 V

Logic Low Bias Current 0.2 2 µA

Logic High Bias Current at VEN = 5V 12 18 24 µA

3

FN6501.0

May 30, 2007

ISL78010

Pin Descriptions

PIN NAME PIN NUMBER DESCRIPTION

1, 2, 4, 6, 8, 10, 12,

16, 18, 23, 32

3 DELB Open drain output for gate drive of optional V 5 LX Drain of the internal N-Channel boost FET 9 FBP Positive LDO voltage feedback input pin; regulates to 1.2V nominal

7 DRVP Positive LDO base drive; open drain of an internal N-Channel FET 11 DRVL Logic LDO base drive; open drain of an internal N-Channel FET 13 FBL Logic LDO voltage feedback input pin; regulates to 1.2V nominal

14, 27 SGND Low noise signal ground

15 DRVN Negative LDO base drive; open drain of an internal P-Channel FET 17 FBN Negative LDO voltage feedback input pin; regulates to 0.2V nominal

19, 20, 21, 22 PGND Power ground, connected to source of internal N-Channel boost FET

24 VREF Bandgap reference output voltage; bypass with a 0.1µF to SGND 25 CINT V

26 FBB Boost regulator voltage feedback input pin; regulates to 1.2V nominal 28 EN Enable pin; High = Enable; Low or floating = Disable 29 VDD Positive supply 30 PG Push-pull gate drive of optional fault protection FET; when chip is disabled or when a fault has been

31 CDLY A capacitor connected from this pin to SGND sets the delay time for start-up sequence and sets the fault

NC Not connected

integrator output; connect capacitor to SGND for PI-mode or connect to VDD for P-mode

BOOST

operation

detected, this is high

timeout time

BOOST

delay FET

Typical Performance Curves T

100

80

60

40

EFFICIENCY (%)

20

0

FIGURE 1. V

A

= 15V

VDD

0 100 200 300 400

I

(mA)

OUT

EFFICIENCY AT VIN=3V (PI-MODE)

BOOST

A

VDD

= +25°C, unless otherwise specified.

A

= 9V

= 12V

FIGURE 2. V

100

80

60

40

EFFICIENCY (%)

20

0

0 200 400 600 800

BOOST

A

VDD

A

= 9V

VDD

I

EFFICIENCY AT VIN=5V (PI-MODE)

= 15V

OUT

(mA)

A

VDD

= 12V

4

FN6501.0

May 30, 2007

ISL78010

Typical Performance Curves T

EFFICIENCY (%)

FIGURE 3. V

LOAD REGULATION (%)

FIGURE 5. V

100

80

A

= 15V

60

40

20

0

0 100 200 300 400 500

BOOST

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7 0 100 200 300 400

LOAD REGULATION AT VIN=3V (PI-MODE)

BOOST

VDD

I

(mA)

OUT

EFFICIENCY AT VIN= 3V (P-MODE)

A

= 12V

VDD

I

(mA)

OUT

VDD

A

VDD

A

= 15V

A

VDD

= 12V

= 9V

= +25°C, unless otherwise specified. (Continued)

A

= 9V

FIGURE 6. V

100

80

60

40

EFFICIENCY (%)

20

0

FIGURE 4. V

0

-0.2

-0.4

-0.6

-0.8

LOAD REGULATION (%)

-1.0

BOOST

A

0 200 400 600 800

BOOST

A

VDD

0 200 400 600 800

A

= 12V

= 15V

(mA)

VDD

= 9V

A

VDD

I

OUT

EFFICIENCY AT VIN= 5V (P-MODE)

A

= 9V

VDD

= 12V

I

OUT

LOAD REGULATION AT V

A

VDD

(mA)

= 15V

IN

= 5V (PI-MODE)

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

LOAD REGULATION (%)

-3.5

-4.0

FIGURE 7. V

0

A

= 9V

A

(mA)

VDD

= 12V

A

= 15V

VDD

0 100 200 300 400 500

I

OUT

LOAD REGULATION AT VIN= 3V (P-MODE)

BOOST

5

LOAD REGULATION (%)

FIGURE 8. V

0

-1

-2

-3

-4

-5 0 200 400 600 800

BOOST

A

= 15V

VDD

I

OUT

LOAD REGULATION AT VIN=5V (P-MODE)

A

(mA)

VDD

A

VDD

= 9V

= 12V

FN6501.0

May 30, 2007

ISL78010

Typical Performance Curves T

0.05

0.04

0.03

0.02

0.01 0

LINE REGULATION (%)

-0.01

-0.02

3.0 3.5 4.0 4.5 5.0 5.5 6.0 V

(V)

IN

FIGURE 9. V

0

-0.1

-0.2

-0.3

-0.4

-0.5

LOAD REGULATION (%)

-0.6 0 20406080

FIGURE 11. V

LINE REGULATION (PI-MODE) FIGURE 10. V

BOOST

I

(mA)

OUT

LOAD REGULATION

ON

= +25°C, unless otherwise specified. (Continued)

A

0

-0.5

-1.0

1.5

-2.0

LINE REGULATION (%)

-2.5

3.0 3.5 4.0 4.5 5.0 5.5 6.0

0

-0.2

-0.4

-0.6

-0.8

-1.0

LOAD REGULATION (%)

-1.2

-1.4 020 6080100

FIGURE 12. V

(V)

V

IN

LINE REGULATION (P-MODE)

BOOST

40

I

(mA)

OUT

LOAD REGULATION

OFF

0

-0.2

-0.4

-0.6

-0.8

-1.0

LOAD REGULATION (%)

-1.2 0 100 200 500 700

FIGURE 13. V

LOGIC

400

300

I

(mA)

OUT

LOAD REGULATION

6

600

V

BOOST

V

LOGIC

CDLY

V

REF

TIME (10ms/DIV)

FIGURE 14. START-UP SEQUENCE

C

DLY

= 220nF

FN6501.0

May 30, 2007