®
ISL78010
Data Sheet May 30, 2007
Automotive Grade TFT-LCD Power Supply
The ISL78010 is a multiple output regulator for use in all
TFT-LCD automotive applications. It features a single boost
converter with an integrated 2A FET, two positive LDOs for
V
and V
ON
V
generation. The boost converter can be programmed
OFF
generation, and a single negative LDO for
LOGIC
to operate in either P-mode for optimal transient response or
PI-mode for improved load regulation.
The ISL78010 includes fault protection for all four channels.
Once a fault is detected on either the V
BOOST
, VON or V
OFF
channels, the device is latched off until the input supply or
EN is cycled. If a fault is detected on the V
LOGIC
channel,
the device is latched off until the input supply is cycled. The
V
channel is not affected by the EN function.
LOGIC
The ISL78010 also includes an integrated start-up sequence
for V
V
BOOST
LOGIC
, V
BOOST
, V
, then VON or for V
OFF
LOGIC
, and VON. The latter sequence requires a single
, V
OFF
external transistor. The timing of the start-up sequence is set
using an external capacitor.
The ISL78010 comes in a 32 Ld 5x5 TQFP package and is
specified for operation over a -40°C to +105°C temperature
range.
Ordering Information
FN6501.0
Features
• 2A current FET
• 3V to 5V input
• Up to 20V boost output
• 1% regulation on boost output
•V
LOGIC-VBOOST-VOFF-VON
V
LOGIC-VOFF-VBOOST-VON
• Programmable sequence delay
or
sequence control
• Fully fault protected
• Thermal shutdown
• Internal soft-start
• 32 Ld 5x5 TQFP packages
,
• Pb-free plus anneal available (RoHS compliant)
Applications
• All Automotive LCD Displays
Pinout
ISL78010
(32 LD 5X5 TQFP)
TOP VIEW
PART NUMBER
(Note)
ISL78010ANZ* 78010ANZ 32 Ld 5x5 TQFP Q32.5x5
*Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for
details on reel specifications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
NC
NC
DELB
NC
LX
NC
DRVP
NC
SGND
EN
VDD
PG
CDLY
NC
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
NC
FBP
NC
DRVL
FBL
SGND
CINT
FBB
161514131211109
NC
DRVN
24
23
22
21
20
19
18
17
VREF
NC
PGND
PGND
PGND
PGND
NC
FBN
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
ISL78010
Absolute Maximum Ratings (T
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V
DELB
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
DRVP
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V
DRVN
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
DD
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V
LX
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
DRVL
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
Electrical Specifications V
= +25°C) Thermal Information
A
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . .-40°C to +105°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Continuous Junction Temperature . . . . . . . . . . . +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
= TC = T
J
= 5V, V
DD
+105°C temperature range, unless otherwise specified.
BOOST
= 11V, I
A
LOAD
= 200mA, V
ON
= 15V, V
OFF
= -5V, V
= 2.5V, limits over -40°C to
LOGIC
PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT
SUPPLY
V
S
I
Quiescent Current Enabled, LX not switching 1.7 2.5 mA
S
Supply Voltage 3 5.5 V
Disabled 750 900 µA
CLOCK
f
OSC
Oscillator Frequency 900 1000 1100 kHz
BOOST
V
V
Boost Output Range 5.5 20 V
BOOST
FBB
Boost Feedback Voltage TA= +25°C 1.192 1.205 1.218 V
1.188 1.205 1.222 V
V
F_FBB
V
REF
FBB Fault Trip Point 0.9 V
Reference Voltage TA= +25°C 1.19 1.215 1.235 V
1.187 1.215 1.238 V
D
MAX
I
LXMAX
I
LEAK
r
DS(ON)
Maximum Duty Cycle 85 %
Current Switch 2.0 A
Switch Leakage Current VLX = 16V 10 µA
Switch ON-Resistance 320 mΩ
Eff Boost Efficiency See curves 85 92 %
I(V
) Feedback Input Bias Current Pl mode, V
FBB
ΔV
BOOST
ΔV
BOOST
ΔV
BOOST
V
CINT_T
V
ON
V
FBP
V
F_FBP
I
FBP
LDO
/ΔV
/ΔI
/ΔI
BOOST
BOOST
Line Regulation C
IN
Load Regulation - “P” Mode C
Load Regulation - “PI” Mode C
CINT Pl Mode Select Threshold 4.7 4.8 V
FBP Regulation Voltage I
FBP Fault Trip Point V
FBP Input Bias Current V
GMP FBP Effective Transconductance V
= 4.7nF , I
INT
pin strapped to VDD,
INT
50mA < I
= 4.7nF, 50mA < IO < 250mA 0.1 %
INT
= 0.2mA, TA = +25°C 1.176 1.2 1.224 V
DRVP
I
DRVP
falling 0.82 0.87 0.92 V
FBP
= 1.35V -250 250 nA
FBP
DRVP
= 1.35V 50 500 nA
FBB
= 100mA, VIN = 3V to 5.5V 0.05 %/V
OUT
3%
< 250mA
LOAD
= 0.2mA 1.172 1.2 1.228 V
= 25V, I
= 0.2mA to 2mA 50 ms
DRVP
2
FN6501.0
May 30, 2007
ISL78010
Electrical Specifications V
= 5V, V
DD
+105°C temperature range, unless otherwise specified. (Continued)
BOOST
= 11V, I
LOAD
= 200mA, V
ON
= 15V, V
OFF
= -5V, V
= 2.5V, limits over -40°C to
LOGIC
PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT
ΔVON/ΔI(VON)VON Load Regulation I(VON) = 0mA to 20mA -0.5 %
I
DRVP
I
L_DRVP
V
OFF
V
FBN
V
F_FBN
I
FBN
LDO
DRVP Sink Current Max V
DRVP Leakage Current V
FBN Regulation Voltage I
FNN Fault Trip Point V
FBN Input Bias Current V
GMN FBN Effective Transconductance V
ΔV
OFF
ΔI(V
OFF
I
DRVN
I
L_DRVN
V
LOGIC
V
FBL
V
F_FBL
I
FBL
G
ML
ΔV
LOGIC
ΔI(V
LOGIC
I
DRVL
I
L_DRL
/
)
LDO
/
)
Load Regulation I(V
V
OFF
DRVN Source Current Max V
DRVN Leakage Current V
FBL Regulation Voltage I
FBL Fault Trip Point V
FBL Input Bias Current V
FBL Effective Transconductance V
Load Regulation I(V
V
LOGIC
DRVL Sink Current Max V
I
L_DRVL
= 1.1V, V
FBP
= 1.5V, V
FBP
= 0.2mA, TA = +25°C 0.173 0.203 0.233 V
DRVN
I
= 0.2mA 0.171 0.203 0.235 V
DRVN
falling 0.38 0.43 0.48 V
FBN
= 0.2V -250 250 nA
FBN
= -6V, I
DRVN
) = 0mA to 20mA -0.5 %
OFF
= 0.3V, V
FBN
= 0V, V
FBN
= 1mA, TA = +25°C 1.176 1.2 1.224 V
DRVL
I
= 1mA 1.174 1.2 1.226 V
DRVL
falling 0.82 0.87 0.92 V
FBL
= 1.35V -500 500 nA
FBL
= 2.5V, I
DRVL
) = 100mA to 500mA 0.5 %
LOGIC
= 1.1V, V
FBL
V
= 1.5V, V
FBL
= 25V 2 4 mA
DRVP
= 35V 0.1 5 µA
DRVP
= 0.2mA to 2mA 50 mS
DRVN
= -6V 2 4 mA
DRVN
= -20V 0.1 5 µA
DRVN
= 1mA to 8mA 200 mS
DRVL
= 2.5V 8 16 mA
DRVL
= 5.5V 0.1 5 µA
DRVL
SEQUENCING
t
ON
t
SS
t
DEL1
t
DEL2
I
DELB
Turn On Delay C
Soft-start Time C
Delay Between A
Delay Between VON and V
VDD
and V
OFFCDLY
OFFCDLY
DELB Pull-down Current V
= 0.22µF 30 ms
DLY
= 0.22µF 2 ms
DLY
= 0.22µF 10 ms
= 0.22µF 17 ms
>0.6V 50 µA
DELB
<0.6V 1.4 mA
V
DELB
FAULT DETECTION
t
FAULT
Fault Time Out C
= 0.22µF 50 ms
DLY
OT Over-temperature Threshold 140 °C
I
PG
PG Pull-down Current VPG > 0.6V 15 µA
VPG < 0.6V 1.7 mA
LOGIC ENABLE
V
HI
V
LO
I
LOW
I
HIGH
Logic High Threshold 2.3 V
Logic Low Threshold 0.8 V
Logic Low Bias Current 0.2 2 µA
Logic High Bias Current at VEN = 5V 12 18 24 µA
3
FN6501.0
May 30, 2007
ISL78010
Pin Descriptions
PIN NAME PIN NUMBER DESCRIPTION
1, 2, 4, 6, 8, 10, 12,
16, 18, 23, 32
3 DELB Open drain output for gate drive of optional V
5 LX Drain of the internal N-Channel boost FET
9 FBP Positive LDO voltage feedback input pin; regulates to 1.2V nominal
7 DRVP Positive LDO base drive; open drain of an internal N-Channel FET
11 DRVL Logic LDO base drive; open drain of an internal N-Channel FET
13 FBL Logic LDO voltage feedback input pin; regulates to 1.2V nominal
14, 27 SGND Low noise signal ground
15 DRVN Negative LDO base drive; open drain of an internal P-Channel FET
17 FBN Negative LDO voltage feedback input pin; regulates to 0.2V nominal
19, 20, 21, 22 PGND Power ground, connected to source of internal N-Channel boost FET
24 VREF Bandgap reference output voltage; bypass with a 0.1µF to SGND
25 CINT V
26 FBB Boost regulator voltage feedback input pin; regulates to 1.2V nominal
28 EN Enable pin; High = Enable; Low or floating = Disable
29 VDD Positive supply
30 PG Push-pull gate drive of optional fault protection FET; when chip is disabled or when a fault has been
31 CDLY A capacitor connected from this pin to SGND sets the delay time for start-up sequence and sets the fault
NC Not connected
integrator output; connect capacitor to SGND for PI-mode or connect to VDD for P-mode
BOOST
operation
detected, this is high
timeout time
BOOST
delay FET
Typical Performance Curves T
100
80
60
40
EFFICIENCY (%)
20
0
FIGURE 1. V
A
= 15V
VDD
0 100 200 300 400
I
(mA)
OUT
EFFICIENCY AT VIN=3V (PI-MODE)
BOOST
A
A
VDD
VDD
= +25°C, unless otherwise specified.
A
= 9V
= 12V
FIGURE 2. V
100
80
60
40
EFFICIENCY (%)
20
0
0 200 400 600 800
BOOST
A
VDD
A
= 9V
VDD
I
EFFICIENCY AT VIN=5V (PI-MODE)
= 15V
OUT
(mA)
A
VDD
= 12V
4
FN6501.0
May 30, 2007
ISL78010
Typical Performance Curves T
EFFICIENCY (%)
FIGURE 3. V
LOAD REGULATION (%)
FIGURE 5. V
100
80
A
= 15V
60
40
20
0
0 100 200 300 400 500
BOOST
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
0 100 200 300 400
LOAD REGULATION AT VIN=3V (PI-MODE)
BOOST
VDD
I
(mA)
OUT
EFFICIENCY AT VIN= 3V (P-MODE)
A
A
= 12V
VDD
I
(mA)
OUT
VDD
A
VDD
A
= 15V
A
VDD
VDD
= 12V
= 9V
= +25°C, unless otherwise specified. (Continued)
A
= 9V
FIGURE 6. V
100
80
60
40
EFFICIENCY (%)
20
0
FIGURE 4. V
0
-0.2
-0.4
-0.6
-0.8
LOAD REGULATION (%)
-1.0
BOOST
A
0 200 400 600 800
BOOST
A
VDD
0 200 400 600 800
A
= 12V
= 15V
(mA)
VDD
VDD
= 9V
A
VDD
I
OUT
EFFICIENCY AT VIN= 5V (P-MODE)
A
= 9V
VDD
= 12V
I
OUT
LOAD REGULATION AT V
A
VDD
(mA)
= 15V
IN
= 5V (PI-MODE)
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
LOAD REGULATION (%)
-3.5
-4.0
FIGURE 7. V
0
A
= 9V
A
(mA)
VDD
VDD
= 12V
A
= 15V
VDD
0 100 200 300 400 500
I
OUT
LOAD REGULATION AT VIN= 3V (P-MODE)
BOOST
5
LOAD REGULATION (%)
FIGURE 8. V
0
-1
-2
-3
-4
-5
0 200 400 600 800
BOOST
A
= 15V
VDD
I
OUT
LOAD REGULATION AT VIN=5V (P-MODE)
A
(mA)
VDD
A
VDD
= 9V
= 12V
FN6501.0
May 30, 2007
ISL78010
Typical Performance Curves T
0.05
0.04
0.03
0.02
0.01
0
LINE REGULATION (%)
-0.01
-0.02
3.0 3.5 4.0 4.5 5.0 5.5 6.0
V
(V)
IN
FIGURE 9. V
0
-0.1
-0.2
-0.3
-0.4
-0.5
LOAD REGULATION (%)
-0.6
0 20406080
FIGURE 11. V
LINE REGULATION (PI-MODE) FIGURE 10. V
BOOST
I
(mA)
OUT
LOAD REGULATION
ON
= +25°C, unless otherwise specified. (Continued)
A
0
-0.5
-1.0
1.5
-2.0
LINE REGULATION (%)
-2.5
3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
-0.2
-0.4
-0.6
-0.8
-1.0
LOAD REGULATION (%)
-1.2
-1.4
020 6080100
FIGURE 12. V
(V)
V
IN
LINE REGULATION (P-MODE)
BOOST
40
I
(mA)
OUT
LOAD REGULATION
OFF
0
-0.2
-0.4
-0.6
-0.8
-1.0
LOAD REGULATION (%)
-1.2
0 100 200 500 700
FIGURE 13. V
LOGIC
400
300
I
(mA)
OUT
LOAD REGULATION
6
600
V
V
BOOST
V
LOGIC
CDLY
V
REF
TIME (10ms/DIV)
FIGURE 14. START-UP SEQUENCE
C
DLY
= 220nF
FN6501.0
May 30, 2007
ISL78010
Typical Performance Curves T
V
BOOST
V
LOGIC
V
OFF
C
V
ON
FIGURE 15. START-UP SEQUENCE
DLY
= 220nF
TIME (10ms/DIV)
= +25°C, unless otherwise specified. (Continued)
A
V
BOOST_DELAY
V
LOGIC
V
OFF
ON
C
V
FIGURE 16. START-UP SEQUENCE
DLY
= 220nF
TIME (10ms/DIV)
V
= 5V
IN
= 13V
V
OUT
= 30mA
I
OUT
TIME (400ns/DIV)
FIGURE 17. LX WAVEFORM - DISCONTINUOUS MODE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.8
1.515W
1.5
(
5
T
1.2
0.9
0.6
POWER DISSIPATION (W)
0.3
0
0 25 75 100 125 15050
m
Q
m
θ
F
J
P
x
A
=
5
6
m
6
°
m
C
)
/
W
AMBIENT TEMPERATURE (°C)
FIGURE 19. PACKAGE POWER DISSIPA TION vs AMBIENT
TEMPERATURE
V
= 5V
IN
= 13V
V
OUT
= 200mA
I
OUT
TIME (400ns/DIV)
FIGURE 18. LX WAVEFORM - CONTINUOUS MODE
7
FN6501.0
May 30, 2007
ISL78010
Applications Information
The ISL78010 provide a highly integrated multiple output
power solution for TFT-LCD automotive applications. The
system consists of one high efficiency boost converter and
three linear-regulator controllers (V
with multiple protection functions. A block diagram is shown
in Figure 20. Table 1 lists the recommended components.
The ISL78010 integrates an N-Channel MOSFET boost
converter to minimize external component count and cost.
The A
VDD
, VON, V
OFF
, and V
LOGIC
independently set using external resistors. V
voltages require external charge pumps which are post
regulated using the integrated LDO controllers.
TABLE 1. RECOMMENDED TYPICAL APPLICATION
DIAGRAM COMPONENTS
DESIGNATION DESCRIPTION
C
D
11
, C2, C
1
C
, C
20
D
, D12, D
L
Q
Q
Q
Q
Q
1
1
1
2
3
4
5
10µF, 16V X7R ceramic capacitor (1206)
3
TDK C3216X7RIC106M
4.7µF, 25V X5R ceramic capacitor (1206)
31
TDK C3216X5R1A475K
1A, 20V low leakage Schottky rectifier (CASE
457-04) ON SEMI MBRM120ET3
200mA, 30V Schottky barrier diode (SOT-23)
21
Fairchild BAT54S
6.8µH, 1.3A Inductor
TDK SLF6025T-6R8M1R3-PF
-2.4, -20V P-Channel 1.8V specified
PowerTrench MOSFET (SuperSOT-3)
Fairchild FDN304P
200mA, 40V NPN amplifier (SOT-23)
Fairchild MMBT3904
200mA, 40V PNP amplifier (SOT-23)
Fairchild MMBT3906
-2A, -30V single P-Channel logic level
PowerTrench MOSFET (SuperSOT-3)
Fairchild FDN360P
1A, 30V PNP low saturation amplifier (SOT-23)
Fairchild FMMT549
, V
OFF
, and V
LOGIC
ON
output voltages are
, V
ON
OFF
)
Boost Converter
The main boost converter is a current mode PWM converter
at a fixed frequency of 1MHz, which enables the use of low
profile inductors and multi-layer ceramic capacitors. This
results in a compact, low cost power system for LCD panel
design.
The ISL78010 is designed for continuous current mode, but
it can also operate in discontinuous current mode at light
load. In continuous current mode, current flows continuously
in the inductor during the entire switching cycle in steady
state operation. The voltage conversion ratio in continuous
current mode is given by Equation 1:
A
VDD
--------------- -
V
IN
where D is the duty cycle of the switching MOSFET.
Figure 21 shows the block diagram of the boost regulator. It
uses a summing amplifier architecture consisting of GM
stages for voltage feedback, current feedback and slope
compensation. A comparator looks at the peak inductor
current cycle by cycle and terminates the PWM cycle if the
current limit is reached.
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 60kΩ is recommended.
The boost converter output voltage is determined by
Equation 2:
A
VDD
The current through the MOSFET is limited to 2A peak. This
restricts the maximum output current based on Equation 3:
I
OMAXILMT
Where ΔIL is peak to peak inductor ripple current, and is set
by Equation 4:
ΔI
1
-------------
=
1D–
R1R2+
---------------------
R
1
⎛⎞
–
⎝⎠
V
D
IN
---- -
---------
L
×=
L
f
S
×=
ΔI
--------
(EQ. 1)
V
REF
V
L
IN
---------
×=
2
V
O
(EQ. 2)
(EQ. 3)
(EQ. 4)
where f
8
is the switching frequency.
S
FN6501.0
May 30, 2007
ISL78010
VREF
SGND
FBB
CINT
VDD
PG
CDLY
DRVN
BUFFER
REFERENCE
GENERATOR
GM
AMPLIFIER
UVLO
COMPARATOR
THERMAL
SHUTDOWN
COMPENSATION
SS
+
-
SLOPE
VOLTAGE
AMPLIFIER
EN
SHUTDOWN
AND
START-UP
CONTROL
0.2V VREF
OSCILLATOR
OSC
COMP
Σ
COMPARATOR
PWM
LOGIC
CONTROLLER
CURRENT
AMPLIFIER
CURRENT
LIMIT COMPARATOR
UVLO
SS
VREF
+
-
BUFFER
CURRENT REF
+
-
EN
LX
PGND
DRVP
BUFFER
FBP
DELB
DRVL
BUFFER
FBN
0.4V
COMPARATOR
UVLO
FBL
UVLO
COMPARATOR
FIGURE 20. BLOCK DIAGRAM
9
FN6501.0
May 30, 2007
FBB
COMPENSATION
IFB
IREF
SLOPE
CURRENT
AMPLIFIER
GM
AMPLIFIER
ISL78010
CLOCK
PWM
LOGIC
SHUTDOWN
AND STARTUP
CONTROL
LX
BUFFER
IFB
IREF
VOLTAGE
AMPLIFIER
REFERENCE
GENERATOR
CINT
FIGURE 21. BLOCK DIAGRAM OF THE BOOST REGULATOR
PGND
10
FN6501.0
May 30, 2007
ISL78010
Table 2 gives typical values (margins are considered 10%,
3%, 20%, 10%, and 15%) on V
TABLE 2. TYPICAL VIN, VO, L, fS, AND I
(V) VO (V) L (µH)
V
IN
3.3 9 6.8 1 0.490686
3.3 12 6.8 1 0.307353
3.3 15 6.8 1 0.197353
5 9 6.8 1 0.743464
5 12 6.8 1 0.465686
5 15 6.8 1 0.29902
, VO, L, fS, and I
IN
OMAX
f
S
(MHz)
OMAX
VALUES
I
OMAX
(A)
:
Input Capacitor
An input capacitor is used to supply the peak charging
current to the converter. It is recommended that C
IN
be
larger than 10µF. The reflected ripple voltage will be smaller
with larger C
. The voltage rating of input capacitor should
IN
be larger than the maximum input voltage.
Boost Inductor
The boost inductor is a critical part which influences the
output voltage ripple, transient response, and efficiency.
Values of 3.3µH to 10µH are to match the internal slope
compensation. The inductor must be able to handle the
following average and peak current:
I
=
-------------
1D–
I
LAVG
I
LPKILAVG
O
ΔI
L
--------
+=
2
(EQ. 5)
(EQ. 6)
NOTE: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across them increases.
C
in Equation 7 assumes the effective value of the capacitor at a
OUT
particular voltage and not the manufacturer’s stated value, measured
at zero volts.
Compensation
The ISL78010 can operate in either P-mode or PI-mode.
P-mode may be preferred in applications where excellent
transient load performance is required but regulation is not
critical. Connecting the C
pin directly to VIN will enable
INT
P-mode; For better load regulation, use PI-mode with a
4.7nF capacitor in series with a 10k resistor between C
INT
and ground. This value may be reduced to improve transient
performance, however, very low values will reduce loop
stability . Figures 5 through 10 show a comparison of P-mode
vs PI-mode performance.
Boost Feedback Resistors
As the boost output voltage, A
effective voltage feedback in the IC increases the ratio of
voltage to current feedback at the summing comparator
because R
decreases relative to R1. To maintain stable
2
operation over the complete current range of the IC, the
voltage feedback to the FBB pin should be reduced
proportionally, as A
is reduced, by means of a series
VDD
resistor-capacitor network (R
with a pole frequency (f
) set to approximately 10kHz for C2
p
(effective) = 10µF and 4kHz for C
1
⎛⎞
⎛⎞
--------------------- -
=
R
7
⎝⎠
⎝⎠
×
0.1 R
2
-------------------------------------------------
=
C
7
2 3.142 f
1
1
-------
–
R
1
×××
pR7
1–
, is reduced below 12V the
VDD
and C7) in parallel with R1,
7
(effective) = 30µF.
2
(EQ. 8)
(EQ. 9)
Rectifier Diode
A high-speed diode is necessary due to the high switching
frequency. Schottky diodes are recommended because of
their fast recovery time and low forward voltage. The rectifier
diode must meet the output current and peak inductor
current requirements.
Output Capacitor
The output capacitor supplies the load directly and reduces
the ripple voltage at the output. Output ripple voltage
consists of two components: the voltage drop due to the
inductor ripple current flowing through the ESR of output
capacitor, and the charging and discharging of the output
capacitor.
V
RIPPLEILPK
ESR
V
O
–
V
OVIN
----------------------- -
For low ESR ceramic capacitors, the output ripple is
dominated by the charging and discharging of the output
capacitor. The voltage rating of the output capacitor should
be greater than the maximum output voltage.
11
I
O
----------------
C
OUT
1
---- -
××+×=
f
S
(EQ. 7)
PI-Mode C
(C23) and R
INT
INT
(R10)
The IC is designed to operate with a minimum C23 capacitor
of 4.7nF and a minimum C
Note that, for high voltage A
ceramic capacitors (C
(effective) = 10µF.
2
, the voltage coefficient of
VDD
) reduces their effective capacitance
2
greatly; a 16V, 10µF ceramic can drop to around 3µF at 15V.
To improve the transient load response of A
a resistor may be added in series with the C
in PI-mode,
VDD
capacitor. The
23
larger the resistor the lower the overshoot but at the expense
of stability of the converter loop - especially at high currents.
With L = 10µH, A
should have a capacitance of greater than 10µF. R
can have values up to 5kΩ for C
up to 10k for C
Larger values of R
A
load currents less than the current limit are used. To
VDD
ensure A
stability, the IC should be operated at the
VDD
= 15V, C23 = 4.7nF, C2 (effective)
VDD
(effective) up to 20µF and
(effective) up to 30µF.
2
(R7) may be possible if maximum
INT
2
INT
(R7)
maximum desired current and then the transient load
response of A
maximum value of R
should be used to determine the
VDD
INT
.
FN6501.0
May 30, 2007
ISL78010
Operation of the DELB Output Function
An open drain DELB output is provided to allow the boost
output voltage, developed at C
(See “Typical Application
2
Diagram” on page 17), to be delayed via an external switch
(Q
) to a time after the V
4
supply and negative V
BOOST
OFF
charge pump supply have achieved regulation during the
start-up sequence shown in Figures 14 and 16. This then
allows the A
instead of the normal offset voltage of V
and VON supplies to start-up from 0V
VDD
IN-VDIODE (D1
) if Q4
were not present.
When DELB is activated by the start-up sequencer, it sinks
50µA allowing a controlled turn-on of Q
C
. C16 can be used to control the turn-on time of Q4 to
9
reduce inrush current into C
by R
and R8 can be used to limit the VGS voltage of Q4 if
9
. The potential divider formed
9
and charge-up of
4
required by the voltage rating of this device. When the
voltage at DELB falls to less than 0.6V, the sink current is
increased to ~1.2mA to firmly pull DELB to 0V.
The voltage at DELB is monitored by the fault protection
circuit so that if the initial 50µA sink current fails to pull DELB
below ~0.6V after the start-up sequencing has completed,
then a fault condition will be detected and a fault time-out
ramp will be initiated on the C
capacitor (C7).
DEL
Operation of the PG Output Function
The PG output consists of an internal pull -up PMOS device to
V
, to turn-off the external Q1 protection switch and a current
IN
limited pull-down NMOS device which sinks ~15µA allowing a
controlled turn-on of Q
control how fast Q
gate capacitance. CO is used to
1
turns-on - limiting inrush current into C1.
1
When the voltage at the PG pin falls to less than 0.6V, the PG
sink current is increased to ~1.2mA to firmly pull the pin to 0V.
The voltage at PG is monitored by the fault protection circuit
so that if the initial 15µA sink current fails to pull PG below
~0.6V after the start-up sequencing has completed, then a
fault condition will be detected and a fault time-out ramp will
be initiated on the C
capacitor (C7).
DEL
Cascaded MOSFET Application
A 20V N-Channel MOSFET is integrated in the boost
regulator. For the applications where the output voltage is
greater than 20V, an external cascaded MOSFET is needed
as shown in Figure 22. The voltage rating of the external
MOSFET should be greater than V
BOOST
.
V
IN
ISL78010
FIGURE 22. CASCADED MOSFET TOPOLOGY FOR HIGH
OUTPUT VOLTAGE APPLICATIONS
Linear-Regulator Controllers (VON, V
V
)
OFF
LX
FB
LOGIC
V
BOOST
, and
The ISL78010 includes three independent linear-regulator
controllers, in which two are positive output voltage (V
and V
V
LOGIC
), and one is negative. The VON, V
LOGIC
OFF
linear-regulator controller functional diagrams,
ON
, and
applications circuits are shown in Figures 23, 24, and 25
respectively.
Calculation of the Linear Regulator Base-Emitter
Resistors (R
For the pass transistor of the linear regulator, low frequency
gain (h
in the datasheet. The pass transistor adds a pole to the loop
transfer function at f
maintain phase margin at low frequency, the best choice for
a pass device is often a high frequency low gain switching
transistor. Further improvement can be obtained by adding a
base-emitter resistor R
Block Diagrams on page 13), which increase the pole
frequency to: f
re = KT/qIc. So choose the lowest value R
as long as there is still enough base current (I
the maximum output current (I
We will take as an example the V
Fairchild FMMT549 PNP transistor is used as the external
pass transistor (Q
maximum V
sheet indicates h
The base-emitter saturation voltage is: Vbe_max = 1.25V
(note this is normally a Vbe ~ 0.7V, however, for the Q
transistor an internal Darlington arrangement is used to
increase it's current gain, giving a 'base-emitter' voltage of
2xV
(Note that using a high current Darlington PNP transistor for
Q
voltage be required, then an ordinary high gain PNP
transistor should be selected for Q
collector-emitter saturation voltage).
) and unity gain frequency (fT) are usually specified
FE
).
BE
requires that VIN > V
5
, RBP and RBN)
BL
p=fT/hFE
*(1+ hFE *re/RBE)/hFE, where
p=fT
in the application diagram) then for a
5
operating requirement of 500mA, the data
LOGIC
(min) = 100.
FE
. Therefore, in order to
(RBP, RBL, RBN in the Functional
BE
in the design
BE
).
C
linear regulator. If a
LOGIC
+ 2V. Should a lower input
LOGIC
so as to allow a lower
5
) to support
B
5
12
FN6501.0
May 30, 2007
ISL78010
For the ISL78010, the minimum drive current is:
I
min()8mA=
DRVL
The minimum base-emitter resistor, R
, can now be
BL
(EQ. 10)
calculated as:
R
min()VBEmax()I
BL
1.25V 8mA 500mA 100⁄–()⁄ 417Ω=
DRVL
min()IChFEmin()⁄–() =⁄=
(EQ. 11)
This is the minimum value that can be used - so, we now
choose a convenient value greater than this minimum value;
say 500Ω. Larger values may be used to reduce quiescent
current, however, regulation may be adversely affected, by
supply noise if R
0.9V
PG_LDOP
+
-
GMP
FIGURE 23. VON FUNCTIONAL BLOCK DIAGRAM
is made too high in value.
BL
LDO_ON
1: Np
36V
ESD
CLAMP
DRVP
FBP
+
R
BP
7kΩ
V
R
P1
R
P2
20kΩ
BOOST
Q3
LX
0.1µF
CP (TO 36V)
0.1µF
VON (TO 35V)
C
ON
OR V
V
IN
PROT
(3V TO 6V)
0.9V
PG_LDOL
FIGURE 25. V
-
+
GML
LDO_LOG
R
+
-
1: N1
FUNCTIONAL BLOCK DIAGRAM
LOGIC
500Ω
DRVL
FBL
BL
R
R
20kΩ
L1
L2
Q5
V
LOGIC
(1.3V TO 3.6V)
C
LOG
10µF
The VON power supply is used to power the positive supply
of the row driver in the LCD panel. The DC/DC consists of an
external diode-capacitor charge pump powered from the
inductor (LX) of the boost converter, followed by a low
dropout linear regulator (LDO_ON). The LDO_ON regulator
uses an external PNP transistor as the pass element. The
on-board LDO controller is a wide band (>10MHz)
transconductance amplifier capable of 4mA drive current,
which is sufficient for up to 40mA or more output current
under the low dropout condition (forced beta of 10). Typical
V
voltage supported by the ISL78010 ranges from +15V
ON
to +36V. A fault comparator is also included for monitoring
the output voltage. The undervoltage threshold is set at 25%
below the 1.2V reference.
PG_LDON
0.4V
FIGURE 24. V
-
+
GMN
-
+
CLAMP
36V
ESD
LDO_OFF
FBN
1: Nn
DRVN
R
BN
3kΩ
FUNCTIONAL BLOCK DIAGRAM
OFF
R
20kΩ
R
V
N2
N1
13
REF
Q2
0.1µF
CP (TO -26V)
V
OFF
LX
0.1µF
(TO -20V)
C
OFF
The V
power supply is used to power the negative
OFF
supply of the row driver in the LCD panel. The DC/DC
consists of an external diode-capacitor charge pump
powered from the inductor (LX) of the boost converter,
followed by a low dropout linear regulator (LDO_OFF). The
LDO_OFF regulator uses an externa l NPN tran si sto r as th e
pass element. The on-board LDO controller is a wide band
(>10MHz) transconductance amplifier capable of 4mA drive
current, which is sufficient for up to 40mA or more output
current under the low dropout condition (forced beta of 10).
Typical V
voltage supported by the ISL78010 ranges
OFF
from -5V to -20V. A fault comparator is also included for
monitoring the output voltage. The undervoltage threshold is
set at 200mV above the 0.2V reference level.
The V
power supply is used to power the logic circuitry
LOGIC
within the LCD panel. The DC/DC may be powered directly
from the low voltage input, 3.3V or 5.0V, or it may be
powered through the fault protection switch. The
LDO_LOGIC regulator uses an external PNP transistor as
the pass element. The on-board LDO controller is a wide
band (>10MHz) transconductance amplifier capable of
16mA drive current, which is sufficient for up to 160mA or
FN6501.0
May 30, 2007
)
ISL78010
more output current under the low dropout condition (forced
beta of 10). Typical V
ISL78010 ranges from +1.3V to V
voltage supported by the
LOGIC
- 0.2V. A fault
DD
comparator is also included for monitoring the output
voltage. The undervoltage threshold is set at 25% below the
1.2V reference.
Set-Up Output Voltage
Refer to the “Typical Application Diagram” on page 17, the
output voltages of V
ON
, V
OFF
, and V
are determined
LOGIC
by Equations 12, 13 and 14:
V
ONVREF
V
OFFVREFN
V
LOGICVREF
where V
REF
12
--------- -
1
+
×=
⎜⎟
R
⎝⎠
11
R
22
----------
V
R
21
R
⎛⎞
42
----------
1
+
×=
⎜⎟
R
⎝⎠
41
= 1.2V, V
REFN
–()×+=
REFNVREF
= 0.2V.
(EQ. 12)
(EQ. 13)
(EQ. 14)
R
⎛⎞
Resistor networks in the order of 250kΩ, 120kΩ and 10kΩ
are recommended for V
ON
, V
OFF
and V
LOGIC
, respectively.
Charge Pump
T o generate an output voltage higher than V
multiple stages of charge pumps are needed. The number of
stages is determined by the input and output voltage. For
positive charge pump stages:
N
POSITIVE
where V
V
OUTVCEVINPUT
--------------------------------------------------------------
≥
V
INPUT
is the dropout voltage of the pass component of
CE
–+
2V
×–
F
the linear regulator. It ranges from 0.3V to 1V depending on
the transistor. V
is the forward-voltage of the charge pump
F
rectifier diode.
The number of negative charge pump stages is given by:
N
NEGATIVE
V
OUTPUTVCE
-------------------------------------------------
≥
V
INPUT
+
2V
×–
F
To achieve high efficiency and low material cost, the lowest
number of charge pump stages which can meet the above
requirements, is always preferred.
BOOST
, single or
(EQ. 15
(EQ. 16)
High Charge Pump Output Vo ltage (>36V)
Applications
In the applications where the charge pump output voltage is
over 36V, an external NPN transistor needs to be inserted
between DRVP pin and base of pass transistor Q
in Figure 26; or the linear regulator can control only one
stage charge pump and regulate the final charge pump
output as shown in Figure 27.
as shown
3
CHARGE PUMP
V
IN
Q3
VDD
NPN
0.1µF
OUTPUT
7kΩ
Q3
0.1µF 0.1µF
0.1µF
LX
A
VDD
V
ON
V
(>36V)
0.22µF
OR A
DRVP
ISL78010
FIGURE 26. CASCODE NPN TRANSISTOR CONFIGURATION
FOR HIGH CHARGE PUMP OUTPUT VOLTAGE
(>36V)
0.1µF
DRVP
ISL78010
FBP
FIGURE 27. THE LINEAR REGULATOR CONTROLS ONE
STAGE OF CHARGE PUMP
FBP
7kΩ
0.47µF
CASCODE
TRANSISTOR
Discontinuous/Continuous Boost Operation and
its Effect on the Charge Pumps
The ISL78010 VON and V
switching edges to drive diode charge pumps from which
LDO regulators generate the V
be appreciated that should a regular supply of LX switching
edges be interrupted, for example, during discontinuous
operation at light A
VDD
affect the performance of V
depending on their exact loading conditions at the time.
To optimize V
ON/VOFF
discontinuous/continuous operation of the boost converter
can be adjusted, by suitable choice of inductor given V
V
, switching frequency and the A
OUT
be in continuous operation.
architecture uses LX
OFF
ON
and V
supplies. It can
OFF
boost load currents, then this may
ON
and V
regulation -
OFF
regulation, the boundary of
current loading, to
VDD
IN
,
ON
14
FN6501.0
May 30, 2007
ISL78010
Equation 17 gives the boundary between discontinuous and
continuous boost operation. For continuous operation (LX
switching every clock cycle) we require that:
I
load()D1D–()× VIN×>
AVDD
---------------------------------------------------------------------------------------
2Lf
××
OSC
where the duty cycle, D = (A
For example, with V
IN
= 5V , f
- VIN)/A
VDD
= 1.0MHz and A
OSC
VDD
VDD
(EQ. 17)
= 12V
we find continuous operation of the boost converter can be
guaranteed for:
L10μ H and I
L6.8μ H and I
L3.3μ H and I
AVDD
AVDD
AVDD
61mA>=
89mA>=
184mA>=
(EQ. 18)
(EQ. 19)
(EQ. 20)
Charge Pump Output Capacitors
Ceramic capacitors with low ESR are recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by Equation 21:
I
C
OUT
where f
OUT
------------------------------------------------------
≥
2V
RIPPLEfOSC
is the switching frequency.
OSC
××
(EQ. 21)
Start-Up Sequence
Figure 28 shows a detailed start-up sequence waveform. For
a successful power up, there should be six peaks at V
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
When the input voltage is higher than 2.5V, an internal
current source starts to charge C
to an upper threshold
CDLY
using a fast ramp followed by a slow ramp. During the initial
slow ramp, the device checks whether there is a fault
condition. If no fault is found, C
first peak and V
REF
turns on.
is discharged after the
CDLY
During the second ramp, the device checks the status of
V
and over-temperature. At the peak of the second
REF
ramp, PG output goes low and enables the input protection
PMOS Q
current into V
Its rate of turn on is controlled by C
. Q1 is a controlled FET used to prevent in-rush
1
BOOST
before V
is enabled internally.
BOOST
. When a fault is
o
detected, M1 will turn off and disconnect the inductor from
V
.
IN
With the input protection FET on, NODE1 (See “Typical
Application Diagram” on page 17) will rise to ~V
the boost is not enabled so V
BOOST
rises to VIN-V
through the output diode. Hence, there is a step at V
during this part of the start-up sequence. If this step is not
desirable, an external P-MOSFET can be used to delay the
. Initially
IN
DIODE
CDLY
BOOST
output until the boost is enabled internally. The delayed
output appears at A
V
soft-starts at the beginning of the third ramp. The
BOOST
soft-start ramp depends on the value of the C
For C
V
REF
of 220nF, the soft-start time is ~2ms.
DLY
and V
LOGIC
.
VDD
capacitor.
DLY
turn on when input voltage (VDD)
exceeds 2.5V. When a fault is detected, the outputs and the
input protection will turn off but V
V
turns on at the start of the fourth peak. At the fifth
OFF
will stay on.
REF
peak, the open drain o/p DELB goes low to turn on the
external PMOS Q
VON is enabled at the beginning of the sixth ramp. A
PG, V
, DELB and VON are checked at end of this ramp.
OFF
to generate a delayed V
4
BOOST
output.
VDD
,
Fault Protection
Once the start-up sequence is complete, the voltage on the
C
capacitor remains at 1.15V until either a fault is
DLY
detected or the EN pin is disabled. If a fault is detected, the
voltage on C
rises to 2.4V at which point the chip is
DLY
disabled until the power is recycled or enable is toggled.
Component Selection for Start- Up Sequencing and
Fault Protection
The C
to stabilize the V
22nF to 1µF and should not be more than five times the
capacitor on C
The C
.
range from 47nF minimum to several microfarads - only
limited by the leakage in the capacitor reaching µA levels.
C
DEL
above). Note that with 220nF on C
be typically 50ms and the use of a larger/smaller value will
vary this time proportionally (e.g. 1µF will give a fault timeout period of typically 230ms).
capacitor is typically set at 220nF and is required
REF
capacitor is typically 220nF and has a usable
DEL
should be at least 1/5 of the value of C
output. The range of C
REF
to ensure correct start-up operation.
DEL
DEL
REF
REF
the fault time-out will
is from
(See
Fault Sequencing
The ISL78010 has advanced fault detection systems which
protects the IC from both adjacent pin shorts during
operation and shorts on the output supplies.
A high quality layout/design of the PCB, in respect of
grounding quality and decoupling is necessary to avoid
falsely triggering the fault detection scheme - especially
during start-up. The user is directed to the “Layout
Recommendation” on page 17 and “Component Selection
for Start-Up Sequencing and Fault Protection” on page 15 to
avoid problems during initial evaluation and prototype PCB
generation.
15
FN6501.0
May 30, 2007
ON
ISL78010
V
V
BOOST
V
LOGIC
CDLY
V
EN
V
REF
LOGIC
, V
REF
V
IN
t
ON
PG ON
SOFT-START
VDD
A
ON
OFF
V
t
OS
SOFT-START
DELB ON
V
ON
FAULT DETECTED
CHIP DISABLED
V
OFF
DELAYED
V
BOOST
V
ON
t
DEL1
t
t
DEL3
START-UP SEQUENCE
TIMED BY C
DLY
DEL2
FIGURE 28. START-UP SEQUENCE
NORMAL
OPERATION
FAULT
PRESENT
16
FN6501.0
May 30, 2007
ISL78010
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point of +140°C, the device will shut
down.
Layout Recommendation
Device performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
2. Place V
and VDD bypass capacitors close to the pins.
REF
3. Minimize the length of traces carrying fast signals and
high current.
Typical Application Diagram
L
SGND
1
6.8µH
LX
FBB
DELB
CINT
DRVP
FBP
DRVN
FBN
PGND
V
IN
C
10
4.7µF
NODE 1
V
LOGIC
(2.5V)
C
4.7µF
Q
1
1nF
R
C64.7µF
R
C
0.1µF
41
R
43
500Ω
Q
5
31
*
5.4kΩ
NODE 1
C
C
0
1
10µF
x2
PG
C
7
0.22µF
10Ω
6
10kΩ
7
V
REF
C
22
0.1µF
R
42
R
41
5kΩ
CDELAY
VDD
EN
VREF
*
DRVL
FBL
R
10
10kΩ
V
4. All feedback networks should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point near the main
decoupling capacitors.
6. A signal ground plane, separate from the power ground
plane, should be used for ground return connections for
feedback resistor networks (R
capacitor, C22, the C
DELAY
, R11, R41) and the V
1
capacitor C7 and the
integrator capacitor C23.
7. Minimize feedback input track lengths to avoid switching
noise pick-up.
8. Connect all "NC" pins to the ground plane to improve the
thermal performance and switching noise immunity
between pins.
A demo board is available to illustrate the proper layout
implementation.
LX
D
R
REF
C
23
C
R
12
R
20kΩ
22
R
20k
1
46.5kΩ
R
5kΩ
4.7nF
1nF
P
R
13
7kΩ
230kΩ
11
R
23
3kΩ
104k
21
R
C
2-C3
OPEN
14
C
25
0.1µF D
9
1MΩ
C
0.1µF
12
21
R
2
10µF
X2
Q
Q
3
C
15
0.47µF
*
2
C
20
4.7µF
*
R7 OPEN
C
7
C
0.1µF
1
Q
4
C
16
22nF
LX
13
C
12
0.1µFD
C
24
0.1µF
R
8
10kΩ
D
LX
C
0.1µF
C
0.1µF
11
9
11
(15V)
*
V
A
(12V)
V
ON
OFF
(-5V)
VDD
REF
NOTE: SGND should be connected to PGND at one point only.
17
FN6501.0
May 30, 2007
ISL78010
Thin Plastic Quad Flatpack Packages (TQFP)
D
D1
-D-
-B-
e
A
C
M
0.09/0.16
0.004/0.006
BASE METAL
WITH PLATING
SEATING
PLANE
0.08
0.003
-C-
A-B
S
D
S
b
b1
0.09/0.20
0.004/0.008
E
E1
GAGE
PLANE
0o-7
-A-
PIN 1
-H-
0.08
0.003
o
0.020
MIN
0.008
0o MIN
L
0.25
o
0.010
11o-13
11o-13
A2
A1
o
Q32.5x5 (JEDEC MS-026AAA ISSUE B)
32 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE
MILLIMETERS
SYMBOL
A - 1.20 -
A1 0.05 0.15 -
A2 0.95 1.05 -
b 0.17 0.27 6
b1 0.17 0.23 -
D 6.90 7.10 3
D1 4.90 5.10 4, 5
E 6.90 7.10 3
E1 4.90 5.10 4, 5
L 0.45 0.75 -
N327
e0.50 BSC-
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane .
4. Dimensions D1 and E1 to be determined at datum plane .
5. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm (0.010 inch) per side.
6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch).
7. “N” is the number of terminal positions.
NOTESMIN MAX
Rev. 0 2/07
-C-
-H-
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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18
FN6501.0
May 30, 2007
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