intersil ISL6722A DATA SHEET

®

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ISL6722A, ISL6723A

Data Sheet FN9237.1July 11, 2007

Flexible Single Ended Current Mode PWM Controllers

The ISL6722A and the ISL6723A are low power, single-ended pulse width modulating (PWM) current mode controllers designed for a wide range of DC/DC conversion applications including boost, flyback, and isolated output configurations. Similar to, and pin compatible with the ISL6721, the ISL6722A and ISL6723A offer a modified feature set. The ISL6722A replaces external synchronization with a low power SLEEP feature that reduces standby current to under 200µA. The ISL6723A changes the supply voltage UVLO threshold to 13V. Additionally, the internal over temperature protection has been removed in both controllers. Other features remain the same and include a low power mode during overvoltage and overcurrent shutdown faults where the supply current drops to 200µA. An internal 300ms delay timer prevents rapid “hiccup” behavior when a shutdown fault does occur.

This advanced BiCMOS design features low operating current, adjustable operating frequency up to 1MHz, and adjustable soft-start.

Pinouts

ISL6722A, ISL6723A (16 LD SOIC, TSSOP)

GATE

ISENSE

SYNC/SLEEP

SLOPE

UV

OV

1 2 3

SLOPE

4 5

UV

6

OV

7

RTCT

8

ISET

ISL6722A (16 LD QFN)

ISENSE

GATE

15

16 14 13

1

2

3

4

6578

ISET

RTCT

VC

FB

16 15 14 13 12

11 10 9

PGND

12

11

10

9

COMP

VC PGND VCC VREF LGND SS COMP FB

VCC

VREF

LGND

SS

Features

• 1A MOSFET Gate Driver

• 100µA Start-up Current

• Fast Transient Response with Peak Current Mode Control

• Adjustable Switching Frequency up to 1MHz

• Low Power Sleep Mode (ISL6722A)

• Low Power Shutdown Mode

• Delayed Restart from OV and OC Shutdown Faults

• Adjustable Slope Compensation

• Adjustable Soft-Start

• Adjustable Overcurrent Shutdown Delay

• Adjustable UV and OV Monitors

• Leading Edge Blanking

• 1% Tolerance Voltage Reference

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Telecom and Datacom Power

• Wireless Base Station Power

• File Server Power

• Industrial Power Systems

• Isolated Buck and Flyback Regulators

• Boost Regulators

Ordering Information

PART

NUMBER*

(Note)

ISL6722AABZ 6722AABZ -40 to +105 16 Ld SOIC M16.15 ISL6723AABZ 6723AABZ -40 to +105 16 Ld SOIC M16.15 ISL6722AAVZ 6722AAVZ -40 to +105 16 Ld TSSOP M16.173

ISL6722AARZ 22AZ -40 to +105 16 Ld QFN L16.3x3B *Add “-T” suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

TEMP.

RANGE (°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6722A, ISL6723A

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Functional Block Diagram (ISL6722A)

V

CC

LGND

SLEEP

ISET

ISENSE

SLOPE

COMP

VFB

V

REF

START/STOP

UV COMPARATOR

+

-

+

BG

-

0.8

5k

VREF

SS

+

-

+

-

2.5V

53µA

0.1

SS CLAMP

ERROR

AMPLIFIER

+

-

+

S

+

-

100mV

ENABLE

RESTART

5V

DELAY

OC DETECT

+

OVERCURRENT

COMPARATOR

1/3

PWM

VOLTAGE CLAMP

+

-

100ns

BLANKING

SS CHARGE

SS CHARGED

START

OVERCURRENT

SHUTDOWN

DELAY

FAULT

LATCH

SRQ

SET DOMINANT

VREF

UV COMPARATOR

4.65V

-

+

BG

OC

FAULT

OC

SS LOW

COMPARATOR

Q

-

+

-

4.375V

SS DCHG

SS CHGSHTDN

-

+

VREF

SOFT-START

CHARGE

CURRENT

25µA

-

+

-

+

270mV

70µA

ON

VREF

SS

15µA

20k

30k

VREF

3.0V/ 12k

1.5V

OSCILLATOR

COMPARATOR

1mA

ON

+

-

+

2.50V

-

+

BLANKING

ON

+

SRQ R

Q

COMPARATOR

3.0V

-

+

-

+

36k

+

1.45V

OV

UV

V

C

GATE

PGND

2

FN9237.1

July 11, 2007

ISL6722A, ISL6723A

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Functional Block Diagram (ISL6723A)

VCC

LGND

ISET

ISENSE

SLOPE

COMP

VFB

VREF

START/STOP

UV COMPARATOR

+

-

+

BG

-

RESTART

0.8

5k

VREF

SS

SS CLAMP

+

-

+

-

2.5V

53µA

0.1

AMPLIFIER

+

S

+

ERROR

+

-

+

-

100mV

5V

1%

ENABLE

DELAY

OC DETECT

+

OVERCURRENT

COMPARATOR

1/3

PWM

+

-

BLANKING

SS CHARGE

VOLTAGE CLAMP

START

100nS

SS CHARGED

OVERCURRENT

SHUTDOWN

SET DOMINANT

VREF

UV COMPARATOR

4.65V

-

+

OC

DELAY

FAULT LATCH

SRQ

Q

FAULT

SS LOW

-

+

BG

OC

SS LOW

COMPARATOR

+

-

+

VREF

-

+

4.375V

SS DCHG

SS CHGSHTDN

270mV

SOFT-START

CHARGE

CURRENT

25µA

ON

-

+

70µA

ON

VREF

SS

15µA

RTCT

4V

2V

SYNC

20k

30k

VREF

3.0V/

1.5V

OSCILLATOR

COMPARATOR

1mA

ON

100

12k

+

-

+

2.50V

-

+

BLANKING

ON

+

-

+

4.5k

BI-DIRECTIONAL

SYNCHRONIZATION

OSC IN CLK OUT

NO EXT SYNC

EXT SYNC BLANKING

SYNC IN SYNC OUT

VREF

SRQ

Q

COMPARATOR

3.0V

-

+

-

+

1.45V

36k

OV

UV

VC

GATE

PGND

3

FN9237.1

July 11, 2007

Typical Application - 48V Input Dual Output Flyback, 3.3V @ 2.5A, 1.8V @ 1.0A

www.BDTIC.com/Intersil

P9

VIN+

4

R1

36V TO 75V

C1

R2

R24

C2

C3

C18

C5

CR6

TP1

Q1

T1

ISOLATION

XFMR

CR2

C6

C17

CR5

R21

CR4

C19 C22

SP1 SP2

+

C21

+

R16

U2

C15 C16

+

C20

R17

R19

C14

R18

+3.3V

+1.8V

RETURN

ISL6722A, ISL6723A

R4

VIN-

R25

Q2

D1

TP3

SLEEP

R5

R6

D2

Q3

R8

July 11, 2007

VR1

FN9237.1

R7

TP5

C7

R9

R23

C4

C8

R3

R10

R11

R22

TP2

GATE ISENSE SLEEP SLOPE UV

OV RTCT

ISET

R12

U4

ISL6722A

PGND

VCC

VREF

LGND

COMP

VFB

R15

U3

VC

SS

R26

R27

C9

R13

C13

R20

R14

TP4

C12

C11

C10

ISL6722A, ISL6723A

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Absolute Maximum Ratings Thermal Information

Supply Voltage, V

GATE. . . . . . . . . . . . . . . . . GND -0.3V to Gate Output Limit Voltage

PGND to LGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V

VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5.3V

Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF

Peak GATE Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A

Operating Conditions

Temperature Range

ISL6722AAxZ . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C

ISL6723AAxZ . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C

Supply Voltage Range (Typical). . . . . . . . . . . . . . . 9VDC to 18VDC

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1. θ

JA

Tech Brief TB379.

2. For θ

3. All voltages are with respect to GND.

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

UNDERVOLTAGE LOCKOUT

START Threshold (ISL6722A) SLEEP = 0V 7.95 8.25 8.55 V START Threshold (ISL6723A) 12.4 13.0 13.4 V STOP Threshold 7.40 7.70 8.20 V Hysteresis (ISL6722A) 0.50 0.55 1.00 V Hysteresis (ISL6723A) 4.00 5.00 6.00 V Start-Up Current, I OC/OV Fault Operating Current, I Operating Current, I Operating Supply Current, I

REFERENCE VOLTAGE

Overall Accuracy Line, load, T

Long Term Stability T Fault Voltage 4.50 4.65 4.75 V VREF Good Voltage 4.65 4.80 4.95 V Hysteresis 75 165 250 mV Operational Current -10 - - mA Current Limit -20 - - mA

CURRENT SENSE

Input Impedance -5-kΩ Offset Voltage 0.08 0.10 0.11 V Input Voltage Range 0-1.5V

. . . . . . . . . . . . . . . . .GND -0.3V to +20.0V

CC, VC

schematic. 9V < V Typical values are at T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

CC

C

= VC < 20V, Rt = 11kΩ, Ct = 330pF, TA = -40°C to +105°C (Note 4),

CC

= +25°C

A

VCC < START Threshold - 100 175 μA

Includes 1nF GATE loading - 8.0 12.0 mA

Line, load, T

= +125°C, 1000 hours (Note 6) - 5 - mV

A

A A

Thermal Resistance (Typical) θ

16 Lead QFN (Note 1, 2) . . . . . . . . . . . 52 4

16 Lead SOIC (Note 1) . . . . . . . . . . . . 80 N/A

16 Lead TSSOP (Note 1). . . . . . . . . . . 105 N/A

Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

- 200 300 μA

- 4.5 10.0 mA

= 0°C to +105°C = -40°C to +105°C

4.95

4.90

5.00

(°C/W) θJC (°C/W)

JA

5.05

V

5

FN9237.1

July 11, 2007

ISL6722A, ISL6723A

www.BDTIC.com/Intersil

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

schematic. 9V < V Typical values are at T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Blanking Time (Note 6) 30 60 100 ns Gain, A

CS

ERROR AMPLIFIER

Open Loop Voltage Gain (Note 6) 60 90 - dB Gain-Bandwidth Product (Note 6) - 15 - MHz Reference Voltage Initial Accuracy V Reference Voltage V COMP to PWM Gain, A COMP to PWM Offset COMP = 4V 0.51 0.75 0.88 V FB Input Bias Current V COMP Sink Current COMP = 1.5V, VFB = 2.7V 2 6 - mA COMP Source Current COMP = 1.5V, V COMP VOH V COMP VOL V PSRR Frequency = 120Hz (Note 6) 60 80 - dB SS Clamp, V

OSCILLATOR

Frequency Accuracy 289 318 347 kHz Frequency Variation with VCC T

Temperature Stability (Note 6) - 8 - % Maximum Duty Cycle (Note 7) 68 75 81 % Comparator High Threshold - 3.00 - V Comparator High Threshold w/Ext. SYNC (ISL6723A) (Note 6) - 4.00 - V Comparator Low Threshold - 1.50 - V Discharge Current T

SOFT-START

Charging Current SS = 2V -40 -55 -70 μA Charged Threshold Voltage 4.26 4.50 4.74 V Initial Overcurrent Discharge Current Sustained OC Threshold

Overcurrent Shutdown Threshold Voltage Charged Threshold minus,

Fault Discharge Current SS = 2V 0.25 1.0 - mA Reset Threshold Voltage T

COMP

= VC < 20V, Rt = 11kΩ, Ct = 330pF, TA = -40°C to +105°C (Note 4),

CC

= +25°C (Continued)

A

V

= 0V, VFB = 2.3V,

SLOPE

= 0.35V, 1.5V

V

ISET

A

= ΔISET/ΔISENSE

CS

= COMP, TA = +25°C (Note 6) 2.465 2.515 2.565 V

FB

= COMP 2.44 2.515 2.590 V

FB

COMP = 4V, TA = +25°C 0.31 0.33 0.35 V/V

= 0V -2 0.1 2 μA

FB

= 2.3V -0.25 -0.5 - mA

FB

= 2.3V 4.25 4.4 5.0 V

FB

= 2.7V 0.4 0.8 1.2 V

FB

SS = 2.5V, VFB = 0V, ISET = 2V 2.4 2.5 2.6 V

= +105°C (f

A

TA = -40°C (f

= 0°C to +105°C

A

T

= -40°C to +105°C

A

< SS < Charged Threshold

= +25°C

T

A

= +25°C 0.22 0.27 0.31 V

A

20V

- f9V)/f

9V

0.77 0.79 0.81 V/V

-223 3

0.75

0.70

30 40 55 μA

0.110 0.125 0.140 V

1.0

1.2

%

mA

6

FN9237.1

July 11, 2007

ISL6722A, ISL6723A

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Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

schematic. 9V < V Typical values are at T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SLOPE COMPENSATION

Charge Current SLOPE = 2V, T

Slope Compensation Gain Fraction of slope voltage added to

Discharge Voltage V

GATE OUTPUT

Gate Output Limit Voltage V

Gate VOH V

Gate VOL GATE - PGND, IOUT = 150mA

Peak Output Current V

Output “Faulted” Leakage V Rise Time V

Fall Time V

Minimum ON time ISET = 0.5V; V

OVERCURRENT PROTECTION

Minimum ISET Voltage - - 0.35 V Maximum ISET Voltage 1.2 - - V ISET Bias Current V Restart Delay T

OV AND UV VOLTAGE MONITOR

Overvoltage Threshold 2.4 2.5 2.6 V Undervoltage Fault Threshold 1.38 1.45 1.52 V Undervoltage Clear Threshold 1.41 1.53 1.62 V Undervoltage Hysteresis Voltage 20 50 100 mV UV Bias Current V OV Bias Current V

SLEEP (ISL6722A)

SLEEP Input Threshold Voltage Active High 1.4 - 2.7 V SLEEP Input Current V

@ SLEEP VCC = 15V - 175 210 μA

I

CC

= VC < 20V, Rt = 11kΩ, Ct = 330pF, TA = -40°C to +105°C (Note 4),

CC

= +25°C (Continued)

A

= 0 to +105°C

= -40°C to +105°C

T

A

I

SENSE

Fraction of slope voltage added to I

SENSE

RTCT

= 20V, C

C

= 0mA

I

OUT

- GATE, VC = 10V,

C

I

= 150mA

OUT

= 20V, C

C

(Note 6)

= 20V, UV = 0V, GATE = 2V 1.2 2.6 - mA

C

= 20V, C

C

1V < GATE < 9V

= 20V, C

C

1V < GATE < 9V

ISENSE to GATE w/10:1 Divider RTCT = 4.75V through 1kΩ (Note 6)

= 1.00V -1.0 - 1.0 μA

ISET

= +25°C 150 295 445 ms

A

= 2.00V -1.0 - 1.0 μA

UV

= 2.00V -1.0 - 1.0 μA

OV

SLEEP

A

, TA = +25°C

(Note 4)

= 4.5V - 0.1 0.2 V

= 1nF,

GATE

IOUT = 10mA

= 1nF

GATE

= 1nF

GATE

= 1nF

GATE

= 0V; VC = 11V

FB

= 4.0V 11 25 46 μA

-45

-41

0.097 - 0.103 V/V

0.082 - 0.118 V/V

11.0 13.5 16.0 V

-1.52.2V

-1.2

-1.0- A

-60100ns

-1540ns

--110ns

-53

0.6

-65

1.5

0.8

μA

V

7

FN9237.1

July 11, 2007

ISL6722A, ISL6723A

www.BDTIC.com/Intersil

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

schematic. 9V < V Typical values are at T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SYNCHRONIZATION (ISL6723A)

Input High Threshold --2.5V Input Pulse Width 25 - - ns Input Frequency Range (Note 6) 0.65 x Free

Input Impedance -4.5-kΩ VOH R VOL R SYNC Advance SYNC rising edge to GATE falling

Output Pulse Width C

NOTES:

4. Specifications at -40°C and +105°C are guaranteed by +25°C test with margin limits.

5. This is the V

current consumed when the device is active but not switching. Does not include gate drive current.

CC

6. Limits should be considered typical and are not production tested.

7. This is the maximum duty cycle achievable using the specified values of RT and CT . Larger or smal ler maximum duty cycles may be obtained using other values for RT and CT. See Equations 1 through 4.

= VC < 20V, Rt = 11kΩ, Ct = 330pF, TA = -40°C to +105°C (Note 4),

CC

= +25°C (Continued)

A

-1.0MHz

Running

= 4.5kΩ 2.5 - - V

LOAD

= open - - 0.1 V

LOAD

-2555ns

edge, C

SYNC

= C

GATE

= 100pF 50 - - ns

SYNC

= 100pF

Typical Performance Curves

1.002

1.000

0.998

0.995

0.993

NORMALIZED EA REFERENCE

0.991

-40 -10 20 50 80 110 TEMPERATURE (°C)

FIGURE 1. EA REFERENCE VOLTAGE vs TEMPERATURE

1.002

0.996

0.989

0.983

0.976

NORMALIZED FREQUENCY

0.970

-40 -10 20 50 80 110 TEMPERATURE (°C)

1.002

1.000

0.998

0.995

0.993

NORMALIZED VREF

0.991

FIGURE 2. V

1000

100

FREQUENCY (kHz)

10

10 20 30 40 50 60 70 80 90 100

-40 -10 20 50 80 110

REFERENCE VOLTAGE vs TEMPERATURE

REF

CT = 680pF

CT = 2200pF

TEMPERATURE (°C)

CT = 220pF

RT (kΩ)

CT = 100pF

CT = 330pF

CT = 470pF

CT = 1000pF

FIGURE 3. OSCILLATOR FREQUENCY vs TEMPERATURE FIGURE 4. CAPACITANCE vs FREQUENCY

8

FN9237.1

July 11, 2007