intersil ISL6721 DATA SHEET

®

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ISL6721

Data Sheet March 5, 2008

Flexible Single-ended Current Mode PWM Controller

The ISL6721 is a low power, single-ended pulse width modulating (PWM) current mode controller designed for a wide range of DC/DC conversion applications including boost, flyback, and isolated output configurations. Peak current mode control effectively handles power transients and provides inherent overcurrent protection. Other features include a low power mode where the supply current drops to less than 200µA during overvoltage and overcurrent shutdown faults.

This advanced BiCMOS design features low operating current, adjustable operating frequency up to 1MHz, adjustable soft-start, and a bi-directional SYNC signal that allows the oscillator to be locked to an external clock for noise sensitive applications.

Ordering Information

PART

NUMBER

ISL6721AB* ISL6721AB -40 to +105 16 Ld SOIC

ISL6721ABZ* (Note)

ISL6721AV* ISL67 21AV -40 to +105 16 Ld TSSOP

ISL6721AVZ* (Note)

*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

6721ABZ -40 to +105 16 Ld SOIC

ISL67 21AVZ -40 to +105 16 Ld TSSOP

TEMP

RANGE (°C) PACKAGE

(150 mil)

(150 mil) (Pb-Free)

(4.4mm)

(4.4mm) (Pb-free)

PKG.

DWG. #

M16.15

M16.173

FN9110.6

Features

• 1A MOSFET Gate Driver

• 100µA Startup Current

• Fast Transient Response with Peak Current Mode Control

• Adjustable Switching Frequency up to 1MHz

• Bi-directional Synchronization

• Low Power Disable Mode

• Delayed Restart from OV and OC Shutdown Faults

• Adjustable Slope Compensation

• Adjustable Soft-start

• Adjustable Overcurrent Shutdown Delay

• Adjustable UV and OV Monitors

• Leading Edge Blanking

• Integrated Thermal Shutdown

• 1% Tolerance Voltage Reference

• Pb-Free Available (RoHS Compliant)

Applications

• Telecom and Datacom Power

• Wireless Base Station Power

• File Server Power

• Industrial Power Systems

• Isolated Buck and Flyback Regulators

• Boost Regulators

Pinout

ISL6721

(16 LD SOIC, TSSOP)

TOP VIEW

GATE

ISENSE

SYNC

SLOPE

UV OV

RTCT

ISET

1 2 3 4 5 6 7 8

16 15 14 13 12

11 10 9

VC PGND VCC VREF LGND SS COMP FB

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Functional Block Diagram

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ISL6721

VCC

LGND

ISET

ISENSE

SLOPE

COMP

VFB

VREF

START/STOP

UV COMPARATOR

+

-

+

BG

-

0.8

5k

VREF

SS

+

-

+

-

2.5V

53µA

0.1

SS CLAMP

ERROR

AMPLIFIER

+

-

+

S

+

-

100mV

ENABLE

PROTECTION

RESTART

5V

1%

THERMAL

DELAY

-

OC DETECT

+

OVERCURRENT

COMPARATOR

1/3

PWM

+

-

BLANKING

SS CHARGE

VOLTAGE CLAMP

SS CHARGED

Q Q

50µs

RETRIGGERABLE

ONE SHOT

100ns

START

OVERCURRENT

SHUTDOWN

DELAY

FAULT LATCH

SRQ

Q

SET DOMINANT

VREF

UV COMPARATOR

4.65V

-

+

SRQ

OC LATCH

SS LOW

COMPARATOR

-

+

BG

SOFT-START

CHARGE

CURRENT

-

+

VREF

-

+

4.375V

270mV

25µA

-

+

-

Q

70µA

ON

VREF

SS

15µA

RTCT

SYNC

4V

2V

20k

30k

VREF

3.0V 12k

1.5V

OSCILLATOR

COMPARATOR

1mA

ON

100k

+

-

+

2.50V

36k

-

+

1.45V

BLANKING

COMPARATOR

ON

+

-

+

4.5k

BI-DIRECTIONAL

SYNCHRONIZATION

OSC IN CLK OUT

NO EXT SYNC

EXT SYNC BLANKING

SYNC IN SYNC OUT

VREF

SRQ

Q

3.0V

-

+

-

+

OV

UV

VC

GATE

PGND

2

FN9110.6

March 5, 2008

ISL6721

www.BDTIC.com/Intersil

Typical Application - 48V Input Dual Output Flyback, 3.3V @ 2.5A, 1.8V @ 1.0A

SP1 SP2

CR5

T1

VIN+

SYNC

VIN-

P9

36-75V

ISOLA T IO N

XFMR

R24

C2

R1

C1

R2

R5

R6

Q3

VR1

C3

R25

Q2

D2

R8

R7

C18

CR2

C5

CR6

TP1

Q1

R4

D1

TP3

R9

R3

R23

C4 U4

TP5

C7

R10

C8

R22

TP2

V

GATE ISENSE SYNC

SLOPE UV OV

RTCT ISET

R11

C

PGND

V

CC

ISL6721

VREF LGND

SS

COMP

VFB

R12

R21

CR4

C17

C6

R26

C21

C15 C16

++

C19

R27

R13

C22

+

R16

U2

C9

R17

R19

R15

U3

+3.3V

+1.8V

+

C20

RETURN

R18

C14

C13

R20

R14

TP4

C12

C11

C10

3

FN9110.6

March 5, 2008

ISL6721

www.BDTIC.com/Intersil

Typical Boost Converter Application Schematic

VIN+

C1

L1

R4

Q1

R1

R2

CR1

R12 C12

R3

+VOUT

+

C2

C3

RETURN

R8

C11

VIN-

R5

C9

C4

R11

C8

R7

U1

GATE

PGND

ISENSE

VCCSYNC

SLOPE

VREF

ISL6721

UV

LGND

OV RTCT ISET VFB

R6

SS

COMP

VIN+

VC

C7

C6

C5

R10

C10

R9

4

FN9110.6

March 5, 2008

ISL6721

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage, V

GATE. . . . . . . . . . . . . . . . GND - 0.3V to Gate Output Limit Voltage

PGND to LGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V

VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5.3V

Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF

Peak GATE Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A

Operating Conditions

Temperature Range

ISL6721Ax . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C

Supply Voltage Range (Typical, Note 2) . . . . . . . . 9VDC to 18VDC

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

NOTES:

1. θ

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2. All voltages are with respect to GND.

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

UNDERVOLTAGE LOCKOUT

START Threshold 7.95 8.25 8.55 V STOP Threshold 7.40 7.70 8.20 V Hysteresis 0.50 0.55 1.00 V Start-Up Current, I OC/OV Fault Operating Current, I Operating Current, I Operating Supply Current, I

REFERENCE VOLTAGE

Overall Accuracy Line, load, 0°C to +105°C 4.95 5.00 5.05 V

Long Term Stability T Fault Voltage 4.50 4.65 4.75 V VREF Good Voltage 4.65 4.80 4.95 V Hysteresis 75 165 250 mV Operational Current -10 - - mA Current Limit -20 - - mA

CURRENT SENSE

Input Impedance -5-kΩ Offset Voltage 0.08 0.10 0.11 V Input Voltage Range 0-1.5V Blanking Time (Note 5) 30 60 100 ns Gain, A

CS

. . . . . . . . . . . . . . . . .GND -0.3V to +20.0V

CC, VC

schematic on page 2 and page 3. 9V < V Typical values are at T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

CC

C

= +25°C.

A

VCC < START Threshold - 100 175 µA

Includes 1nF GATE loading - 8.0 12.0 mA

Line, load, -40°C to +105°C 4.90 5.00 5.05 V

= +125°C, 1000 hours (Note 5) - 5 - mV

A

V

= 0V, VFB = 2.3V,

SLOPE

V

= 0.35V, 1.5V

ISET

= ΔISET/ΔISENSE

A

CS

Thermal Resistance (Typical, Note 1) θ

16 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

16 Ld TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

= VC < 20V, RT = 11kΩ, Ct = 330 pF, TA = -40 to +105°C (Note 3),

CC

- 200 300 µA

- 4.5 10.0 mA

0.77 0.79 0.81 V/V

(°C/W)

JA

5

FN9110.6

March 5, 2008

ISL6721

www.BDTIC.com/Intersil

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

schematic on page 2 and page 3. 9V < V Typical values are at T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ERROR AMPLIFIER

Open Loop Voltage Gain (Note 5) 60 90 - dB Gain-Bandwidth Product (Note 5) - 15 - MHz Reference Voltage Initial Accuracy V Reference Voltage V COMP to PWM Gain, A COMP to PWM Offset COMP = 4V (Note 5) 0.51 0.75 0.88 V FB Input Bias Current V COMP Sink Current COMP = 1.5V, V COMP Source Current COMP = 1.5V, VFB = 2.3V -0.25 -0.5 - mA COMP VOH V COMP VOL V PSRR Frequency = 120Hz (Note 5) 60 80 - dB SS Clamp, V

OSCILLATOR

Frequency Accuracy 289 318 347 kHz Frequency Variation with V

Temperature Stability (Note 5) - 8 - % Maximum Duty Cycle (Note 6) 68 75 81 % Comparator High Threshold - Free Running - 3.00 - V Comparator High Threshold - with External SYNC (Note 5) - 4.00 - V Comparator Low Threshold - 1.50 - V Discharge Current 0°C to +105°C

SYNCHRONIZATION

Input High Threshold --2.5V Input Pulse Width 25 - - ns Input Frequency Range (Note 5) 0.65 x Free

Input Impedance -4.5-kΩ VOH R VOL R SYNC Advance SYNC rising edge to GATE falling

Output Pulse Width C

COMP

CC

= +25°C. (Continued)

A

= COMP, TA = +25°C (Note 5) 2.465 2.515 2.565 V

FB

= COMP 2.44 2.515 2.590 V

FB

COMP = 4V, TA = +25°C 0.31 0.33 0.35 V/V

= 0V -2 0.1 2 µA

FB

= 2.3V 4.25 4.4 5.0 V

FB

= 2.7V 0.4 0.8 1.2 V

FB

SS = 2.5V, VFB = 0V, ISET = 2V 2.4 2.5 2.6 V

T = +105°C (f T = -40°C (f

-40°C to +105°C

LOAD LOAD

edge, C

SYNC

20V

= 4.5kΩ 2.5 - - V = open - - 0.1 V

= C

GATE

= 100pF 50 - - ns

= VC < 20V, RT = 11kΩ, Ct = 330 pF, TA = -40 to +105°C (Note 3),

CC

= 2.7V 2 6 - mA

FB

- f9V)/f

-f9V)/f

SYNC

9V

= 100pF

-223 3

0.75

0.70

Running

-2555ns

1.0

-1.0MHz

1.2

%

mA

6

FN9110.6

March 5, 2008

ISL6721

www.BDTIC.com/Intersil

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

schematic on page 2 and page 3. 9V < V Typical values are at T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SOFT-START

Charging Current SS = 2V -40 -55 -70 µA Charged Threshold Voltage 4.26 4.50 4.74 V Initial Overcurrent Discharge Current Sustained OC Threshold < SS <

Overcurrent Shutdown Threshold Voltage Charged Threshold minus,

Fault Discharge Current SS = 2V 0.25 1.0 - mA Reset Threshold Voltage T

SLOPE COMPENSATION

Charge Current SLOPE = 2V, 0°C to +105°C

Slope Compensation Gain Fraction of slope voltage added to

Discharge Voltage V

GATE OUTPUT

Gate Output Limit Voltage V

Gate VOH V

Gate VOL GATE - PGND, IOUT = 150mA

Peak Output Current V Output “Faulted” Leakage VC = 20V, UV = 0V, GATE = 2V 1.2 2.6 - mA Rise Time V

Fall Time V

Minimum ON time ISET = 0.5V; V

OVERCURRENT PROTECTION

Minimum ISET Voltage - - 0.35 V Maximum ISET Voltage 1.2 - - V ISET Bias Current V Restart Delay T

OV AND UV VOLTAGE MONITOR

Overvoltage Threshold 2.4 2.5 2.6 V Undervoltage Fault Threshold 1.38 1.45 1.52 V Undervoltage Clear Threshold 1.41 1.53 1.62 V

= +25°C. (Continued)

A

Charged Threshold

= +25°C

T

A

= +25°C 0.22 0.27 0.31 V

A

-40°C to +105°C

, TA = +25°C

I

SENSE

Fraction of slope voltage added to I

(Note 3)

SENSE

= 4.5V - 0.1 0.2 V

RTCT

= 20V, C

C

I

OUT

- GATE, VC = 10V,

C

I

OUT

IOUT = 10mA

= 20V, C

C

= 20V, C

C

1V < GATE < 9V

= 20V, C

C

1V < GATE < 9V

ISENSE to GATE w/10:1 Divider RTCT = 4.75V through 1kΩ (Note 5)

ISET

= +25°C 150 295 445 ms

A

GATE

= 0mA

= 150mA

GATE

FB

= 1.00V -1.0 - 1.0 µA

= VC < 20V, RT = 11kΩ, Ct = 330 pF, TA = -40 to +105°C (Note 3),

CC

30 40 55 µA

0.095 0.125 0.155 V

-45

-41

0.097 - 0.103 V/V

0.082 - 0.118 V/V

= 1nF,

= 1nF (Note 5) - 1.0 - A

= 1nF

= 0V; VC = 11V

11.0 13.5 16.0 V

-1.52.2V

-1.2

-60100ns

-1540ns

--110ns

-53

0.6

-65

1.5

0.8

µA

V

7

FN9110.6

March 5, 2008