intersil ISL6700 DATA SHEET

®

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ISL6700

Data Sheet December 29, 2004 FN9077.6

80V/1.25A Peak, Medium Frequency, Low
Cost, Half-Bridge Driver

The ISL6700 is an 80V/1.25A peak, medium frequency, low
cost, half-bridge driver IC available in 8-lead SOIC and
12-lead QFN plastic packages. The low-side and high-side
gate drivers are independently controlled and matched to
25ns. This gives the user maximum flexibility in dead-time
selection and driver protocol. Undervoltage protection on
both the low-side and high-side supplies force the outputs
low. Non-latching, level-shift translation is used to control the
upper drive circuit. Unlike some competitors, the high-side
output returns to its correct state after a momentary
undervoltage of the high-side supply.

Ordering Information

PART

NUMBER

ISL6700IB -40 to 125 8 Ld SOIC M8.15

ISL6700IBZ
(See Note)

ISL6700IR -40 to 125 12 Ld 4x4 QFN L12.4x4

ISL6700IRZ
(See Note)

Add “-T” suffix to part number for tape and reel packaging.

NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

-40 to 125 8 Ld SOIC
(Pb-free)

-40 to 125 12 Ld 4x4 QFN
(Pb-free)

M8.15

L12.4x4

Features

• Drives 2 N-Channel MOSFETs in Half-Bridge
Configuration

• Space Saving SO8 and Low R

QFN Packages

C-S

• Phase Supply Max Voltage to 80VDC

• Bootstrap Supply Max Voltage to 96VDC

• Drives 1000pF Load with Rise and Fall Times Typ. 15ns

• TTL/CMOS Compatible Input Thresholds

• Independent Inputs for Non-Half-Bridge Topologies

• No Start-Up Problems

• Low Power Consumption

• Wide Supply Range

• Supply Undervoltage Protection

• QFN Package

- Compliant to JEDEC PUB95 MO-220 QFN

- Quad Flat No Leads - Package Outline

• Pb-Free Available (RoHS Compliant)

Applications

• Telecom/Datacom Power Supplies

• Half-Bridge Converters

• Two-Switch Forward Converters

• Active Clamp Forward Converters

Pinouts

ISL6700IB (SOIC)

TOP VIEW

V

1

DD

HI

2

LI

3

V

4

SS

1

8

HB

HO

7

HS

6

LO

5

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6700IR (QFN)

TOP VIEW

VDDNC

12

HI

1

SS

V

EPAD

NC

2

LI

3

NOTE: EPAD = Exposed PAD.

Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved.

11 10

564

NC

HB

LO

9

HO

NC

8

HS

7

Application Block Diagram

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ISL6700

PWM

CONTROLLER

Functional Block Diagram

+12V

V

DD

HI

LI

CONTROL

ISL6700

V

SS

DRIVE

HI

DRIVE

LO

HB

HO

HS

LO

+48V

REFERENCE

AND

ISOLATION

SECONDARY

CIRCUIT

HB

U/V

HI

LI

V

DD

V

SS

DETECTOR

UNDERVOLTAGE

EPAD (QFN PACKAGE ONLY)

LEVEL

SHIFT

TURN-ON

DELAY

HO

HS

LO

2

FN9077.6

December 29, 2004

+12V

www.BDTIC.com/Intersil

ISL6700

+48V

+12V

PWM

FIGURE 1. TWO-SWITCH FORWARD CONVERTER

PWM

ISL6700

+48V

ISL6700

SECONDARY

CIRCUIT

ISOLATION

SECONDARY

CIRCUIT

ISOLATION

FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP

3

FN9077.6

December 29, 2004

ISL6700

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage, V

LI and HI Voltages (Note 1) . . . . . . . . . . . . . . . . -0.3V to V

Voltage on HS (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 80V

Voltage on HB (Note 1) . . . . . . . . . . . . . . . . V

Voltage on LO (Note 1) . . . . . . . . . . . . . . . . . VSS-0.3 to VDD+0.3V

Voltage on HO (Note 1) . . . . . . . . . . . . . . . . V

Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns

Maximum Recommended Operating Conditions

Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 15V

Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 75V

Voltage on HS (Note 2) . . . . . . . . . .(Repetitive Transient) -1V to 80V

Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.

NOTES:

1. All voltages referenced to V

2. Based on V
, where VHS is the magnitude of the allowable negative transient and VF is the forward voltage drop of the bootstrap diode.

V

DD+VF

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3. θ

JA

4. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the

JA

“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

(Note 1) . . . . . . . . . . . . . . . . . . . -0.3V to 16V

DD

-0.3V to VHS+V

HS

-0.3V to VHB+0.3V

HS

+7.5V to VHS+V

HS

unless otherwise specified.

SS

=15V. The magnitude of the allowable negative transient on the HS pin is a function of the VDD supply voltage. VHS<15.6V-

DD

DD

+0.3V

DD

DD

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

SOIC (Note 3) . . . . . . . . . . . . . . . . . . . 95 N/A

QFN (Note 4) . . . . . . . . . . . . . . . . . . . . 49 7

Max Power Dissipation at 25°C in Free Air (SOIC, Note 3). 1.316W
Max Power Dissipation at 25°C in Free Air (QFN, Note 4) . . 2.976W

Maximum Storage Temperature Range. . . . . . . . . . -65°C to +150°C

Maximum Junction Temperature Range . . . . . . . . . -40°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C

(SOIC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389.

Electrical Specifications V

PARAMETERS SYMBOL TEST CONDITIONS

SUPPLY CURRENTS & UNDERVOLTAGE PROTECTION

Quiescent Current I

V

DD

Operating Current I

V

DD

Operating Current I

V

DD

HB Off Quiescent Current I

HB On Quiescent Current I

HB Operating Current I

HB Operating Current I

HS Leakage Current I

VDD Rising Undervoltage Threshold V

Falling Undervoltage Threshold V

V

DD

Undervoltage Hysteresis UVHYS 0.17 0.45 0.75 0.15 0.90 V

HB Undervoltage Threshold VHBUV Referenced to HS 4.8 5.3 6.5 4.0 7.5 V

INPUT PINS: LI and HI

Low Level Input Voltage V

High Level Input Voltage V

Input Voltage Hysteresis - 100 - - - mV

Low Level Input Current I

High Level Input Current I

DD

= V

= 12V, V

HB

DD

DDO

DDO

HBL

HBH

HBO

HBO

HLK

DDUV+

DDUV-

IL

IH

= V

SS

LI = 0 or V

f = 50kHz - 2.0 2.2 - 2.5 mA

f = 500kHz - 2.5 3.0 - 4.0 mA

HI = 0 - 1.25 1.5 - 1.8 mA

HI = V

f = 50kHz, CL = 1000pF - 1.45 1.8 - 2.0 mA

f = 500kHz, CL = 1000pF - 2.4 2.8 - 3.0 mA

VHS = 80V
V

HB

Full Operating Conditions 0.8 1.6 - 0.8 - V

IL

Full Operating Conditions - 1.7 2.2 - 2.2 V

IH

V

IN

VIN = 5V, Full Operating Conditions 30 115 130 30 145 µA

= 0V, No Load on LO or HO, Unless Otherwise Specified

HS

T

T

= 25°C

J

DD

DD

= 96V

= 0V, Full Operating Conditions -70 -60 -30 -80 -30 µA

- 1.9 2.2 - 2.4 mA

- 170 240 - 250 µA

--1-1µA

6.8 7.6 8.25 6.5 8.5 V

6.5 7.1 7.8 6.25 8.1 V

J

= -40°C TO

125°C

UNITSMIN TYP MAX MIN MAX

4

FN9077.6

December 29, 2004

ISL6700

www.BDTIC.com/Intersil

Electrical Specifications V

PARAMETERS SYMBOL TEST CONDITIONS

GATE DRIVER OUTPUT PINS: LO & HO

Low Level Output Voltage V

High Level Output Voltage V

Peak Pullup Current I

Peak Pulldown Current IO-V

Switching Specifications V

PARAMETERS SYMBOL

Lower Turn-off Propagation Delay
(LI Falling to LO Falling)

Upper Turn-off Propagation Delay
(HI Falling to HO Falling)

Lower Turn-on Propagation Delay
(LI Rising to LO Rising)

Upper Turn-on Propagation Delay
(HI Rising to HO Rising)

Deadtime, (t

Deadtime, (t

Rise Time t

Fall Time t

Delay Matching: Lower Turn-On and Upper Turn-Off t

Delay Matching: Lower Turn-Off and Upper Turn-On t

HPLH

LPLH

- t

)DHt

LPHL

- t

)DLt

HPHL

= V

DD

DD

= 12V, V

HB

OL

DD-VOHIOUT

+V

O

= VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified

SS

I

OUT

= V

OUT

OUT

t

LPHL

t

HPHL

t

LPLH

t

HPLH

MON

MOFF

= 0V, No Load on LO or HO, Unless Otherwise Specified (Continued)

HS

= -40°C TO

T

T

= 25°C

J

= 0A - - 0.1 - 0.1 V

= 0A - - 0.1 - 0.1 V

= 0V - 1.4 - - - A

= 12V - 1.3 - - - A

= 25°C

T

TEST

CONDITIONS

LI, HI switched simultaneously 0 24 - 0 - ns

ON

ON

R

F

J

- 45 50 - 65 ns

- 60 75 - 90 ns

- 75 82 - 95 ns

- 70 75 - 95 ns

017- 0 - ns

-520-25ns

-520-25ns

-820-25ns

- -15 25 - 30 ns

J

125°C

T

= -40°C

J

TO 125°C

UNITSMIN TYP MAX MIN MAX

UNITSMIN TYP MAX MIN MAX

Pin Descriptions

SYMBOL DESCRIPTION

V

DD

HI Logic level input that controls the HO output.

LI Logic level input that controls the LO output.

V

SS

LO Low-side output. Connect to gate of low-side power MOSFET.

HS High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this

HO High-side output. Connect to gate of high-side power MOSFET.

HB High-side bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive

EPAD Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.

Positive supply to control logic and lower gate drivers. De-couple this pin to VSS. Connect anode of bootstrap diode to this pin.

Chip negative supply, generally will be ground.

pin.

side of bootstrap capacitor to this pin.

5

December 29, 2004

FN9077.6

Timing Diagrams

www.BDTIC.com/Intersil

ISL6700

LI

HI,

HO,

LO

HI

LI

t

HPLH

t

LPLH

FIGURE 3.

,

t

HPHL

t

LPHL

,

LO

HO

t

MON

FIGURE 4.

t

MOFF

6

FN9077.6

December 29, 2004

ISL6700

www.BDTIC.com/Intersil

Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)

L12.4x4

12 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 -

A1 - - 0.05 -

A2 - - 1.00 9

A3 0.20 REF 9

b 0.23 0.28 0.38 5, 8

D 4.00 BSC -

D1 3.75 BSC 9

D2 1.95 2.10 2.25 7, 8

E 4.00 BSC -

E1 3.75 BSC 9

E2 1.95 2.10 2.25 7, 8

e 0.80 BSC -

k0.25 - - -

L 0.35 0.60 0.75 8

L1 - - 0.15 10

N122

Nd 3 3

Ne 3 3

P- -0.609

θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.

10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.

NOTESMIN NOMINAL MAX

Rev. 1 5/03

7

FN9077.6

December 29, 2004

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

ISL6700

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45

o

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMIN MAX MIN MAX

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

8

FN9077.6

December 29, 2004